KR20010054164A - Method for forming dual sti(silicon trenched isolation) well - Google Patents

Method for forming dual sti(silicon trenched isolation) well Download PDF

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Publication number
KR20010054164A
KR20010054164A KR1019990054835A KR19990054835A KR20010054164A KR 20010054164 A KR20010054164 A KR 20010054164A KR 1019990054835 A KR1019990054835 A KR 1019990054835A KR 19990054835 A KR19990054835 A KR 19990054835A KR 20010054164 A KR20010054164 A KR 20010054164A
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South Korea
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trench
region
well
forming
insulating layer
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KR1019990054835A
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Korean (ko)
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조석원
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990054835A priority Critical patent/KR20010054164A/en
Publication of KR20010054164A publication Critical patent/KR20010054164A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A forming method of dual STI(Silicon Trench Isolation) is provided to reduce cell size by minimizing wall space. CONSTITUTION: The first and the second insulating layers are built on a semiconductor substrate(21). To define an active surface, the second insulating layer is etched selectively using an active mask, and the second isolation pattern is formed. The second isolation layer is used as a mask, the first trench and the second trench are made by etching the first insulation layer and the substrate(21). The third insulating layer is doped on the whole the substrate. In the sidewall of the first trench, a sidewall spacer is constructed, and the third insulating layer fills in the second trench. The fourth insulating layer(26) is deposited and flattened. Through the step, a T-shape of wall STI(Silicon Trench Isolation)(26) and an isolation region(26a) are produced. The active surface is defined by removing the second and the first insulating layers. Inserting p-conductive ions and n-conductive ions, a p-wall region(27) and an n-wall region(28) are formed, respectively. An impurity diffusion region(29) is made with injecting n-conductive impurity ions into the p-wall region(27). As the same way, the other impurity diffusion region(30) is built with inserting p-conductive impurity ions into the n-wall region(28).

Description

듀얼 에스티아이(ＳＴＩ) 웰 형성방법{METHOD FOR FORMING DUAL STI(SILICON TRENCHED ISOLATION) WELL}Dual STI well formation method {METHOD FOR FORMING DUAL STI (SILICON TRENCHED ISOLATION) WELL}

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 SRAM셀에서 면적을 가장 많이 차지하는 웰 스페이스(well space)를 듀얼 STI(Silicon Trench Isolation)공정을 이용하여 획기적으로 감소시킬 수 있는 듀얼 STI 웰 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a dual STI well, which can dramatically reduce a well space that occupies the largest area in an SRAM cell using a dual silicon trench isolation (STI) process. It is about.

일반적으로 풀 씨모스(Full CMOS) 구조의 SRAM셀에서 면적을 가장 많이 차지하는 부분은 웰(Well)이다.In general, the most occupied area of an SRAM cell of a full CMOS structure is a well.

따라서, 웰의 면적을 얼마만큼 효율적으로 감소시키느냐에 따라 셀 사이즈의 최소화 및 고집적화를 만족시킬 수가 있다.Therefore, it is possible to satisfy the minimization and high integration of the cell size depending on how efficiently the area of the well is reduced.

이하, 종래 기술에 따른 듀얼 STI 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a dual STI forming method according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 1g는 종래 기술에 따른 듀얼 STI 형성방법을 설명하기 위한 공정단면도이다.1A to 1G are cross-sectional views illustrating a method of forming a dual STI according to the related art.

도 1a에 도시한 바와 같이, 반도체 기판(11)의 표면상에 제 1 절연층(12)을 성장시키고, 제 1 절연층(12)상에 제 2 절연층(13)으로써, 실리콘 질화막을 형성한다.As shown in FIG. 1A, a silicon nitride film is formed by growing the first insulating layer 12 on the surface of the semiconductor substrate 11 and by using the second insulating layer 13 on the first insulating layer 12. do.

도 1b에 도시한 바와 같이, 액티브 영역을 정의하기 위해 액티브 마스크를 이용하여 상기 제 2 절연층(13)을 선택적으로 제거하는 것에 의해 제 2 절연층 패턴(13a)들을 형성한다.As shown in FIG. 1B, the second insulating layer patterns 13a are formed by selectively removing the second insulating layer 13 using an active mask to define an active region.

도 1c에 도시한 바와 같이, 제 2 절연층 패턴(13a)들을 마스크로 이용한 식각 공정으로 제 1 절연층(12) 및 반도체 기판(11)을 식각하여 제 1 트렌치(14)와 상기 제 1 트렌치(14)에 비해 상대적으로 작은 폭을 갖는 제 2 트렌치(14a)들을 형성한다.As illustrated in FIG. 1C, the first insulating layer 12 and the semiconductor substrate 11 are etched by an etching process using the second insulating layer patterns 13a as a mask to form the first trench 14 and the first trench. The second trenches 14a having a smaller width than 14 are formed.

도 1d에 도시한 바와 같이, 제 1, 제 2 트렌치(14,14a)를 포함한 전면에 상기 트렌치를 매립시킬 수 있도록 충분한 두께의 제 3 절연층(15)을 형성한다.As shown in FIG. 1D, a third insulating layer 15 having a sufficient thickness is formed on the entire surface including the first and second trenches 14 and 14a so as to fill the trench.

도 1e에 도시한 바와 같이, 화학기계적 단면연마(CMP:Chemical Mechanical Polishing)공정을 이용하여 평탄화시킨다.As shown in FIG. 1E, the planarization is performed by using a chemical mechanical polishing (CMP) process.

이때, 상기 제 2 절연층 패턴도 소정두께로 평탄화된다.At this time, the second insulating layer pattern is also planarized to a predetermined thickness.

도 1f에 도시한 바와 같이, 제 2 절연층 패턴 및 제 1 절연층(12)을 제거하여 상기 트렌치(14)내에 매립된 제 3 절연층(15)으로 이루어진 웰 STI(15a)와 소자 격리영역(15b)을 형성하여 액티브 영역을 정의한다.As shown in FIG. 1F, the well STI 15a and the device isolation region including the third insulation layer 15 embedded in the trench 14 by removing the second insulation layer pattern and the first insulation layer 12. An active region is defined by forming 15b.

도 1g에 도시한 바와 같이, P도전형의 이온주입과 N도전형의 이온주입을 통해 P웰 영역(16)과 N웰 영역(17)을 형성한다.As shown in FIG. 1G, the P well region 16 and the N well region 17 are formed through ion implantation of P conductivity type and ion implantation of N conductivity type.

그리고, P웰 영역(16)에 상응하는 액티브 영역의 표면내에 N도전형의 불순물 영역(18)들을 형성하고, N웰 영역(17)에 상응하는 액티브 영역의 표면내에 P도전형의 불순물 영역(19)들을 형성하면 종래 기술에 따른 듀얼 STI 웰 형성공정이 완료된다.Then, the N conductive impurity regions 18 are formed in the surface of the active region corresponding to the P well region 16, and the P conductive impurity regions (in the surface of the active region corresponding to the N well region 17) are formed. Forming 19) completes the dual STI well forming process according to the prior art.

그러나 상기와 같은 종래의 듀얼 STI 웰 형성방법은 다음과 같은 문제점이 있었다.However, the conventional dual STI well formation method as described above has the following problems.

P웰 영역에 형성된 N도전형의 불순물 영역과 N웰 영역간의 브랙다운 전압 및 N웰 영역에 형성된 P도전형의 불순물 영역과 P웰 영역간의 브랙다운 전압 때문에 N도전형의 불순물 영역에서 P도전형의 불순물 영역에 이르는 간격을 충분히 확보하여야 하기 때문에 결과적으로 웰 스페이스가 커지게 된다.P conductivity type in the N conductive impurity region because of the breakdown voltage between the N conductive region and the N well region formed in the P well region and the breakdown voltage between the P conductive region and the P conductive region formed in the N well region Since the interval to reach the impurity region must be sufficiently secured, the well space becomes large as a result.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로,웰 스페이스를 최소화하여 셀 사이즈를 감소시킬 수 있는 듀얼 STI 웰 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a dual STI well forming method that can reduce the cell size by minimizing the well space.

도 1a 내지 1g는 종래 기술에 따른 듀얼 STI웰 형성방법을 설명하기 위한 공정단면도1A to 1G are cross-sectional views illustrating a method of forming a dual STI well according to the related art.

도 2a 내지 2h는 본 발명 듀얼 STI 웰 형성방법을 설명하기 위한 공정단면도2A to 2H are cross-sectional views illustrating a method of forming a dual STI well according to the present invention.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

21 : 반도체 기판 24,24a : 제 1, 제 2 트렌치21 semiconductor substrate 24, 24a: first and second trenches

26 : 웰 STI 26a : 소자격리막26 well STI 26a element isolation film

27 : P웰 영역 28 : N웰 영역27: P well area 28: N well area

29 : N형 불순물 영역 30 : P형 불순물 영역29: N-type impurity region 30: P-type impurity region

상기의 목적을 달성하기 위한 본 발명의 듀얼 STI 웰 형성방법은 반도체 기판상에 트렌치 형성을 위한 마스크층을 형성하는 공정과, 상기 마스크층을 이용한 식각 공정으로 상기 기판을 식각하여 제 1 트렌치를 형성하고, 상기 제 1 트렌치에 비해 작은 폭을 가지며 그 양측에 일정간격을 두고 제 2 트렌치를 형성하는 공정과, 상기 제 1, 제 2 트렌치를 포함한 전면에 절연층을 형성한 후, 상기 제 1 트렌치의 내측면에 절연측벽을 형성하는 공정과, 상기 절연측벽을 마스크로 기판을 소정깊이로 식각하는 공정과, 소정깊이로 식각된 기판을 포함한 전면에 절연층을 형성한 후, 평탄화하여 상기 제 1 트렌치영역에 웰 STI를 형성하고, 상기 제 2 트렌치 영역에 소자격리막을 형성하는 공정과, 상기 마스크층을 제거한 후, 상기 웰 STI를 중심으로 그 양측의 기판내에 P웰 영역과 N웰 영역을 형성하는 공정과, 상기 P웰 영역내에 N도전형의 불순물 영역을 형성하고, 상기 N웰 영역내에 P도전형의 불순물 영역을 형성하는 공정을 포함하여 이루어진다.The dual STI well forming method of the present invention for achieving the above object is to form a first trench by etching the substrate by a process for forming a mask layer for forming a trench on a semiconductor substrate, and an etching process using the mask layer And forming a second trench having a width smaller than that of the first trench and having a predetermined interval on both sides thereof, and forming an insulating layer on the entire surface including the first and second trenches, and then forming the first trench. Forming an insulating side wall on an inner side of the substrate; etching the substrate to a predetermined depth using the insulating side wall; and forming an insulating layer on the entire surface including the substrate etched to a predetermined depth, and then planarizing the first Forming a well STI in the trench region and forming a device isolation film in the second trench region; removing the mask layer, and then removing the mask layer in the substrate on both sides of the well STI. A step of forming a P-well region and the N well region, within the P well region forming impurity regions of N conductivity type, and is achieved by in the N well region includes the step of forming the impurity region of the P conductivity type.

이하, 첨부된 도면을 참조하여 본 발명의 듀얼 STI 웰 형성방법을 설명하기로 한다.Hereinafter, a dual STI well forming method of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 2h는 본 발명 듀얼 STI 웰(well) 형성방법을 설명하기 위한 공정단면도이다.2A to 2H are cross-sectional views illustrating a method of forming a dual STI well according to the present invention.

도 2a에 도시한 바와 같이, 반도체 기판(21)상에 제 1 절연층(22)을 형성하고, 제 1 절연층(22)상에 제 2 절연층(23)을 차례로 형성한다.As shown in FIG. 2A, the first insulating layer 22 is formed on the semiconductor substrate 21, and the second insulating layer 23 is sequentially formed on the first insulating layer 22.

이때, 제 1 절연층(22)은 산화막을, 그리고 제 2 절연층(23)은 질화막을 적용하며, 이후에 형성될 웰 STI를 형성하는 절연층과 식각선택비가 큰 물질을 사용한다.In this case, the first insulating layer 22 uses an oxide film and the second insulating layer 23 uses a nitride film, and a material having a high etching selectivity and an insulating layer forming a well STI to be formed later is used.

도 2b에 도시한 바와 같이, 액티브 영역을 정의하기 위한 액티브 마스크(Active Mask)를 이용하여 상기 제 2 절연층(23)을 선택적으로 제거하는 것에 의해 제 2 절연층 패턴(23a)들을 형성한다.As illustrated in FIG. 2B, the second insulating layer patterns 23a are formed by selectively removing the second insulating layer 23 using an active mask for defining an active region.

상기 제 2 절연층 패턴(23a)은 웰 STI 및 소자격리막을 형성하기 위한 마스크층으로 사용된다.The second insulating layer pattern 23a is used as a mask layer for forming a well STI and an isolation layer.

이후, 상기 제 2 절연층 패턴(23a)들을 마스크로 이용한 식각 공정으로 제 1 절연층(22) 및 반도체 기판(21)을 식각하여 큰 폭을 갖는 제 1 트렌치(24)와, 상기 제 1 트렌치(24)에 비해 상대적으로 작은 폭을 갖는 제 2 트렌치(24a)를 상기 제 1 트렌치(24)의 좌,우측에 일정 거리를 두고 형성한다.Thereafter, the first insulating layer 22 and the semiconductor substrate 21 are etched by the etching process using the second insulating layer patterns 23a as a mask, and the first trench 24 having the large width and the first trenches are etched. A second trench 24a having a smaller width than that of 24 is formed at a predetermined distance on the left and right sides of the first trench 24.

도 2c에 도시한 바와 같이, 상기 제 1, 제 2 트렌치(24,24a)를 포함한 전면에 제 3 절연층(25)을 형성한다.As shown in FIG. 2C, a third insulating layer 25 is formed on the entire surface including the first and second trenches 24 and 24a.

이후, 에치백 공정을 통해 도 2d에 도시한 바와 같이, 폭이 큰 제 1 트렌치(24)의 내측면에는 사이드월 스페이서(25a)를 형성하고, 폭이 작은 제 2 트렌치(24a)내에는 움푹파인 형상으로 제 3 절연층(25)을 매립한다.Thereafter, as illustrated in FIG. 2D, the sidewall spacers 25a are formed on the inner side of the large first trench 24 through the etch back process, and the recesses are formed in the small second trench 24a. The third insulating layer 25 is embedded in the fine shape.

이후, 도 2e에 도시한 바와 같이, 폭이 큰 제 1 트렌치(24)의 내측면에 형성된 사이드월 스페이서(25a)를 마스크로 상기 반도체 기판(21)을 식각한다.Thereafter, as illustrated in FIG. 2E, the semiconductor substrate 21 is etched using the sidewall spacer 25a formed on the inner surface of the first trench 24 having a large width.

그리고, 도 2f에 도시한 바와 같이, 트렌치를 매립시킬 수 있도록 제 4 절연층(26)을 충분한 두께로 증착한 후, 화학기계적 단면연마법(CMP:Chemical Mechanical Polishing)을 이용하여 평탄화한다.As shown in FIG. 2F, the fourth insulating layer 26 is deposited to a sufficient thickness so as to fill the trench, and then planarized by chemical mechanical polishing (CMP).

따라서, T자 형상의 웰 STI(26)와 그 양측의 소자격리영역(26a)이 형성된다.Thus, a T-shaped well STI 26 and element isolation regions 26a on both sides thereof are formed.

이후, 도 2g에 도시한 바와 같이, 상기 제 2 절연층(23) 및 제 1 절연층(22)을 제거하여 액티브 영역을 정의한다.Thereafter, as shown in FIG. 2G, the second insulating layer 23 and the first insulating layer 22 are removed to define an active region.

도 2h에 도시한 바와 같이, P도전형 이온주입을 통해 P웰 영역(27)을 형성하고, 다시 N도전형의 이온주입을 통해 N웰 영역(28)을 형성한다.As shown in FIG. 2H, the P well region 27 is formed through the P conductive ion implantation, and the N well region 28 is formed through the N conductive ion implantation.

이때, 도면에서와 같이, P웰 영역(27)과 N웰 영역(28)의 격리는 T자 형상의 웰 STI(26)에 의해 격리된다.At this time, as shown in the figure, the isolation of the P well region 27 and the N well region 28 is separated by the T-shaped well STI 26.

이후, P웰 영역(27)내에 N도전형의 불순물 이온주입을 통해 불순물 확산영역(29)들을 형성하고, N웰 영역(28)내에 P도전형의 불순물 이온주입을 통해 불순물 확산영역(30)들을 형성하면 본 발명에 따른 듀얼 STI 웰 형성공정이 완료된다.Subsequently, impurity diffusion regions 29 are formed in the P well region 27 by implanting N-conductive impurity ions, and impurity diffusion region 30 is formed in the N well region 28 by implanting P-conductive impurity ions. After the formation, the dual STI well forming process according to the present invention is completed.

이상 상술한 바와 같이 본 발명의 듀얼 STI 웰 형성방법은 P웰 영역과 P웰 영역내 N불순물 영역, 그리고 N웰 영역과 N웰 영역내 P불순물 영역간의 BV(Break Voltage)를 억제하여 웰 스페이스를 최소화할 수 있는 효과가 있다.As described above, the dual STI well forming method of the present invention suppresses the breakdown voltage (BV) between the P well region and the N impurity region in the P well region, and the N well region and the P impurity region in the N well region, thereby reducing the well space. There is an effect that can be minimized.

Claims (3)

반도체 기판상에 트렌치 형성을 위한 마스크층을 형성하는 공정과,Forming a mask layer for forming trenches on the semiconductor substrate; 상기 마스크층을 이용한 식각 공정으로 상기 기판을 식각하여 제 1 트렌치를 형성하고, 상기 제 1 트렌치에 비해 작은 폭을 가지며 그 양측에 일정간격을 두고 제 2 트렌치를 형성하는 공정과,Etching the substrate to form a first trench by an etching process using the mask layer, forming a second trench having a smaller width than the first trench and having a predetermined interval on both sides thereof; 상기 제 1, 제 2 트렌치를 포함한 전면에 절연층을 형성한 후, 상기 제 1 트렌치의 내측면에 절연측벽을 형성하는 공정과,Forming an insulating side wall on an inner surface of the first trench after forming an insulating layer on the entire surface including the first and second trenches; 상기 절연측벽을 마스크로 기판을 소정깊이로 식각하는 공정과,Etching the substrate to a predetermined depth using the insulating side wall as a mask; 소정깊이로 식각된 기판을 포함한 전면에 절연층을 형성한 후, 평탄화하여 상기 제 1 트렌치영역에 웰 STI를 형성하고, 상기 제 2 트렌치 영역에 소자격리막을 형성하는 공정과,Forming an insulating layer on the entire surface including the substrate etched to a predetermined depth, and then planarizing to form a well STI in the first trench region, and forming an isolation layer in the second trench region; 상기 마스크층을 제거한 후, 상기 웰 STI를 중심으로 그 양측의 기판내에 P웰 영역과 N웰 영역을 형성하는 공정과,Removing the mask layer and forming a P well region and an N well region in the substrate on both sides of the well STI; 상기 P웰 영역내에 N도전형의 불순물 영역을 형성하고, 상기 N웰 영역내에 P도전형의 불순물 영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 듀얼 STI 웰 형성방법.And forming an N conductive impurity region in the P well region, and forming an P conductive impurity region in the N well region. 제 1 항에 있어서, 상기 웰 STI는 T자 형상으로 형성하는 것을 특징으로 하는 듀얼 STI 웰 형성방법.The method of claim 1, wherein the well STI is formed in a T-shape. 제 1 항에 있어서, 상기 마스크층은 절연물질로 형성하며, 상기 절연물질은 상기 절연층과 식각선택비가 큰 물질을 사용하는 것을 특징으로 하는 듀얼 STI 웰 형성방법.The method of claim 1, wherein the mask layer is formed of an insulating material, and the insulating material is formed of a material having a high etching selectivity with the insulating layer.
KR1019990054835A 1999-12-03 1999-12-03 Method for forming dual sti(silicon trenched isolation) well KR20010054164A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428785B1 (en) * 2001-08-30 2004-04-30 삼성전자주식회사 Semiconductor device having a trench isolation structure and method of fabricating the same
KR100515057B1 (en) * 2003-01-10 2005-09-14 삼성전자주식회사 Methods for trench device isolation layers of semiconductor devices
KR100702775B1 (en) * 2005-05-03 2007-04-03 주식회사 하이닉스반도체 Method for forming isolation in semiconductor device
CN103515230A (en) * 2012-06-19 2014-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100428785B1 (en) * 2001-08-30 2004-04-30 삼성전자주식회사 Semiconductor device having a trench isolation structure and method of fabricating the same
KR100515057B1 (en) * 2003-01-10 2005-09-14 삼성전자주식회사 Methods for trench device isolation layers of semiconductor devices
US6979628B2 (en) 2003-01-10 2005-12-27 Samsung Electronics Co., Ltd. Methods of forming semiconductor devices having field oxides in trenches and devices formed thereby
KR100702775B1 (en) * 2005-05-03 2007-04-03 주식회사 하이닉스반도체 Method for forming isolation in semiconductor device
US7662697B2 (en) 2005-05-03 2010-02-16 Hynix Semiconductor Inc. Method of forming isolation structure of semiconductor device
CN103515230A (en) * 2012-06-19 2014-01-15 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and formation method thereof

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