KR100671691B1 - Method for manufacturing a bipolar transistor and mehtod for manufacturing a semiconductor device using the same - Google Patents

Abstract

The present invention provides a method for manufacturing a bipolar transistor and a method for manufacturing a semiconductor device using the same, which can simplify the manufacturing process and reduce the chip size during the emitter manufacturing process of the bipolar transistor. Providing a substrate defining a first region in which a bipolar transistor is to be formed, a second region in which an NMOS transistor is formed, and a third region in which a PMOS transistor is formed, forming a collector in the first region, and Forming a well in a third region, forming a base in the collector of the first region, depositing an insulating film and a first conductive layer over the entire structure on which the base is formed; Etching a conductive layer and the insulating film to expose a portion of the base, and a portion of the exposed base Depositing a second conductive layer doped with an impurity so as to be buried, and performing a heat treatment process to diffuse the doped impurities in the second conductive layer into the base to form an emitter in the base of the exposed portion. And forming an emitter electrode and a first gate electrode in the first region, and forming second and third gate electrodes in the second and third regions, respectively, and performing an ion implantation process. Forming first and second source / drain regions on the substrate exposed to the first gate electrode and on the substrate exposed to the second and third gate electrodes, respectively, and the base electrode; And forming a contact plug connected to the collector electrode, the emitter electrode, and the first and second source / drain regions. Provide a method.

Bipolar transistor, doped polysilicon film, heat treatment, emitter.

Description

Method of manufacturing bipolar transistor and method of manufacturing semiconductor device using same {METHOD FOR MANUFACTURING A BIPOLAR TRANSISTOR AND MEHTOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME}

1 to 10 are cross-sectional views illustrating a method of manufacturing a bipolar transistor and a method of manufacturing a semiconductor device using the same according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

BI: Bipolar Region NM: NMOS Region

PM: PMOS region 10: substrate

11 element isolation film 12 collector

15 base 16 gate insulating film

17: first conductive layer 20: second conductive layer

21 emitter electrode 22a bipolar gate electrode

22b: NMOS gate electrode 22c: PMOS gate electrode

23 spacer 26a base electrode

26b, 29 Source / drain region 30 Interlayer insulating film

31: contact plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor manufacturing method and a semiconductor device manufacturing method using the same. Particularly, BiCMOS fabricating a bipolar device operating at high speed and a Complementary Metal Oxide Semiconductor (CMOS) device capable of high integration on a single chip. A method for manufacturing a device.

In general, an integrated circuit made of a semiconductor device is required to manufacture a computer or a communication device used for information processing. In particular, when a large amount of information needs to be processed, a high speed and high integration can be processed quickly. It is already known that an integrated circuit is required. Semiconductor devices commonly used in such integrated circuits include devices having a bipolar structure and devices having a metal oxide semiconductor (MOS) structure.

However, the bipolar device has a high operation speed while having a large area, making it difficult to manufacture highly integrated, while the MOS device has a small area, which can be manufactured highly integrated, while having a large capacitance, which makes it difficult to operate at high speed. .

Therefore, in order to solve such a problem, a BiMOS (Bipolar MOS) device having a bipolar device operating at high speed and a highly integrated MOS device fabricated on a single chip are fabricated. Recently, in order to reduce power consumption of BiMOS devices, many BiCMOS devices using MOS devices as complementary MOS devices have been used.

BiCMOS devices can be applied to integrated circuits that require high speed, high integration, and low power, especially bipolar devices for signal processing devices that require high speed, such as microprocessors, high speed memory devices, and communication devices, and CMOS devices for high density memory devices. By using the same chip at the same time, its utilization is increasing.

A method of manufacturing a BiCMOS device according to the prior art is as follows.

By performing a mask process and an ion implantation process to form a bipolar device, that is, a collector, a base, and an emitter of a bipolar transistor, the gate electrode of the CMOS transistor is formed, and source / drain regions are formed on the substrate exposed to both sides of the gate electrode. Complete the bipolar transistor and the CMOS transistor.

However, since the emitter of the bipolar transistor is formed by forming a collector and a base and then performing a separate mask process and an ion implantation process using a photomask, the manufacturing process is complicated. In addition, due to the high integration of the device is limited by the size of the photomask used in the mask process, there is a problem that the size of the emitter is increased to increase the chip size.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a bipolar transistor that can simplify the manufacturing process and reduce the chip size in the emitter manufacturing process of the bipolar transistor. have.

In addition, another object of the present invention is to provide a method for manufacturing a semiconductor device that can simplify the manufacturing process of the emitter of the bipolar transistor and reduce the chip size in the manufacturing process of the BiCMOS device.

According to an aspect of the present invention, a substrate in which a first region in which a bipolar transistor is to be formed, a second region in which an NMOS transistor is formed, and a third region in which a PMOS transistor is formed are defined through an isolation layer. Forming a collector in the first region, forming a well in the second and third regions, forming a base in the collector of the first region, and forming the base. Depositing an insulating film and a first conductive layer over the entire structure, exposing the portion of the base by etching the first conductive layer and the insulating film, and doping the doped so that a portion of the exposed base is buried Depositing a second conductive layer and performing a heat treatment process to diffuse the doped impurities in the second conductive layer into the base to expose the exposed portion. Forming an emitter in the base, and performing an etching process to form an emitter electrode and a first gate electrode in the first region, and second and third gate electrodes in the second and third regions, respectively. And a base electrode and a collector electrode on the substrate exposed to the first gate electrode by performing an ion implantation process, and first and second source / drain regions on the substrate exposed to the second and third gate electrodes, respectively. Forming a contact plug connected to the base electrode, the collector electrode, the emitter electrode, and the first and second source / drain regions.

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In the present invention, the first conductive layer is formed of a silicon film doped with the same impurities as the second conductive layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

Hereinafter, a method of manufacturing a bipolar transistor and a method of manufacturing a semiconductor device using the same will be described with reference to FIGS. 1 to 10. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 10 are the same elements performing the same function. Here, for the convenience of description, the case where the bipolar transistor according to the present embodiment is of the NPN type will be described.

First, as shown in FIG. 1, a region in which a bipolar transistor is to be formed (BI; hereinafter referred to as a bipolar region), a region in which an NMOS transistor is to be formed (NM; hereinafter referred to as an NMOS region), and a region in which a PMOS transistor is to be formed An isolation layer 11 for separating the bipolar region BI, the NMOS region NM, and the PMOS region PM is formed on the substrate 10 on which PM (hereinafter referred to as a PMOS region) is defined. In this case, the device isolation layer 11 is formed by performing a LOCOS (LOCal Oxidation of Silicon) process. In addition, it may be formed by performing a shallow trench isolation (STI) process that is advantageous for high integration.

Subsequently, as shown in FIG. 2, a mask process and an ion implantation process are performed on the substrate 10 on which the device isolation layer 11 is formed, and the N well (N-Well) is formed in the bipolar region BI and the PMOS region PM. P wells are formed in the NMOS region NM. Here, the N well formed in the substrate 10 of the bipolar region BI functions as the collector 12.

Subsequently, as shown in FIG. 3, a mask process is performed to form a first photoresist pattern 13 having a structure in which the bipolar region BI is opened on the substrate 10.

Subsequently, an ion implantation process 14 using the first photoresist pattern 13 as a mask is performed to form the base 15 of the bipolar transistor in the collector 12 of the bipolar region BI. At this time, the ion implantation step 14 is carried out using boron as a dopant to form a P-type base 15.

Subsequently, as shown in FIG. 4, a strip process is performed to remove the first photoresist pattern 13.

Subsequently, the gate insulating layer 16 and the first conductive layer 17 are sequentially deposited on the entire structure on which the base 15 is formed. In this case, the first conductive layer 17 is formed of a doped or undoped polysilicon film. For example, in the case of the undoped polysilicon layer, Si ₂ H ₄ is used to form a low pressure chemical vapor deposition (LPCVD) method. On the other hand, the doped polysilicon film is formed by LPCVD using Si ₂ H ₄ and PH ₃ gas.

Subsequently, as shown in FIG. 5, a mask process is performed to open a region (see 'A' region; referred to as an emitter region) on the first conductive layer 17 where an emitter of a bipolar transistor is to be formed. The second photoresist pattern 18 having the structure is formed.

Subsequently, an etching process 19 using the second photoresist pattern 18 as a mask is performed to sequentially etch the first conductive layer 17 and the gate oxide film 16. Thus, the emitter region (see 'A' region) of the bipolar transistor is defined so that a portion of the base 15 is exposed.

Subsequently, as shown in FIG. 6, the strip process is performed to remove the second photoresist pattern 18.

Subsequently, the second conductive layer 20 is deposited on the entire structure such that the emitter region (see 'A' region) of the bipolar transistor is buried, and then a heat treatment process is performed. As a result, ions of the second conductive layer 20 embedded in the emitter region (see 'A' region) are diffused into the base 15 by the heat treatment process performed after the deposition of the second conductive layer 20. 21 is formed. At this time, the second conductive layer 20 deposits a silicon film doped with Si ₂ H ₄ and PH ₃ gas.

Here, the reason for using the silicon film doped with Si ₂ H ₄ and PH ₃ gas for the second conductive layer 20 is that the phosphorus (P) ions constituting the second conductive layer 20 are formed on the substrate during the heat treatment process as described above. This is to allow the N-type emitter 21 to be formed in the base 15 while being diffused to the base 10.

Subsequently, as illustrated in FIG. 7, a predetermined third photoresist pattern (not shown) is formed on the entire structure in which the collector 12, the base 15, and the emitter 21 of the bipolar transistor are completed by performing a mask process. ).

Subsequently, an etch process using the third photoresist pattern as a mask is performed to form the emitter electrode 20a on the emitter 21, and the plurality of bipolar gate electrodes (eg, on the substrate 10 of the bipolar region BI) are formed. 22a). At the same time, an NMOS gate electrode 22b is formed in the NMOS region NM, and a PMOS gate electrode 22c is formed in the PMOS region PM. In this case, the plurality of bipolar gate electrodes 22a function as one contact separation layer for separating the emitter 21, the base 15, and the collector 12 of the bipolar transistor, respectively.

Subsequently, as shown in FIG. 8, a strip process is performed to remove the third photoresist pattern (not shown).

Subsequently, an insulating film for a spacer (not shown) is deposited along the steps of the entire structure where the emitter electrode 20a, the bipolar gate electrode 22a, the NMOS gate electrode 22b, and the PMOS gate electrode 22c are formed.

Subsequently, a dry etching process is performed to form spacers 23 on both sidewalls of each emitter electrode 20a, bipolar gate electrode 22a, NMOS gate electrode 22b, and PMOS gate electrode 22c.

Subsequently, a mask process is performed to form a fourth photoresist pattern 24 covering the NMOS region NM.

Subsequently, the first impurity ion implantation step 25 using the fourth photoresist pattern 24 as a mask is performed to form a high concentration junction region 26a in the base 15 between the bipolar gate electrodes 22a, thereby forming a PMOS. The source / drain regions 26b are formed in the substrate 10 exposed to both sides of the gate electrode 22c. At this time, the first impurity ion implantation step 25 is performed using phosphorus. Here, the high concentration junction region 26a in the base 15 functions as a base electrode 26a connected to the base terminal. Although not shown here, a junction region is also formed in the collector 12 to function as a collector electrode. Here, the first impurity ion implantation step 25 is performed using phosphorus.

That is, the emitter electrode 20a, the base electrode 26a, and the collector electrode (not shown) are self-aligned during the first impurity ion implantation process 25 due to the bipolar gate electrode 22a formed above.

Next, as shown in FIG. 9, the strip process is performed to remove the fourth photoresist pattern 24.

Subsequently, a mask process is performed to form a fifth photoresist pattern 27 having an open NMOS region NM.

Subsequently, a second impurity ion implantation process 28 using the fifth photoresist pattern 27 as a mask is performed to provide the source / drain regions 29 to the substrate 10 exposed to both sides of the NMOS gate electrode 22b. Form. At this time, the second impurity ion implantation step 28 is performed using boron.

Subsequently, as shown in FIG. 10, the strip process is performed to remove the fifth photoresist pattern 27.

Next, an interlayer insulating film 30 is deposited over the entire structure in which the junction region 26a and the source / drain regions 26b and 29 are formed. In this case, the interlayer insulating film 30 is formed of an oxide film-based material. For example, the interlayer insulating film 30 may include a high density plasma (HDP) oxide film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a plasma enhanced tetra thyle ortho silicate (peteos) film, and a plasma enhanced chemical vapor (PECVD) film. A single layer film or a laminate of these layers is laminated using any one of a deposition film, a USG (Un-doped Silicate Glass) film, a FSG (Fluorinated Silicate Glass) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film Form into a film.

Subsequently, a mask process and an etching process are performed to partially expose the emitter electrode 20a, the junction region 26a, the collector electrode (not shown), and the respective source / drain regions 26b and 29 in the interlayer insulating film 30. A plurality of contact holes (not shown) are formed.

Subsequently, a conductive film filling the contact hole is deposited to deposit the emitter electrode 20a, the junction region 26a, the collector electrode (not shown) of the bipolar transistor, the source / drain region 29 of the NMOS transistor, and the source / drain of the PMOS. Contact plugs 31 connecting the regions 26b are formed, respectively.

Subsequently, although not shown in the drawing, a metal wiring material is deposited on the entire structure on which the contact plug 31 is formed, and then an etching process is performed to form wiring layers on the contact plug 31. Accordingly, the emitter 21, the base 15, and the collector 12 of the bipolar transistor are electrically connected to the wiring layer through the contact plug 31, while the source / drain regions 29 and 26b of the NMOS and PMOS transistors are electrically connected. It is electrically connected with this wiring layer.

That is, according to a preferred embodiment of the present invention, a polysilicon film doped with an impurity containing phosphorus ions is deposited on the substrate 10 on which the collector 12 and the base 15 of the bipolar transistor are formed, followed by heat treatment. Emitter 21 is formed. Thus, not only a separate mask process and an ion implantation process for forming the emitter 21 of the bipolar transistor can be skipped, but also the emitter 21 can be formed at the correct position. This not only simplifies the process of manufacturing the emitter 21 of the bipolar transistor, but also allows the size of the emitter 21 to be controlled to reduce the chip size.

Further, according to a preferred embodiment of the present invention, a plurality of bipolar gate electrodes on the substrate 10 of the bipolar region BI in which the collector 12, the base 15, and the emitter 21 of the bipolar transistor are formed. After the 22a is formed, the emitter electrode 20a is formed between the gate electrodes 22a thus formed, and the collector electrode and the base electrode 26a are formed on the substrate 10 between the gate electrodes 22a. Therefore, the emitter electrode 20a, the base electrode 26a, and the collector electrode are self-aligned through the gate electrode 22a.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a doped polysilicon film is deposited on a substrate on which a collector and a base of a bipolar transistor are formed, followed by heat treatment to form an emitter, thereby forming an emitter of a bipolar transistor. Not only can the mask process and the ion implantation process be skipped, but also the emitter can be formed in the correct position. Accordingly, the emitter manufacturing process of the bipolar transistor can be simplified, the chip size can be reduced, and the distance between the emitter and the base can be reduced to improve the series resistance characteristics of the base.

Further, according to the present invention, after forming a plurality of gate electrodes on a substrate on which a collector, a base and an emitter of a bipolar transistor are formed, an emitter electrode is formed between the gate electrodes thus formed and the collector is formed on the substrate between the gate electrodes. By forming the electrode and the base electrode, the emitter electrode, the base electrode and the collector electrode can be self-aligned through the gate electrode. Accordingly, mis-alignment that may occur when the emitter electrode, the base electrode, and the collector electrode are formed through the mask process and the ion implantation process may be prevented.

Claims (4)

delete delete Providing a substrate on which a first region in which a bipolar transistor is to be formed, a second region in which an NMOS transistor is to be formed, and a third region in which a PMOS transistor is to be formed are formed through an isolation layer; Forming a collector in the first region and forming a well in the second and third regions; Forming a base in the collector of the first region; Depositing an insulating film and a first conductive layer on the entire structure where the base is formed; Etching the first conductive layer and the insulating layer to expose a portion of the base; Depositing a second conductive layer doped with impurities such that a portion of the exposed base is embedded; Performing a heat treatment process to diffuse the doped impurities in the second conductive layer into the base to form an emitter in the exposed portion of the base; Performing an etching process to form an emitter electrode and a first gate electrode in the first region, and second and third gate electrodes in the second and third regions, respectively; Performing an ion implantation process to form first and second source / drain regions on the substrate exposed by the base and collector electrodes and the second and third gate electrodes, respectively, on the substrate exposed to the first gate electrode; step; And Forming a contact plug connected to the base electrode, the collector electrode, the emitter electrode, and the first and second source / drain regions; Method for manufacturing a semiconductor device comprising a. The method of claim 3, wherein And the first conductive layer is formed of a silicon film doped with the same impurities as the second conductive layer.

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