KR20010066327A - A method for fabricating dual gate electrode - Google Patents
A method for fabricating dual gate electrode Download PDFInfo
- Publication number
- KR20010066327A KR20010066327A KR1019990067927A KR19990067927A KR20010066327A KR 20010066327 A KR20010066327 A KR 20010066327A KR 1019990067927 A KR1019990067927 A KR 1019990067927A KR 19990067927 A KR19990067927 A KR 19990067927A KR 20010066327 A KR20010066327 A KR 20010066327A
- Authority
- KR
- South Korea
- Prior art keywords
- gate electrode
- layer
- region
- film
- forming
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000009977 dual effect Effects 0.000 title claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000011229 interlayer Substances 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 씨모스에서 듀얼 게이트전극 제조방법에 관한 것으로, 특히 CMOS의 듀얼 게이트전극을 사용하는 트랜지스터의 제조공정에서 게이트전극으로 사용되는 다결정실리콘층 패턴과 소오스/드레인영역에 이온주입공정을 동시에 실시하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a dual gate electrode in CMOS, and in particular, an ion implantation process is simultaneously performed on a polysilicon layer pattern and a source / drain region used as a gate electrode in a transistor manufacturing process using a dual gate electrode of CMOS. It is about how to.
종래의 듀얼 게이트전극을 제조하는 방법은 언도프(undoped)된 폴리실리콘층 상부에 마스크(Mask)를 사용하여 듀얼 임플란트(implant)(n+: AS· P, p+: B·BF2)하거나, 인-시튜 도핑(in-situ doping)방법에 의하여 n+게이트와 p+게이트를 각각 증착하고, 패터닝(patterning)하는 방법이 주로 사용되었다.The conventional method of manufacturing a dual gate electrode is to use a dual implant (n + : AS · P, p + : B · BF 2 ) using a mask on the undoped polysilicon layer. By the in-situ doping method, a method of depositing and patterning n + gate and p + gate, respectively, has been mainly used.
그러나, 전자의 방법은 공정이 간편한 편이나 하이 도핑(high doping)이 어렵고, 도판트 프로파일(dopant profile) 특성상 게이트 디플리션이 일어나기 쉽다.However, the former method is easy to process, but high doping is difficult, and gate depletion tends to occur due to the dopant profile characteristics.
또한, 후자의 방법은 n+/p+폴리실리콘 게이트를 증착해야 하므로 각각의 공정을 셋업(set-up) 해야 되는 문제점이 있으며, 또한 각각의 게이트를 증착하고 디파인하고 패터닝해야 되는 복잡성이 있다.In addition, the latter method requires the deposition of n + / p + polysilicon gates, so there is a problem in that each process needs to be set-up, and there is also a complexity of depositing, defining and patterning each gate.
이하, 종래기술에 따른 듀얼 게이트전극 제조방법을 설명하기로 한다.Hereinafter, a dual gate electrode manufacturing method according to the prior art will be described.
먼저, 반도체기판에서 소자분리영역으로 예정되는 부분에 소자분리절연막을 형성한다.First, a device isolation insulating film is formed on a portion of the semiconductor substrate, which is intended as a device isolation region.
다음, NMOS영역으로 예정되는 부분에 p웰을 형성하고, PMOS영역으로 예정되는 부분에 n웰을 형성한다.Next, p wells are formed in a portion intended for the NMOS region, and n wells are formed in a portion intended for the PMOS region.
그 다음, 전체표면 상부에 게이트절연막을 형성하고, 상기 게이트절연막 상부에 다결정실리콘층을 형성한 후, 상기 다결정실리콘층 상부에 NMOS를 노출시키는 제1감광막 패턴을 형성하고, n 형 불순물을 임플란트하여 n+형 다결정실리콘층를 형성한다.Next, a gate insulating film is formed over the entire surface, a polysilicon layer is formed over the gate insulating film, a first photoresist pattern is formed over the polysilicon layer to expose an NMOS, and an n-type impurity is implanted. An n + type polycrystalline silicon layer is formed.
다음, 상기 제1감광막 패턴을 제거하고, 상기 다결정실리콘층 상부에 PMOS를 노출시키는 제2감광막 패턴을 형성한 후, p 형 불순물을 임플란트하여 p+형 다결정실리콘층을 형성한다.Next, the first photoresist layer pattern is removed, and a second photoresist layer pattern exposing the PMOS is formed on the polysilicon layer, and then p-type impurities are implanted to form a p + polysilicon layer.
그 다음, 상기 제2감광막 패턴을 제거하고, 전체표면 상부에 확산방지막, 텅스텐층 및 마스크절연막의 적층구조를 형성한 다음, 게이트전극으로 예정되는 부분을 보호하는 게이트전극 마스크를 식각마스크로 상기 적층구조 및 불순물이 이온주입된 다결정실리콘층을 식각하여 마스크절연막 패턴, 텅스텐층 패턴, 확산방지막 패턴 및 게이트전극을 형성한다.Next, the second photoresist layer pattern is removed, a stacked structure of a diffusion barrier layer, a tungsten layer, and a mask insulating layer is formed on the entire surface, and then the gate electrode mask that protects a portion intended as a gate electrode is laminated using the etching mask. The polysilicon layer implanted with the structure and impurities is etched to form a mask insulating film pattern, a tungsten layer pattern, a diffusion barrier film pattern and a gate electrode.
다음, 저농도의 불순물을 이온주입하여 LDD영역을 형성하고, 상기 구조의 측벽에 절연막스페이서를 형성한 다음, 고농도의 불순물을 이온주입하여 소오스/드레인영역을 형성한다.Next, an LDD region is formed by ion implantation of a low concentration of impurities, an insulating film spacer is formed on the sidewall of the structure, and a source / drain region is formed by ion implantation of a high concentration of impurities.
상기와 같이 종래기술에 따른 듀얼 게이트전극 제조방법은, 게이트절연막/다결정실리콘층/마스크절연막의 적층구조를 갖는 듀얼 게이트 트랜지스터에서는 다결정실리콘 또는 비정질실리콘층을 증착한 후 NMOS와 PMOS영역을 각각 독립적인 마스크공정으로 게이트전극의 다결정실리콘층을 도핑하고 패터닝한 다음 소오스/드레인영역을 형성하기 위한 이온주입공정을 실시하므로 4회의 마스크공정을 실시하였다.또한, 소자가 점점 고집적화되어 감에 따라 콘택의 크기가 줄어들어 저항이 증가하고 얕은 접합의 도입으로 접합누설전류의 증가 등 신뢰성이 저하되는 문제점이 있다.As described above, in the dual gate electrode manufacturing method according to the related art, in a dual gate transistor having a laminated structure of a gate insulating film / polycrystalline silicon layer / mask insulating film, after depositing a polysilicon or an amorphous silicon layer, the NMOS and PMOS regions are independent of each other. The mask process was performed by doping and patterning the polysilicon layer of the gate electrode, followed by an ion implantation process to form a source / drain region. Thus, the mask process was performed four times. Is reduced, the resistance is increased, and the introduction of a shallow junction causes a problem in that reliability is lowered, such as an increase in junction leakage current.
본 발명은 상기한 종래기술의 문제점들을 해결하기 위하여, 다결정실리콘층 또는 비정질실리콘층으로 게이트전극을 형성하고, NMOS영역과 PMOS영역을 각각 독립적으로 오픈시킨 후 불순물을 이온주입하여 소오스/드레인영역을 형성하는 동시에 상기 게이트전극에 불순물을 이온주입하여 마스크공정을 감소시킴으로써 공정을 단순화시키는 듀얼 게이트전극 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the gate electrode is formed of a polysilicon layer or an amorphous silicon layer, the NMOS region and the PMOS region are independently opened, and impurities are ion implanted to form a source / drain region. It is an object of the present invention to provide a method of manufacturing a dual gate electrode which simplifies the process by reducing the mask process by implanting impurities into the gate electrode at the same time.
도 1 내지 도 8 은 본 발명에 따른 듀얼 게이트전극 제조방법을 도시한 단면도.1 to 8 are cross-sectional views showing a method for manufacturing a dual gate electrode according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 반도체기판 11 : p웰10 semiconductor substrate 11: p well
12 : n웰 13 : 소자분리절연막12 n-well 13 element isolation insulating film
14 : 게이트절연막 15a : 다결정실리콘층14 gate insulating film 15a polysilicon layer
15b : 게이트전극 15c : n+게이트전극15b: gate electrode 15c: n + gate electrode
15d : p+게이트전극 16a : n-LDD영역15d: p + gate electrode 16a: n-LDD region
16b : p- LDD영역 17 : 절연막 스페이서16b: p-LDD region 17 insulating film spacer
18a : n+소오스/드레인영역 18b : p+소오스/드레인영역18a: n + source / drain region 18b: p + source / drain region
19 : 살리사이드막 20 : 식각방지막19: salicide film 20: etching prevention film
21 : 층간절연막 22 : 금속배선콘택21: interlayer insulating film 22: metal wiring contact
이상의 목적을 달성하기 위한 본 발명에 따른 듀얼 게이트전극 제조방법은,Dual gate electrode manufacturing method according to the present invention for achieving the above object,
NMOS영역과 PMOS영역이 구비되는 반도체기판 상부에 게이트절연막을 형성하고, 상기 게이트절연막 상에 게이트전극을 형성하는 공정과,Forming a gate insulating film on the semiconductor substrate including the NMOS region and the PMOS region, and forming a gate electrode on the gate insulating film;
상기 NMOS영역에 n-불순물을 이온주입하여 n-LDD영역을 형성한 다음, 상기 PMOS영역에 p-불순물을 이온주입하여 p-LDD영역을 형성하는 공정과,Forming an n-LDD region by ion-implanting an n-impurity into the NMOS region, followed by ion implantation of a p-impurity into the PMOS region to form a p-LDD region;
상기 게이트전극의 측벽에 절연막 스페이서를 형성하는 공정과,Forming an insulating film spacer on sidewalls of the gate electrode;
상기 NMOS영역에 n+불순물을 이온주입하여 n+게이트전극 및 n+소오스/드레인영역을 형성한 다음, 상기 PMOS마스크에 p+불순물을 이온주입하여 p+게이트전극 및 p+소오스/드레인영역을 형성하는 공정과,Implanting n + impurities into the NMOS region to form an n + gate electrode and an n + source / drain region, and ion implanting a p + impurity into the PMOS mask to form a p + gate electrode and a p + source / drain region;
상기 n+, p+게이트전극 및 n+, p+소오스/드레인영역 상부에 살리사이드막을형성하고, 전체표면 상부에 식각방지막을 형성하는 공정과,Forming a salicide film on the n +, p + gate electrodes and the n +, p + source / drain regions, and forming an etch stop layer on the entire surface;
상기 식각방지막 상부에 층간절연막을 형성하고, 금속배선 콘택마스크를 식각마스크로 상기 층간절연막 및 식각방지막을 식각하여 금속배선콘택홀을 형성하는 공정과,Forming an interlayer insulating layer on the etch stop layer, and etching the interlayer insulating layer and the etch stop layer using an metal wiring contact mask as an etch mask to form a metal wiring contact hole;
상기 금속배선콘택홀을 통하여 상기 살리사이드막과 접속되는 금속배선콘택을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a metal wiring contact connected to the salicide layer through the metal wiring contact hole.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 8 은 본 발명에 따른 듀얼 게이트전극 제조방법을 도시한 단면도이다.1 to 8 are cross-sectional views illustrating a method of manufacturing a dual gate electrode according to the present invention.
먼저, 반도체기판(10)에서 소자분리영역으로 예정되는 부분에 소자분리절연막(13)을 형성한다.First, an element isolation insulating film 13 is formed on a portion of the semiconductor substrate 10 that is intended as an element isolation region.
다음, NMOS영역으로 예정되는 부분에 p웰(11)을 형성하고, PMOS영역으로 예정되는 부분에 n웰(12)을 형성한다. (도 1 참조)Next, the p well 11 is formed in the portion intended for the NMOS region, and the n well 12 is formed in the portion intended for the PMOS region. (See Figure 1)
그 다음, 전체표면 상부에 게이트절연막(14)을 성장시킨다. (도 2 참조)Then, the gate insulating film 14 is grown on the entire surface. (See Figure 2)
다음, 상기 게이트절연막(14) 상부에 다결정실리콘층(15a)을 형성한다. (도 3 참조)Next, a polysilicon layer 15a is formed on the gate insulating layer 14. (See Figure 3)
그 다음, 게이트전극으로 예정되는 부분을 보호하는 게이트전극 마스크를 식각마스크로 상기 다결정실리콘층(15a)을 식각하여 게이트전극(15b)을 형성한다.Next, the polysilicon layer 15a is etched by using a gate electrode mask that protects a portion intended as a gate electrode as an etch mask to form a gate electrode 15b.
다음, NMOS영역을 노출시키는 NMOS마스크를 이온주입마스크로 사용하여 저농도의 n-불순물을 이온주입하여 n-LDD영역(16a)을 형성한 후, PMOS영역을 노출시키는 PMOS마스크를 이온주입마스크로 사용하여 저농도의 p-불순물을 이온주입하여 p-LDD영역(16b)을 형성한다. (도 4 참조)Next, an NMOS mask exposing the NMOS region is used as an ion implantation mask to form an n-LDD region 16a by ion implantation of a low concentration of n-impurity, and then a PMOS mask exposing the PMOS region is used as an ion implantation mask. As a result, p-LDD region 16b is formed by ion implantation of low concentration of p-impurity. (See Figure 4)
그 다음, 전체표면 상부에 절연막(도시안됨)을 형성한 후 전면식각공정을 실시하여 상기 게이트전극(15b)의 측벽에 절연막 스페이서(17)를 형성한다.Next, an insulating film (not shown) is formed over the entire surface, and then an entire surface etching process is performed to form an insulating film spacer 17 on the sidewall of the gate electrode 15b.
그 후, NMOS마스크를 이온주입마스크로 사용하여 상기 게이트전극(15b) 및 절연막 스페이서(17)의 양측에 고농도의 n+불순물을 이온주입하여 n+ 게이트전극(15c)와 n+소오스/드레인영역(18a)을 형성한다.Thereafter, using a NMOS mask as an ion implantation mask, ion implantation of high concentrations of n + impurities on both sides of the gate electrode 15b and the insulating film spacer 17 results in the n + gate electrode 15c and the n + source / drain region 18a. To form.
이어서, PMOS마스크를 이온주입마스크로 사용하여 상기 게이트전극(15b) 및 절연막 스페이서(17)의 양측에 고농도의 p+불순물을 이온주입하여 p+ 게이트전극(15d)와 p+소오스/드레인영역(18b)을 형성한다.Subsequently, a high concentration of p + impurities are implanted into both sides of the gate electrode 15b and the insulating film spacer 17 by using a PMOS mask as an ion implantation mask to form the p + gate electrode 15d and the p + source / drain region 18b. Form.
다음, 상기 게이트절연막(14)을 제거하여 반도체기판(10)을 노출시키고, 상기 n+게이트전극(15c), p+게이트전극(15d) 및 노출된 반도체기판(10)의 표면에 선택적으로 살리사이드막(19)을 형성한다. 이때, 상기 살리사이드막(19)은 Ti계열의 금속 또는 Co계열의 금속 또는 Ti를 다량 함유하는 실리사이드막 또는 Co를 다량 함유하는 실리사이드막으로 형성하여 반도체기판(10)에서 소모되는 실리콘의 양을 제한시켜 소오스/드레인영역이 손상되는 것을 최소화시킨다. (도 6 참조)Next, the gate insulating layer 14 is removed to expose the semiconductor substrate 10, and the salicide layer is selectively formed on the surfaces of the n + gate electrode 15c, the p + gate electrode 15d, and the exposed semiconductor substrate 10. (19) is formed. In this case, the salicide layer 19 is formed of a silicide layer containing a large amount of Ti or a metal based on Co or a metal or a Co type or a silicide layer containing a large amount of Co, thereby reducing the amount of silicon consumed in the semiconductor substrate 10. Restriction minimizes damage to the source / drain regions. (See Figure 6)
그 다음, 전체표면 상부에 식각방지막(20)을 형성하되, 상기 식각방지막(20)은 질화막 또는 후속공정으로 형성되는 층간절연막과 식각선택비를 갖는 산화물을 이용하여 형성한다. 상기 식각방지막(20)은 상기 살리사이드막(19) 상부에서 마스크절연막의 역할을 하는 동시에 후속 금속배선 콘택홀을 형성하기 위한 식각공정시식각장벽의 역할을 한다. (도 7 참조)Next, an etch stop layer 20 is formed on the entire surface, and the etch stop layer 20 is formed using an oxide having an etching selectivity and an interlayer insulating layer formed by a nitride film or a subsequent process. The etch stop layer 20 serves as a mask insulating layer on the salicide layer 19 and also serves as an etching barrier during the etching process for forming subsequent metal wiring contact holes. (See Figure 7)
다음, 전체표면 상부에 층간절연막(21)을 형성한다.Next, an interlayer insulating film 21 is formed over the entire surface.
그리고, 상기 반도체기판(10)에서 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 사용하여 상기 층간절연막(21) 및 식각방지막(20)을 식각하여 금속배선 콘택홀(도시안됨)을 형성한다.The interlayer insulating layer 21 and the etch stop layer 20 are etched using a metal wiring contact mask that exposes a predetermined portion of the semiconductor substrate 10 as a metal wiring contact as an etching mask. No).
그 후, 상기 금속배선 콘택홀을 통하여 상기 살리사이드막(19)에 접속되는 금속배선 콘택(22)을 형성한다. (도 8 참조)Thereafter, a metal wiring contact 22 connected to the salicide layer 19 is formed through the metal wiring contact hole. (See Figure 8)
이상에서 설명한 바와 같이 본 발명에 따른 듀얼 게이트 제조방법은, CMOS의 듀얼 게이트전극의 제조공정시 NMOS영역과 PMOS영역의 게이트전극으로 사용되는 실리콘층 패턴과 소오스/드레인영역으로 예정되는 부분에 불순물을 동시에 이온주입하여 게이트전극과 소오스/드레인영역을 형성하여 마스크공정을 줄이고, 금속배선콘택 형성공정에서 사용되는 식각방지막과 게이트전극 상의 마스크절연막을 동시에 형성하여 공정을 단순하게 하고 콘택저항을 감소시킴으로써 트랜지스터의 동작 특성을 향상시켜 공정의 안정성을 확보하고 그에 따른 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the dual gate fabrication method according to the present invention, impurities are deposited in portions defined as silicon layer patterns and source / drain regions used as gate electrodes of the NMOS region and the PMOS region during the manufacturing process of the dual gate electrode of the CMOS. At the same time, the gate electrode and the source / drain regions are formed by ion implantation to reduce the mask process, and the etch stop layer used in the metallization contact forming process and the mask insulating film on the gate electrode are simultaneously formed to simplify the process and reduce the contact resistance. By improving the operating characteristics of the process to ensure the stability of the process there is an advantage to enable high integration of the semiconductor device.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067927A KR20010066327A (en) | 1999-12-31 | 1999-12-31 | A method for fabricating dual gate electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990067927A KR20010066327A (en) | 1999-12-31 | 1999-12-31 | A method for fabricating dual gate electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010066327A true KR20010066327A (en) | 2001-07-11 |
Family
ID=19635015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990067927A KR20010066327A (en) | 1999-12-31 | 1999-12-31 | A method for fabricating dual gate electrode |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010066327A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100411025B1 (en) * | 2001-12-11 | 2003-12-18 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100446860B1 (en) * | 2002-06-12 | 2004-09-04 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100488540B1 (en) * | 2002-08-29 | 2005-05-11 | 삼성전자주식회사 | Devices and Method of manufacturing semiconductor |
| KR100514166B1 (en) * | 2004-01-20 | 2005-09-13 | 삼성전자주식회사 | Method of forming cmos |
| US6962862B2 (en) | 2001-07-25 | 2005-11-08 | Nec Electronics Corporation | Manufacturing method of semiconductor device |
| KR101133530B1 (en) * | 2005-07-29 | 2012-04-05 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293790A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH10261792A (en) * | 1997-03-18 | 1998-09-29 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH10294459A (en) * | 1997-04-22 | 1998-11-04 | Sharp Corp | Manufacture of semiconductor device |
| JPH1154745A (en) * | 1997-07-29 | 1999-02-26 | Sony Corp | Manufacture of semiconductor device |
-
1999
- 1999-12-31 KR KR1019990067927A patent/KR20010066327A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09293790A (en) * | 1996-04-25 | 1997-11-11 | Nec Corp | Semiconductor device and manufacture thereof |
| JPH10261792A (en) * | 1997-03-18 | 1998-09-29 | Hitachi Ltd | Semiconductor device and its manufacture |
| JPH10294459A (en) * | 1997-04-22 | 1998-11-04 | Sharp Corp | Manufacture of semiconductor device |
| JPH1154745A (en) * | 1997-07-29 | 1999-02-26 | Sony Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6962862B2 (en) | 2001-07-25 | 2005-11-08 | Nec Electronics Corporation | Manufacturing method of semiconductor device |
| KR100411025B1 (en) * | 2001-12-11 | 2003-12-18 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100446860B1 (en) * | 2002-06-12 | 2004-09-04 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR100488540B1 (en) * | 2002-08-29 | 2005-05-11 | 삼성전자주식회사 | Devices and Method of manufacturing semiconductor |
| KR100514166B1 (en) * | 2004-01-20 | 2005-09-13 | 삼성전자주식회사 | Method of forming cmos |
| KR101133530B1 (en) * | 2005-07-29 | 2012-04-05 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5489546A (en) | Method of forming CMOS devices using independent thickness spacers in a split-polysilicon DRAM process | |
| KR20030084144A (en) | Semiconductor device using silicon-germanium gate and method for fabricating the same | |
| US5612240A (en) | Method for making electrical connections to self-aligned contacts that extends beyond the photo-lithographic resolution limit | |
| US6274914B1 (en) | CMOS integrated circuits including source/drain plug | |
| US6586296B1 (en) | Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks | |
| KR100387721B1 (en) | Manufacturing method of semiconductor device | |
| US6261912B1 (en) | Method of fabricating a transistor | |
| US20010017391A1 (en) | Method of fabricating semiconductor device | |
| KR20010066327A (en) | A method for fabricating dual gate electrode | |
| US6635522B2 (en) | Method of forming a MOS transistor in a semiconductor device and a MOS transistor fabricated thereby | |
| KR100370128B1 (en) | Method for manufacturing of semiconductor device | |
| US7202180B2 (en) | Methods of forming semiconductor devices using an etch stop layer | |
| KR100273296B1 (en) | Method for fabricating mos transistor | |
| KR100312808B1 (en) | Method of fabricating dual voltage mos transistors | |
| KR100495858B1 (en) | Method of manufacturing a semiconductor device | |
| KR20000044936A (en) | Method for fabricating cmos transistor | |
| KR100415191B1 (en) | Method for fabricating asymmetric cmos transistor | |
| KR20010059984A (en) | A method for fabricating a semiconductor device | |
| US6093595A (en) | Method of forming source and drain regions in complementary MOS transistors | |
| KR100546124B1 (en) | Transistor Formation Method of Semiconductor Device | |
| KR100313783B1 (en) | Method for fabricating metal oxide semiconductor transistor | |
| KR100224586B1 (en) | Manufacturing method of cmos transistor | |
| KR100611786B1 (en) | Method for fabrication of mos transistor | |
| EP0878833B1 (en) | Process for the selective formation of salicide on active areas of MOS devices | |
| KR20020017833A (en) | A method for forming a dual transistor of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |