JP2007053399A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the contact resistance during contact connection of a lower layer and an upper layer. <P>SOLUTION: The semiconductor device has a MOS transistor with a normal breakdown voltage (A) formed on a semiconductor substrate and a MOS transistor with a high breakdown voltage (B). The number of plug contact parts 47 to be made into contact connection with a source/drain layer 42 of the MOS transistor with a normal breakdown voltage (A) is smaller than that of plug contact parts 47 to be made into contact connection with a source/drain layer 30 of the MOS transistor with a high breakdown voltage (B). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for reducing contact resistance when a lower layer and an upper layer are contact-connected.

  Hereinafter, a conventional semiconductor device will be described with reference to the drawings.

  In FIG. 13, reference numeral 1 denotes a semiconductor substrate. A gate electrode 3 is formed on the substrate 1 via a gate oxide film 2, and a source / drain layer 4 is formed adjacent to the gate electrode 3. Then, an interlayer insulating film 5 covering the gate electrode is formed, and source / drain electrodes 7 are formed in contact with the source / drain layer 4 through contact holes 6 formed in the interlayer insulating film 5. .

  Here, when forming the source / drain electrodes, when a metal film such as Al is deposited by sputtering, the step coverage of the metal film in the contact hole is reduced as the contact hole is reduced. For this reason, recently, a conductive wiring film such as a tungsten film is buried in the contact hole by a CVD method, and a metal film such as Al is formed thereon by patterning to form a metal wiring layer.

  When adopting such plug contact technology and configuring various transistors, if the contact hole size is various, the recess amount at the time of etching back after filling also varies. It may be as bad as when the step coverage is not embedded.

  For this reason, when various transistors are formed by a miniaturization process such as 0.35 μm, it is necessary to make each contact hole size the same as the contact hole size of a transistor with the minimum design rule. There was a problem that would rise.

  Therefore, the semiconductor device of the present invention includes a first gate oxide film formed on a semiconductor substrate, a first gate electrode formed on the first gate oxide film, and the first gate electrode. A first transistor comprising a first source / drain layer formed on a surface layer of the semiconductor substrate so as to be adjacent to the first transistor, and a film thickness greater than that of the first gate oxide film formed on the semiconductor substrate. A second gate oxide film, a second gate electrode formed on the second gate oxide film, and a second gate oxide film formed on a surface layer of the semiconductor substrate so as to be adjacent to the second gate electrode. And a second contact transistor having a higher breakdown voltage than that of the first transistor and connected to the first source / drain layer of the first transistor. Number, and is characterized in that less than the number of plug contact portion to be contact connected to a second source-drain layer of the second transistor.

  A first gate oxide film formed on the semiconductor substrate; a first gate electrode formed on the first gate oxide film; and the semiconductor substrate adjacent to the first gate electrode. A first transistor comprising a first source / drain layer formed on the surface layer of the first gate oxide film; and a second gate oxide film formed on the semiconductor substrate and having a thickness greater than that of the first gate oxide film A second gate electrode formed on the second gate oxide film, and a second source / drain layer formed on the surface layer of the semiconductor substrate so as to be adjacent to the second gate electrode. And a second transistor having a higher breakdown voltage than the first transistor, and the number of plug contact portions connected in contact between the lower layer wiring and the upper layer wiring on the first transistor side is the second transistor. Trang Is characterized in that less than the number of plug contact portion to be contact connected between static side of the lower layer wiring and the upper wiring.

  In the second transistor, a semiconductor layer constituting a channel is formed below the gate electrode, and a low concentration layer having the same conductivity type as the source / drain layer is formed so as to be in contact with the semiconductor layer. It is a feature.

  Further, the semiconductor layer is configured in a lower central portion of the second gate electrode.

  Further, the plug contact portion is formed in a contact hole formed with a minimum dimension in a design rule.

  Further, the plug contact portion is embedded with a tungsten film or a polysilicon film.

  Further, the plug contact portions formed in the first transistor are in one row, and the plug contact portions formed in the second transistor are in a plurality of rows.

  The plug contact portions of the first transistor arranged near the power supply pad are in a plurality of rows.

  According to the present invention, the contact resistance can be reduced by increasing the number of contact portions, and the on-resistance of the transistor can be reduced.

  Further, in the present invention having various transistors and forming contact holes with the minimum dimensions in the design rule, by setting and arranging the optimum number of contacts for each transistor, contact resistance can be reduced, The on-resistance of the transistor can be reduced.

  Furthermore, the resistance can be further reduced by applying not only to the contact portion for contact connection to the source / drain layer but also to the contact portion for connecting the lower layer wiring and the upper layer wiring.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor device and a method for manufacturing the same according to the invention will be described with reference to the drawings with respect to an embodiment in which the invention is applied to a semiconductor device in which various MOS transistors constituting a liquid crystal drive driver are mixedly mounted. To do.

  From the left side of FIG. 10A, the above-mentioned driver for liquid crystal driving is a logic (for example, 3V) N-channel MOS transistor, a P-channel MOS transistor, a level shifter (for example 30V) N-channel MOS transistor, a high breakdown voltage (For example, 30V) N-channel MOS transistor, high withstand voltage (for example, 30V) N-channel MOS transistor with low on-resistance from the left side of FIG. 10B, high withstand voltage (for example, 30V) It is composed of a P-channel MOS transistor and a high-breakdown-voltage (for example, 30 V) P-channel MOS transistor with low on-resistance. For the sake of convenience of explanation, in order to differentiate the high withstand voltage MOS transistor from the high withstand voltage MOS transistor with low on-resistance, the following description will be made with a high withstand voltage system with low on resistance. This MOS transistor is referred to as an SLED (Slit channel by counter doping with extended shallow drain) MOS transistor.

  In a semiconductor device in which various MOS transistors constituting such a liquid crystal driver are mixedly mounted, as shown in FIG. 10, the high breakdown voltage P-channel MOS transistor and the low breakdown voltage are reduced. The N-type well 23 in which the P-channel type SLED MOS transistor of the system is formed has a step high portion, and the P-type well 22 in which other various MOS transistors are formed in the step low portion. In other words, a fine logic system (for example, 3V) N-channel MOS transistor and P-channel MOS transistor are arranged in a low step portion.

  Hereinafter, a method for manufacturing the semiconductor device will be described.

First, in FIG. 1, in order to demarcate regions for forming various MOS transistors, for example, a P-type well (PW) 22 and an N-type well (NW) 23 are provided in a P-type semiconductor substrate (P-sub) 21. Is formed using the LOCOS method. That is, although the illustrated explanation is omitted, a pad oxide film and a silicon nitride film are formed on the N-type well formation region of the substrate 21, and, for example, boron ions are approximately formed using the pad oxide film and the silicon nitride film as a mask. at an acceleration voltage of 80 KeV, and ion implantation of 8 × ^10/12 cm ² implantation conditions to form an ion implantation layer. Thereafter, the surface of the substrate is field oxidized by the LOCOS method using the silicon nitride film as a mask to form a LOCOS film. At this time, boron ions that have been ion-implanted under the LOCOS film formation region are diffused into the substrate to form a P-type layer.

Next, after removing the pad oxide film and silicon nitride film, phosphorus ions are ion-implanted into the substrate surface with the LOCOS film as a mask at an acceleration voltage of about 80 KeV under an implantation condition of 9 × 10 ¹² / cm ^2. An injection layer is formed. Then, after removing the LOCOS film, each impurity ion implanted into the substrate is thermally diffused to form a P-type well and an N-type well, thereby forming in the substrate 21 as shown in FIG. The P-type well 22 is disposed at a step low portion, and the N-type well 23 is disposed at a step high portion.

  In FIG. 2, an element isolation film 24 of about 500 nm is formed by the LOCOS method in order to isolate each MOS transistor, and a high breakdown voltage of about 80 nm is formed on the active region other than the element isolation film 24. A thick gate oxide film 25 is formed by thermal oxidation.

Subsequently, first low-concentration N-type and P-type source / drain layers (hereinafter referred to as LN layer 26 and LP layer 27) are formed using the resist film as a mask. That is, first, for example, phosphorus ions are ion-implanted under an implantation condition of 8 × 10 ¹² / cm ² at an acceleration voltage of about 120 KeV in a state where a region other than the LN layer formation region is covered with a resist film (not shown). Thus, the LN layer 26 is formed. After that, the region other than the LP layer formation region is covered with a resist film (PR), and, for example, boron ions are ion-implanted at an acceleration voltage of about 120 KeV and an implantation condition of 8.5 × 10 ¹² / cm ^2. The LP layer 27 is formed by implantation. Actually, after the subsequent annealing process (for example, in an N ₂ atmosphere at 1100 ° C. for 2 hours), each ion-implanted ion species is thermally diffused to become the LN layer 26 and the LP layer 27. .

Subsequently, in FIG. 3, the second low-concentration N-type and P-type are formed by using a resist film as a mask between the LN layer 26 and the LP layer 27 where the P-channel and N-channel SLED MOS transistor formation regions are formed. A source / drain layer of a type (hereinafter referred to as SLN layer 28 and SLP layer 29) is formed. That is, first, a region other than the SLN layer formation region is covered with a resist film (not shown) and, for example, phosphorus ions are implanted at an acceleration voltage of about 120 KeV and an injection condition of 1.5 × 10 ¹² / cm ^2. Ions are implanted to form an SLN layer 28 that continues to the LN layer 26. Thereafter, with the resist film (PR) covering a region other than the region on which the SLP layer is formed, for example, boron difluoride ions ( ⁴⁹ BF ²⁺ ) are applied to the substrate surface layer at an acceleration voltage of approximately 140 KeV at 2.5 × 10 ¹² / An SLP layer 29 connected to the LP layer 27 is formed by ion implantation under a cm ² implantation condition. The impurity concentrations of the LN layer 26 and the SLN layer 28 or the LP layer 27 and the SLP layer 29 are set to be substantially the same or one of them is increased.

Further, in FIG. 4, high-concentration N-type and P-type source / drain layers (hereinafter referred to as N + layer 30 and P + layer 31) are formed using the resist film as a mask. That is, first, for example, phosphorus ions are ion-implanted at an acceleration voltage of about 80 KeV and an implantation condition of 2 × 10 ¹⁵ / cm ² in a state in which a region other than the N + layer formation region is covered with a resist film (not shown). Thus, the N + layer 30 is formed. Thereafter, for example, boron difluoride ions are ion-implanted at an acceleration voltage of about 140 KeV under an implantation condition of 2 × 10 ¹⁵ / cm ² in a state where the region other than the P + layer formation region is covered with a resist film (PR). P + layer 31 is formed by implantation.

Next, in FIG. 5, the SLN layer 28 connected to the LN layer 26 is masked with a resist film having an opening diameter smaller than the mask opening diameter for forming the SLN layer 28 and the SLP layer 29 (see FIG. 3). A P-type body layer 32 and an N-type body layer that divide the SLN layer 28 and the SLP layer 29 by ion-implanting a reverse conductivity type impurity into the central portion and the central portion of the SLP layer 29 connected to the LP layer 27, respectively. 33 is formed. That is, first, for example, boron difluoride ions are implanted at 5 × 10 ¹² / cm ² at an acceleration voltage of about 120 KeV into the substrate surface in a state where a region other than the P-type layer formation region is covered with a resist film (not shown). P-type body layer 32 is formed by ion implantation under conditions. Thereafter, for example, phosphorus ions are ion-implanted into the substrate surface layer with a resist film (PR) other than the region on the N-type layer formation region at an acceleration voltage of approximately 190 KeV and an implantation condition of 5 × 10 ¹² / cm ^2. Thus, the N-type body layer 33 is formed. 3 to 5 can be changed as appropriate, and channels are formed in the surface layer portions of the P-type body layer 32 and the N-type body layer 33.

  Further, in FIG. 6, a second P-type well (SPW) 34 and a second N-type are formed in the substrate (P-type well 22) in the region for forming the miniaturized N-channel and P-channel MOS transistors for the normal breakdown voltage. A well (SNW) 35 is formed.

That is, using a resist film (not shown) having an opening on the normal breakdown voltage N-channel MOS transistor formation region as a mask, boron ions, for example, are applied at an acceleration voltage of about 190 KeV and 1.5 × in the P-type well 22. After ion implantation under the first implantation condition of 10 ¹³ / cm ² , boron ions are also implanted under the second implantation condition of 2.6 × 10 ¹² / cm ² at an acceleration voltage of approximately 50 KeV, The P-type well 34 is formed. Further, for example, phosphorus ions are implanted into the P-type well 22 at an acceleration voltage of about 380 KeV with a resist film (PR) having an opening on the normal breakdown voltage P-channel MOS transistor formation region as a mask. Ions are implanted under an implantation condition of ¹³ / cm ² to form a second N-type well 35. If there is no high acceleration voltage generator of about 380 KeV, a double charge method in which divalent phosphorus ions are ion-implanted under an implantation condition of 1.5 × 10 ¹³ / cm ² at an acceleration voltage of about 190 KeV may be used. Subsequently, phosphorus ions are ion-implanted at an acceleration voltage of approximately 140 KeV under an implantation condition of 4.0 × 10 ¹² / cm ² .

  Next, after removing the gate oxide film 25 on the normal breakdown voltage N-channel and P-channel MOS transistor formation regions and the level shifter N-channel MOS transistor formation region, as shown in FIG. A gate oxide film having a desired film thickness is newly formed on the region.

  That is, first, it is about 14 nm for the N-channel type MOS transistor for the level shifter on the entire surface (at this stage, it is about 7 nm, but the film thickness increases when a gate oxide film for normal breakdown voltage described later is formed). A gate oxide film 36 is formed by thermal oxidation. Subsequently, after removing the gate oxide film 36 of the level shifter N-channel MOS transistor formed on the normal breakdown voltage N-channel and P-channel MOS transistor formation regions, the normal breakdown voltage thin film is formed in this region. A gate oxide film 37 (about 7 nm) is formed by thermal oxidation.

Subsequently, in FIG. 8, a polysilicon film having a thickness of about 100 nm is formed on the entire surface. After POCl ₃ is thermally diffused and made conductive using this polysilicon film as a heat diffusion source, a polysilicon film having a thickness of about 100 nm is formed on the polysilicon film. A tungsten silicide film and a SiO ₂ film of about 150 nm are stacked and patterned using a resist film (not shown) to form gate electrodes 38A, 38B, 38C, 38D, 38E, 38F, and 38G for each MOS transistor. To do. The SiO ₂ film serves as a hard mask during patterning.

  Subsequently, in FIG. 9, low concentration source / drain layers are formed for the normal breakdown voltage N-channel and P-channel MOS transistors.

That is, first, using a resist film (not shown) that covers a region other than the low-concentration source / drain layer formation region for a normal breakdown voltage N-channel MOS transistor as a mask, for example, phosphorus ions are applied at an acceleration voltage of about 20 KeV. Ions are implanted under an implantation condition of 6.2 × 10 ¹³ / cm ² to form a low concentration N − -type source / drain layer 39. Further, using a resist film (PR) covering a region other than the low-concentration source / drain layer formation region for a normal breakdown voltage P-channel MOS transistor as a mask, for example, boron difluoride ions are applied at an acceleration voltage of about 20 KeV. Ions are implanted under an implantation condition of 2 × 10 ¹³ / cm ² to form a low concentration P − -type source / drain layer 40.

  Further, in FIG. 10, a TEOS film 41 of about 250 nm is formed by LPCVD so as to cover the gate electrodes 38A, 38B, 38C, 38D, 38E, 38F, and 38G on the entire surface, and the normal breakdown voltage N channel is formed. The TEOS film 41 is anisotropically etched using a resist film (PR) having an opening over the mold and P channel type MOS transistor formation region as a mask. As a result, as shown in FIG. 10, sidewall spacer films 41A are formed on both side walls of the gate electrodes 38A, 38B, and the TEOS film 41 remains as it is in the region covered with the resist film (PR).

  Then, using the gate electrode 38A and the sidewall spacer film 41A, and the gate electrode 38B and the sidewall spacer film 41A as a mask, a high-concentration source transistor for the normal breakdown voltage N-channel and P-channel MOS transistors is used. A drain layer is formed.

That is, using a resist film (not shown) that covers a region other than the high-concentration source / drain layer forming region for a normal breakdown voltage N-channel MOS transistor as a mask, for example, arsenic ions are applied at an acceleration voltage of about 100 KeV. Ions are implanted under the conditions of × 10 ¹⁵ / cm ² to form a high concentration N + type source / drain layer 42. Further, using a resist film (not shown) that covers a region other than the high concentration source / drain layer forming region for the normal breakdown voltage P channel type MOS transistor as a mask, for example, boron difluoride ions are applied at an acceleration voltage of about 40 KeV. Ions are implanted under an implantation condition of 2 × 10 ¹⁵ / cm ² to form a high concentration P + type source / drain layer 43.

  Thereafter, an interlayer insulating film 45 of about 600 nm made of a TEOS film, a BPSG film or the like is formed on the entire surface, and then a metal wiring layer 48 connected in contact with each of the high concentration source / drain layers 30, 31, 42, 43 is formed. By forming, the normal-voltage N-channel MOS transistor and the P-channel MOS transistor, the level shifter N-channel MOS transistor, the high-voltage N-channel MOS transistor and the P-channel constituting the liquid crystal driving driver. A high-breakdown-voltage N-channel SLEDMOS transistor and a P-channel SLEDMOS transistor with reduced on-resistance are completed (see FIG. 11).

  Here, the present invention is characterized in the configuration of a contact portion and a method of forming the contact portion for connecting the metal wiring layer 48 to the source / drain layers 30, 31, 42 and 43.

  Hereinafter, the configuration of the contact portion of the present invention will be described with reference to FIG. In FIG. 11, each N channel type normal withstand voltage MOS transistor (A), high voltage MOS transistor (B), and SLEDMOS transistor (C) will be described as an example. The same applies to the high voltage MOS transistor and the SLEDMOS transistor.

  In the present invention, as shown in FIG. 11, a contact hole 46 that contacts the source / drain layers 30 and 42 is formed in the interlayer insulating film 45, and a conductive film such as a tungsten film is formed in the contact hole 46. A plug contact portion 47 is formed by embedding, a metal wiring layer 48 made of an Al film or the like is formed on the plug contact portion 47, and source / drain electrodes are formed.

  At this time, the arrangement of the plug contact portion 47 is made different for each type of transistor constituting the liquid crystal driving driver. In the present embodiment, at least the source / drain layer 42 of the normal breakdown voltage MOS transistor (A) is provided with the plug contact portions 47 arranged in a row, and the sources of the high breakdown voltage MOS transistor (B) and the SLEDMOS transistor (C). The plug contact portions 47 are arranged in a plurality of rows (for example, two rows) with respect to the drain layer 30 (see FIG. 12).

  Therefore, in the present invention, the contact resistance can be reduced by increasing the number of plug contact portions 47, and the on-resistance of the transistor can be lowered.

  As described above, the present invention has various transistors and forms contact holes with the minimum dimensions in the design rule. By setting and arranging the optimum number of contacts for each transistor, the contact resistance can be reduced. As a result, the on-resistance of the transistor can be reduced.

  Further, not only the tungsten film but also a polysilicon film or the like may be embedded. Furthermore, instead of embedding the conductive film in the contact hole 46 by etching back, the wiring may be used as it is without etching back.

  In this embodiment, the plug contact portions 47 are arranged in one row for the normal withstand voltage MOS transistors. However, in the normal withstand voltage MOS transistors, the plug contact portions 47 are arranged in a plurality of rows. For example, in a normally withstand voltage MOS transistor arranged near the power supply pad, the plug contact portions 47 are arranged in a plurality of rows, thereby improving the reliability and transmitting only the “H” and “L” signals. For example, a configuration in which the plug contact portions 47 are arranged in one row is sufficient.

  Further, in the present embodiment, the contact portion for contact connection to the source / drain layer is described, but the present invention is not limited to this, and is for connecting the lower layer wiring and the upper layer wiring. It can also be applied to the contact portion. Particularly in the case where a high breakdown voltage and a low on-resistance are achieved as in the SLEDMOS transistor, the lower layer wiring and the upper layer wiring (for example, this process has a three-layer wiring structure). The resistance can be further reduced by applying to the contact portion for connecting the two-layer wiring and the three-layer wiring).

It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is a top view which shows the manufacturing method of the semiconductor device of one Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Claims (8)

A first gate oxide film formed on the semiconductor substrate; a first gate electrode formed on the first gate oxide film; and a surface layer of the semiconductor substrate adjacent to the first gate electrode A first transistor comprising a first source / drain layer formed on
A second gate oxide film formed on the semiconductor substrate and having a thickness larger than the first gate oxide film; a second gate electrode formed on the second gate oxide film; A second source / drain layer formed on a surface layer of the semiconductor substrate so as to be adjacent to the second gate electrode, and a second transistor having a higher breakdown voltage than the first transistor,
The number of plug contact portions contact-connected to the first source / drain layer of the first transistor is larger than the number of plug contact portions contact-connected to the second source / drain layer of the second transistor. There are few semiconductor devices. A first gate oxide film formed on the semiconductor substrate; a first gate electrode formed on the first gate oxide film; and a surface layer of the semiconductor substrate adjacent to the first gate electrode A first transistor comprising a first source / drain layer formed on
A second gate oxide film formed on the semiconductor substrate and having a thickness larger than the first gate oxide film; a second gate electrode formed on the second gate oxide film; A second source / drain layer formed on a surface layer of the semiconductor substrate so as to be adjacent to the second gate electrode, and a second transistor having a higher breakdown voltage than the first transistor,
The number of plug contact portions that are contact-connected between the lower layer wiring and the upper layer wiring on the first transistor side is larger than the number of plug contact portions that are contact-connected between the lower layer wiring and the upper layer wiring on the second transistor side. There are few semiconductor devices. In the second transistor, a semiconductor layer constituting a channel is formed below the gate electrode, and a low concentration layer having the same conductivity type as the source / drain layer is formed so as to be in contact with the semiconductor layer. The semiconductor device according to claim 1, wherein the semiconductor device is provided. The semiconductor device according to claim 3, wherein the semiconductor layer is formed in a lower central portion of the second gate electrode. 5. The semiconductor device according to claim 1, wherein the plug contact portion is formed in a contact hole formed with a minimum dimension in a design rule. The semiconductor device according to claim 1, wherein a tungsten film or a polysilicon film is embedded in the plug contact portion. 7. The plug contact portion formed in the first transistor is in one row, and the plug contact portion formed in the second transistor is in a plurality of rows. The semiconductor device according to claim. 7. The semiconductor device according to claim 1, wherein the plug contact portions of the first transistor disposed at a location close to the power supply pad are in a plurality of rows. 8.