JP2007194266A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device with which the semiconductor device can inexpensively be manufactured with a non-volatile memory element, a field effect transistor, and a bipolar transistor, and with a desired characteristic. <P>SOLUTION: The semiconductor device is provided with the non-volatile memory element, the field effect transistor, and the bipolar transistor. One polysilicon film is patterned. A floating gate polysilicon film 33a becoming a base of a floating gate electrode in the non-volatile memory element, and an emitter electrode 62 of the bipolar transistor, are formed together. A floating gate lamination film becoming a base of an insulating film in the non-volatile memory element is formed on the floating gate polysilicon film 33a. A control gate electrode, the insulating film, the floating gate electrode of the non-volatile memory element, and a gate electrode of the field effect transistor, are formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a nonvolatile memory element, a field effect transistor (including a complementary metal oxide semiconductor (CMOS) transistor), and a bipolar transistor are formed on the same substrate, and a nonvolatile memory The present invention relates to a semiconductor device in which a volatile memory element, a field effect transistor and a bipolar transistor are formed on the same substrate.

  A bipolar transistor is a circuit element capable of high-speed operation, and a CMOS transistor, which is one of the field effect transistors, is a circuit element capable of high integration with low power consumption. By integrating the transistors on the same substrate, a high-performance semiconductor device can be obtained. Nowadays, in addition to bipolar transistors and CMOS transistors, a semiconductor device (hereinafter referred to as “BiCMOS device”) that achieves higher performance by mounting a nonvolatile memory element that can be modified and digitally trimmed is also abbreviated. ) Is also being developed.

  FIG. 23 is a cross-sectional view schematically showing an example of a BiCMOS device. The BiCMOS device 100 shown in the figure includes a nonvolatile memory element 40, a CMOS transistor 60, and a bipolar transistor 70 formed on a semiconductor substrate 25.

The semiconductor substrate 25 forms a desired element region by appropriately changing the impurity concentration at a predetermined position of the P-type silicon substrate 2, and further, an element isolation film 24 having a predetermined pattern that locally exposes each of the element regions. Is formed. An N ⁺ type buried layer 5 is formed in the element region corresponding to the nonvolatile memory 40, and on this N ⁺ type buried layer 5, an N type well surrounding the P type well 6 and the P type well 6. 7 are formed. In the P-type well 6, a predetermined number of source regions 8s and drain regions 8d made of N-type impurity diffusion regions are alternately formed at a predetermined interval to constitute a memory cell.

  In the element region corresponding to the CMOS transistor 60, the N-type well 10 and the P-type well 12 are formed adjacent to each other. A source region 10s made of a P-type impurity diffusion region and a drain region 10d are formed in the N-type well 10 at a predetermined interval, and a drain region 12d made of an N-type impurity diffusion region is formed in the P-type well 12. The source region 12s is formed at a predetermined interval.

An N ⁺ buried layer 15 is formed in the element region corresponding to the bipolar transistor 70. An N ⁻ type epitaxial layer 16 is formed from above the N ⁺ type buried layer 15 to the side, and an N type well 17 is formed in the N ⁻ type epitaxial layer 16. A P-type impurity diffusion region 18 and a P-type well 19 formed thereon surround the N ⁺ type buried layer 15 and the N ⁻ type epitaxial layer 16. The N ⁺ type buried layer 15 and the N type well 17 constitute a collector region, and a collector contact region 20 made of a P type impurity diffusion region is formed on the N type well 17. The N ⁻ type epitaxial layer 16 is formed with a base contact region 21 made of a P ⁺ type impurity diffusion region and a base region 22 made of a P ⁻ type impurity diffusion region. An emitter region 23 made of a type impurity diffusion region is formed.

Note that “P ⁻ type”, “P type”, “P ⁺ type”, “N ⁻ type”, “N type”, and “N ⁺ type” represent semiconductor conductivity types, respectively. The P-type impurity (acceptor) concentration in “P ^- type” is higher than the P-type impurity concentration in “P ⁻ -type”, and the P-type impurity concentration in “P ⁺ -type” is P-type impurity in “P-type”. Higher than concentration. Similarly, the N type impurity (donor) concentration in “N type” is higher than the N type impurity concentration in “N ⁻ type”, and the N type impurity concentration in “N ⁺ type” is “N type”. It is higher than the N-type impurity concentration.

  The nonvolatile memory element 40 in the BiCMOS device 100 shown in FIG. 23 has a plurality of memory cells. Each memory cell is formed by an N-type impurity diffusion region and is adjacent to each other between a source region 8s and a drain region 8d and a region (channel) in the P-type well 6 between the source region 8s and the drain region 8d. Region), a floating gate electrode 33 disposed on the region via the tunnel oxide film 31, and a control gate electrode 37 disposed on the floating gate electrode 33 via the insulating film 35. A protective film 39 is formed on the control gate electrode 37. Further, sidewall spacers Sw are formed on both sides in the line width direction of the laminate of the tunnel oxide film 31, the floating gate electrode 33, the insulating film 35, the control gate electrode 37, and the protective film 39. . In FIG. 23, for convenience, hatching is omitted for all the sidewall spacers Sw.

  The CMOS transistor 60 has a P channel MOS transistor 50 and an N channel MOS transistor 55. P-channel MOS transistor 50 is formed of a P-type impurity diffusion region and is adjacent to each other between source region 10s and drain region 10d, and region located between source region 10s and drain region 10d in N-type well 10 ( Channel region) and a gate electrode 44 disposed on this region via a gate insulating film 42. On the gate electrode 44, a protective film 39 is formed as in the memory cell described above. Is formed. In addition, sidewall spacers Sw are formed on both sides in the line width direction of the stack of the gate insulating film 42, the gate electrode 44, and the protective film 39. N-channel MOS transistor 55 has P-type well 12 in place of N-type well 10, and has drain region 12d and source region 12s made of N-type impurity diffusion regions in place of drain region 10d and source region 10s. Except for this, it has the same structure as the P-channel MOS transistor 50.

The bipolar transistor 70 is disposed on the collector region, the collector contact region 20, the base contact region 21, the base region 22, the emitter region 23, and the emitter region 23 formed by the N ⁺ type buried layer 15 and the N type well 17. And an emitter electrode 62. Side wall spacers Sw are formed on both sides of the emitter electrode 62 in the line width direction.

  The nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70 described above are electrically isolated from each other by an element isolation film 24 formed by a method such as LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation). ing. Further, it is covered with an interlayer insulating film 90. The interlayer insulating film 90 is formed with a required number of contact plugs 92 penetrating the interlayer insulating film 90 and having one end in contact with a predetermined impurity diffusion region of the nonvolatile memory element 40, the CMOS transistor 60, or the bipolar transistor 70. . A predetermined upper wiring 94 is connected to the other end of each contact plug 92. In FIG. 23, eight contact plugs 92 and eight upper wirings 94 appear.

  Conventionally, in manufacturing such a BiCMOS device 100, first, on the element region corresponding to the nonvolatile memory element 40, a conductive film that is a source of each floating gate electrode 33 and a stack that is a source of each insulating film 35. A laminate with the film (hereinafter referred to as “first laminate”) is formed. Next, a conductive film serving as the base of the emitter electrode 62 is formed, and this conductive film is patterned by etching to form the emitter electrode 62. Then, after the formation of the emitter electrode 62, a laminate (hereinafter referred to as “second laminate”) of the conductive film that is the source of each control gate electrode 37 and each gate electrode 44 and the inorganic insulating film that is the source of each protective film 39. And the second laminate is patterned to form each control gate electrode 37 and each protective film 39 thereon, and each gate electrode 44 and each protective film 39 thereon. Each floating gate electrode 33 and each insulating film 35 are formed by patterning the first laminate by anisotropic etching using each control gate electrode 37 and each protective film 39 thereon as a mask.

  The insulating film 35 in the nonvolatile memory element 40 is for preventing leakage of charges accumulated in the floating gate electrode 33, and the insulating film 35 is required to have high electrical insulation. For this reason, an ONO film is usually used as the insulating film 35. The ONO film is a laminated film having a three-layer structure formed by stacking an oxide film, a nitride film, and an oxide film in this order. A silicon oxide film is frequently used as the oxide film, and a silicon nitride film is used as the nitride film. Membranes are frequently used. In many cases, the gate electrode 44 in the P-channel MOS transistor 50 and the N-channel MOS transistor 55 and the emitter electrode 62 in the bipolar transistor 70 are formed of polysilicon (doped with impurities).

  An insulating film in the nonvolatile memory element is formed by an ONO film, and a gate electrode in a P-channel MOS transistor or an N-channel MOS transistor and an emitter electrode in a bipolar transistor are each formed by polysilicon (impurities doped). When a BiCMOS device is manufactured by a conventional method, when an emitter electrode is obtained by patterning a polysilicon film, the upper surface of the stacked film (ONO film) in the first stacked body is also exposed to etching and damaged. Then, a control gate electrode is formed on the damaged ONO film.

  When the ONO film is damaged by etching, its electrical insulation characteristics are deteriorated or the film thickness varies. A decrease in the electrical insulation characteristics of the ONO film leads to a decrease in storage characteristics in the nonvolatile memory element. Further, when the film thickness of the ONO film varies, the coupling capacitance between the floating gate electrode and the control gate electrode varies, and this variation leads to a decrease in erase characteristics and write characteristics in the nonvolatile memory element.

  Of course, if the above ONO film is protected with an etching mask when an emitter electrode is obtained, the ONO film can be prevented from being damaged by etching, but one etching mask must be added. Productivity decreases and manufacturing costs increase. As described above, the conventional method for manufacturing the BiCMOS device has a problem that it is difficult to manufacture a nonvolatile memory element having good characteristics at low cost.

  The present invention has been made in view of the above, and a method of manufacturing a semiconductor device that can easily manufacture a semiconductor device having desired characteristics including a nonvolatile memory element, a field effect transistor, and a bipolar transistor at low cost, Another object of the present invention is to obtain a semiconductor device that can easily obtain a device including a nonvolatile memory element having desired characteristics, a field effect transistor, and a bipolar transistor at low cost.

  A method of manufacturing a semiconductor device of the present invention that achieves the above object includes a semiconductor substrate, a nonvolatile memory element having a plurality of memory cells, a field effect transistor having at least one gate electrode, and a bipolar transistor having an emitter electrode. Each of the memory cells has a structure in which an insulating film and a control gate electrode are stacked in this order on a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film. The gate electrode is disposed on the semiconductor substrate via a gate insulating film, and the emitter electrode is a method for manufacturing a semiconductor device disposed in contact with the semiconductor substrate, the nonvolatile memory element, An element region is formed corresponding to each of the field effect transistor and the bipolar transistor, and the element region Each of the element regions while leaving an opening on a region corresponding to a region where the emitter electrode and the semiconductor substrate are in contact with each other on a semiconductor substrate on which an element isolation film having a predetermined pattern for locally exposing each of the semiconductor substrate is formed. An electric insulating film covering the exposed surface of the semiconductor device, and further covering the element isolation film and the electric insulating film formed in at least the element region corresponding to the nonvolatile memory element and the region corresponding to the bipolar transistor, respectively. And forming a first polysilicon film so as to fill the opening, and then patterning the first polysilicon film so that each of the plurality of memory cells is placed on an element region corresponding to the nonvolatile memory element. Forming a floating gate polysilicon film to be a source of the floating gate electrode in the device, A first electrode forming step for forming the emitter electrode and a floating gate stacked film serving as an insulating film in each of the plurality of memory cells are formed so as to cover the floating gate polysilicon film. Forming a conductive film that covers the laminated film forming step, an electrical insulating film on the element region corresponding to the field effect transistor, and the floating gate laminated film, patterning the conductive film, and forming the gate electrode and And a second electrode forming step for forming the control gate electrode. Hereinafter, this manufacturing method is sometimes referred to as “manufacturing method I”.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a semiconductor substrate; a nonvolatile memory element having a plurality of memory cells; a field effect transistor having at least one gate electrode; and an emitter electrode. Each of the memory cells has a structure in which an insulating film and a control gate electrode are stacked in this order on a floating gate electrode formed on the semiconductor substrate via a tunnel oxide film. A method of manufacturing a semiconductor device, wherein the gate electrode is disposed on the semiconductor substrate via a gate insulating film, and the emitter electrode is disposed in contact with the semiconductor substrate, A device region corresponding to each of the memory element, the field effect transistor, and the bipolar transistor; An electrical insulating film is formed on a semiconductor substrate on which an element isolation film having a predetermined pattern for locally exposing each of the element regions is formed, and further covers at least the nonvolatile memory element. A first polysilicon film forming step of forming a first polysilicon film so as to cover the element isolation film and the electric insulating film formed in each of the element region corresponding to the bipolar transistor and the region corresponding to the bipolar transistor; Forming an opening by removing the region of the first polysilicon film located on the region where the emitter electrode and the semiconductor substrate are in contact with each other and the electrical insulating film below the region; A second polysilicon film forming step of forming a second polysilicon film so as to cover the first polysilicon film and fill the opening; A polysilicon layer for floating gate, which is a source of floating gate electrodes in each of the plurality of memory cells, is formed on the element region corresponding to the nonvolatile memory element by patterning the polysilicon film and the second polysilicon film together. A patterning step of forming an emitter polysilicon laminate at the emitter electrode formation position, and an insulating film in each of the plurality of memory cells so as to cover the floating gate polysilicon laminate Forming a conductive film that covers the laminated film forming step for forming the original floating gate laminated film, the electrical insulating film on the element region corresponding to the field effect transistor, and the floating gate laminated film; A gate electrode forming step of patterning a film to form the gate electrode and the control gate electrode. Hereinafter, this production method is sometimes referred to as “Production Method II”.

  According to the manufacturing method I and the manufacturing method II of the present invention, a BiCMOS device can be manufactured without exposing a region to be an insulating film of a nonvolatile memory element in the floating gate laminated film. Further, since the floating gate polysilicon film or the floating gate polysilicon laminate and the emitter electrode are formed together, the total number of masks can be reduced as compared with the conventional case. As a result, the manufacturing method I and the manufacturing method II make it easy to manufacture a semiconductor device having desired characteristics including a nonvolatile memory element, a field effect transistor, and a bipolar transistor at low cost.

  Hereinafter, a method for manufacturing a semiconductor device and embodiments of the semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

Embodiment 1 FIG.
The first embodiment is an example when the semiconductor device having the cross-sectional structure shown in FIG. 23 is manufactured based on the manufacturing method I described above. As already described, the manufacturing method I includes the first electrode forming step, the laminated film forming step, and the second electrode forming step. After the second electrode formation process, a predetermined post-process is performed. In the following, the reference numerals used in FIG. Description of components already described with reference to FIG. 23 is omitted here.

(First electrode forming step)
In the first electrode formation step, first, element regions are formed corresponding to each of the nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70 shown in FIG. On the semiconductor substrate on which the element isolation film 24 having a predetermined pattern to be exposed is formed, the element region is formed while leaving an opening in a region corresponding to a region where the emitter electrode 62 of the bipolar transistor and the semiconductor substrate are in contact with each other. An electric insulating film is formed to cover each exposed surface. Hereinafter, the semiconductor substrate on which the electrical insulating film is formed is abbreviated as “semiconductor substrate with insulating film”. The semiconductor substrate with an insulating film may be manufactured by itself or may be purchased by another manufacturer. FIGS. 1-1 and 1-2 are cross-sectional views schematically showing intermediate products produced in the process of obtaining a desired semiconductor substrate with an insulating film.

The intermediate product 25A shown in FIG. 1-1 corresponds to a predetermined element region on the P-type silicon substrate 2, that is, an element region R ₁ corresponding to a nonvolatile memory, an element region R ₂ corresponding to a CMOS transistor, and a bipolar transistor. after forming the device region R ₃ that, in these device regions R ₁ to R _3, the isolation layer 24 having a predetermined pattern to expose locally each of the element regions R ₁ to R _3, the element region R ₁ to R ₃ is obtained by forming an electrically insulating film 31a to cover the respective exposed surfaces. The element region R ₁ are N ⁺ -type buried layer 5, the P-type well 6, and N-type well 7 is formed, N-type well 10 and the P-type well 12 is formed in the element region R _2. In the element region R ₃ , an N ⁺ type buried layer 15, an N ⁻ type epitaxial layer 16, an N type well 17, a P type impurity diffusion region 18, and a P type well 19 are formed.

Unlike the semiconductor substrate 25 shown in FIG. 23, the source region and the drain region are not formed in the element region R ₁ and the element region R ₂ in the P-type silicon substrate 2 in the intermediate product 25A. . In the element region R ₃ , the collector contact region, the base contact region, the base region, and the emitter region are not formed.

  Each well, buried layer, epitaxial region, element isolation film, and electrical insulating film constituting the intermediate product 25A can be formed by ordinary methods. Further, the impurity concentration in each well and the epitaxial region and the thickness of the electrical insulating film 31a are the performance required for each of the nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70 (see FIG. 23) to be formed. It is appropriately selected according to the above. When the electrical insulating film 31a is used as a material for a tunnel oxide film in a nonvolatile memory element, the film thickness can be set to about 10 to 12 nm, for example.

The intermediate product 25B shown in FIG. 1-2 has a P-type impurity diffusion that becomes the base region of the base region in the bipolar transistor 70 (see FIG. 23) in the N ⁻ type epitaxial layer 16 in the intermediate product 25A shown in FIG. The region 22a is further formed. In forming the P-type impurity diffusion region 22a, for example, as shown in the figure, first, an ion implantation mask M ₁ having an opening OP ₁ formed at a position corresponding to the formation region of the P-type impurity diffusion region 22a is formed by P The acceptor A is ion-implanted into the P-type semiconductor substrate 2 through the electrical insulating film 31a. Thereafter, heat treatment is performed to activate the implanted acceptor A. As a result, a P-type impurity diffusion region 22a is formed, and an intermediate product 25B shown in the figure is obtained.

1-3 is a cross-sectional view schematically showing an example of a semiconductor substrate with an insulating film manufactured in the first electrode formation step. In the semiconductor substrate with an insulating film 25C shown in the figure, the electrical insulating film 31a in the intermediate product 25B shown in FIG. 1-2 is removed by, for example, wet etching, and the surface of the P-type silicon substrate 2 exposed thereby is thermally oxidized. After the electrical insulating film 31b is newly formed by the above method, the electrical insulating film 31b is patterned, and an opening is formed on a region corresponding to a region where the emitter electrode 62 (see FIG. 23) and the P-type silicon substrate are in contact with each other. The part OP ₂ is formed. The electrical insulating film 31b covers the exposed surfaces of the element regions R _{1 to} R ₃ while leaving the opening OP ₂ .

In the first electrode formation step, after the above-described semiconductor substrate with an insulating film 25C is fabricated, an element region R ₁ corresponding to at least the nonvolatile memory element 40 (see FIG. 23) is formed on the semiconductor substrate with an insulating film 25C. bipolar transistor 70 of the first polysilicon film so as to fill the openings OP ₂ covers the device isolation film 24 and the electrically insulating film 31b is formed on each region R ₃ corresponding to (see FIG. 23) formed Film. Then, the first polysilicon film is patterned to form a floating gate polysilicon film serving as a source of the floating gate electrode 33 (see FIG. 23) in each memory cell constituting the nonvolatile memory element 40 in the element region R _1. And the emitter electrode 62 (see FIG. 23) of the bipolar transistor 70 is formed in the element region R ₃ . As the first polysilicon film, for example, an N-type polysilicon film can be used. The film thickness of the first polysilicon film can be set to, for example, about 150 nm.

FIG. 2-1 is a cross-sectional view schematically showing an example of a first polysilicon film formed in the first electrode formation step. The first polysilicon film 32 shown in the figure is formed above the element regions R ₁ , R ₂ , and R ₃ so as to cover each of the element isolation film 24 and the electrical insulating film 31b. _In FIG. ₃ , the opening OP ₂ is filled.

FIG. 2B is a cross-sectional view schematically showing an example of the floating gate polysilicon film and the emitter electrode formed in the first electrode formation step. As shown in the figure, the polysilicon film 33a for the floating gate, the nonvolatile memory device 40 so as to cover the electrical insulating film 31b on the element region R ₁ corresponding to (see FIG. 23), the element region R ₁ above Formed. The emitter electrode 62 is formed in the element region R ₃ in contact with the P-type impurity diffusion region 22a. The patterning of the first polysilicon film 32 for obtaining the floating gate polysilicon film 33a and the emitter electrode 62 can be performed, for example, by dry etching or wet etching using an etching mask having a predetermined shape.

  After performing the first electrode forming process in this way, a donor is ion-implanted into the P-type impurity diffusion region 22a using an ion implantation mask having a predetermined shape, and an activation process is performed to form an N-type impurity diffusion region. An emitter region made of is formed in the P-type impurity diffusion region 22a. The ion implantation at this time can be performed through the emitter electrode 62.

  FIG. 3 is a cross-sectional view schematically showing an example of an emitter region formed after the first electrode formation step. As shown in the figure, the emitter region 23 mainly extends downward from the interface between the emitter electrode 62 and the P-type impurity diffusion region 22a. The depth of the emitter region 23 is the same as that before the emitter region 23 is formed. This is shallower than the depth of the P-type impurity diffusion region 22a. The semiconductor substrate 25C with an insulating film shown in FIG. 1C formed up to the emitter region 23 is hereinafter referred to as “semiconductor substrate with an insulating film 25D”, and is also denoted by reference numeral 25D in FIG.

(Laminated film forming process)
In the laminated film forming step, the insulating film 35 (see FIG. 23) in each of the plurality of memory cells constituting the nonvolatile memory element is formed so as to cover the floating gate polysilicon film 33a (see FIG. 3). A laminated film for a floating gate is formed. The floating gate laminated film is formed, for example, by patterning the laminated film after forming the laminated film as a base of the floating gate laminated film.

FIG. 4A is a cross-sectional view schematically illustrating an example of a stacked film that is a source of the floating gate stacked film. As shown in the drawing, the laminated film 34 is provided above the element regions R _{1 to} R ₃ from the element region R ₁ to the element region R ₂ and the element region R ₃ . The laminated film 34 is a film having a laminated structure made of, for example, an ONO film or an ON film, but is drawn as one layer for convenience in FIG.

  Note that the ON film is a laminated film having a two-layer structure formed by laminating an oxide film and a nitride film in this order. A silicon oxide film is often used as the oxide film, and a silicon film is used as the nitride film. A nitride film is frequently used.

FIG. 4B is a cross-sectional view schematically showing an example of a laminated film for floating gate formed in the laminated film forming step. As shown in the figure, the laminated film 35a for the floating gate is formed above the element region R _1, to cover the polysilicon film 33a for the floating gates. Electrical insulating film 31b on the electrical insulating film 31b and the element region R ₃ on the element region R ₂ are exposed.

(Second electrode forming step)
In the second electrode formation step, a conductive film is formed covering the electrical insulating film on the element region R ₂ and the floating gate laminated film 35a, and the conductive film is patterned to form each gate electrode constituting the CMOS transistor. 44 (see FIG. 23) and each control gate electrode 37 (see FIG. 23) constituting the nonvolatile memory element are formed.

  In order to improve the performance of the CMOS transistor 60 (see FIG. 23), a region (hereinafter referred to as the following) located in the element region corresponding to the nonvolatile memory element 40 (see FIG. 23) in the electrical insulating film 31b. The remaining region except the electric insulating film 31b in this region is referred to as “electric insulating film 31c”) is removed by, for example, wet etching, and the exposed surface of the P-type silicon substrate 2 is subjected to a method such as thermal oxidation. It is preferable to form the conductive film after forming a new electrical insulating film. In order to facilitate the formation of the floating gate electrode 33 (see FIG. 23), it is preferable to further stack an inorganic insulating film on the conductive film.

FIG. 5A is a cross-sectional view schematically illustrating an example of a conductive film formed in the second electrode formation step. As shown in the figure, the conductive film 37a is formed so as to cover the element regions R ₂ and R ₃ and the floating gate laminated film 35a. As the conductive film 37a, for example, an N-type polysilicon film, a laminated film of an N-type polysilicon film and a tungsten silicide film, or the like can be used, and the film thickness can be set to about 200 nm, for example.

In the illustrated example, a new electrical insulating film 42a is formed on the surface of the P-type silicon substrate 2 in the element regions R ₂ and R ₃ . The electrical insulating film 42a is a source of the gate insulating film 42 (see FIG. 23) in the CMOS transistor, and is formed of silicon oxide or the like. The film thickness of the electrical insulating film 42a can be, for example, about 10 to 15 nm.

  Further, the above-described inorganic insulating film 39a is laminated on the conductive film 37a. The inorganic insulating film 39a is used as a material for an etching protective film when the floating gate electrode 33 (see FIG. 23) is formed by anisotropic etching, and is formed of, for example, silicon oxide. The film thickness of the inorganic insulating film 39a is appropriately selected according to the material, the film thickness of each of the floating gate laminated film 35a and the floating gate polysilicon film 33a, and the like.

  The patterning of the conductive film 37a in the case of providing the inorganic insulating film 39a is, for example, that a resist pattern having a predetermined shape is formed on the inorganic insulating film 39a, and the resist pattern is used as an etching mask to form the inorganic insulating film 39a and the conductive film 37a. Is performed by etching. By this patterning, each control gate electrode 37 (see FIG. 23) in the nonvolatile memory element and each gate electrode 44 (see FIG. 23) in the CMOS transistor are formed.

  FIG. 5B is a cross-sectional view schematically showing an example of each of the control gate electrode and the gate electrode formed in the second electrode formation step. As shown in the figure, each control gate electrode 37 is formed on the floating gate laminated film 35a, and each gate electrode 44 is formed on the electrical insulating film 42a. On each control gate electrode 37 and each gate electrode 44, a protective film 39 formed of an inorganic insulating film 39a is located.

  After performing the second electrode formation process described above, (1) formation of floating gate electrode, (2) formation of tunnel oxide film in nonvolatile memory element and gate insulating film in CMOS transistor, (3) sidewall Formation of spacers, (4) formation of source and drain regions in each of the nonvolatile memory element and the CMOS transistor, (5) formation of collector contact region and base contact region in the bipolar transistor, (6) formation of contact plugs, and ( 7) By sequentially forming the upper wiring, a semiconductor device having the same structure as that of the BiCMOS device 100 shown in FIG. 23 can be obtained. Hereinafter, the formation method of each member formed after performing a 2nd electrode formation process is demonstrated.

  The floating gate electrode 33 (see FIG. 23) uses, for example, the protective film 39 (see FIG. 5-2) on each control gate electrode 37 as an etching protective film, and in the element region corresponding to the nonvolatile memory element. It can be formed by anisotropic etching (for example, dry etching) using the electrical insulating film 31c and the element isolation film 24 (see FIG. 5-2) as an etching stopper.

FIG. 6 is a cross-sectional view schematically showing the floating gate electrode formed by the anisotropic etching. As shown in the figure, the anisotropic etching of the above, perform other region excluding the element area corresponding to the non-volatile memory device in a state where protected by the etching mask M _2. Of each of the floating gate laminated film 35a and the floating gate polysilicon film 33a (see FIG. 5-2), the region overlapping the protective film 39 in plan view is protected from anisotropic etching, and the other regions are anisotropic. It is removed by etching. As a result, a predetermined number of floating gate electrodes 33 are formed on the electrical insulating film 31c. On each floating gate electrode 33, an insulating film 35 formed from the floating gate laminated film 35 a is positioned. On the insulating film 35, the control gate electrode 37 and the protective film 39 described above are arranged in this order. Are stacked.

The tunnel oxide film 31 (see FIG. 23) in the nonvolatile memory element and the gate insulating film 42 (see FIG. 23) in the CMOS transistor remove the etching mask M ₂ (see FIG. 6) used when forming the floating gate electrode 33. Formed after. For example, the tunnel oxide film 31 is removed by dry etching of a region not covered by the floating gate electrode 33 in the electrical insulating film 31c and a region not covered by the gate electrode 44 in the electrical insulating film 42a. In addition, a gate insulating film 42 (see FIG. 23) can be formed.

  For example, after the sidewall spacer is formed up to the tunnel oxide film 31 and the gate insulating film 42, a silicon oxide film or silicon nitride film having a predetermined thickness is formed isotropically on the P-type silicon substrate 2 (see FIG. 6). It can be formed by filming and etching back this film. The side wall spacer includes (1) a tunnel oxide film 31, a floating gate electrode 33, an insulating film 35, a control gate electrode 37, and a protective film 39 on both sides in the line width direction, and (2) gate insulation. The film 42 (see FIG. 23), the gate electrode 44 and the protective film 39 are formed on both sides in the line width direction, and (3) the emitter electrode 62 is formed on both sides in the line width direction. Among these side wall spacers, the side wall spacers constituting the nonvolatile memory element 40 (see FIG. 23) are the side wall spacers constituting the CMOS transistor 60 (see FIG. 23) and the bipolar transistor 70 (see FIG. 23). It is preferably formed in a separate process from the side wall spacer to be formed.

  The formation of the source region and the drain region in each of the nonvolatile memory element and the CMOS transistor and the formation of the collector contact region or the base contact region in the bipolar transistor can be performed in parallel.

  For example, by ion implantation using an ion implantation mask having a predetermined shape, a region corresponding to each of the source region 8s and the drain region 8d (see FIG. 23) of the nonvolatile memory element, a source region 12s of the N-channel MOS transistor 55 in the CMOS transistor. Impurity-doped regions are formed by implanting donor ions into regions corresponding to the drain and drain regions 12d (see FIG. 23) and regions corresponding to the collector contact region 20 (see FIG. 23) of the bipolar transistor. In addition, by ion implantation using another ion implantation mask, regions corresponding to the source region 10s and the drain region 10d (see FIG. 23) of the P-channel MOS transistor 50 in the CMOS transistor, and the base contact region 21 ( An acceptor ion is implanted into a region corresponding to FIG. 23) to form an impurity added region. Thereafter, a necessary number of impurity diffusion regions can be formed by performing heat treatment for impurity activation on these impurity added regions.

FIG. 7 is a cross-sectional view schematically showing an example of an ion implantation mask used when an acceptor is ion-implanted after a donor is ion-implanted. As shown in the figure, the ion implantation mask M ₃ includes an opening OP ₅ opened on the element region corresponding to the P-channel MOS transistor 50 (see FIG. 23) and the base contact region 21 ( And an opening OP ₆ opened on a region corresponding to FIG. 23). Among the acceptors A that have entered the openings OP ₅ and OP ₆ , the acceptor A that is not blocked by the protective film 39, the sidewall spacer Sw, or the element isolation film 24 is injected into the P-type silicon substrate 2. After adding impurities (donor and acceptor) to the P-type silicon substrate 2 in this way, these impurities are activated to form an impurity diffusion region, whereby the semiconductor substrate 25 shown in FIG. 23 is obtained.

  In FIG. 7, for the sake of convenience, not the impurity-added regions formed by the ion implantation described above, but the impurity diffusion regions obtained by activating the added impurities, that is, the source regions, the drain regions, and Each contact region is shown. Further, hatching to the sidewall spacer Sw is omitted.

  If necessary, each of the source region and the drain region can have an LDD (Lightly Doped Drain) structure. In forming the source region and the drain region of the LDD structure, for example, ions are implanted into the P-type silicon substrate 2 before forming the sidewall spacers Sw, so that the impurity dose is small and the impurity implantation depth is also small. A shallow impurity diffusion region is formed, and then a sidewall spacer Sw is formed, and then ion implantation is performed again on the P-type silicon substrate 2 to form an impurity diffusion region having a large impurity dose and a deep impurity implantation depth. Form.

  Each contact plug 92 (see FIG. 23) connected to the nonvolatile memory element, the CMOS transistor, or the bipolar transistor can be formed as follows, for example. First, an interlayer insulating film 90 (see FIG. 23) is formed of a desired organic material or inorganic material on the semiconductor substrate 25 formed as described above, and a predetermined portion of the interlayer insulating film 90 is penetrated by anisotropic etching. A hole is formed. Next, a conductive material such as tungsten or tungsten-aluminum alloy is deposited in each through hole by an evaporation method. Thereafter, excess conductive material deposited on the upper surface of the interlayer insulating film 90 is removed to form contact plugs 92 in the respective through holes.

  For the upper wiring 94 (see FIG. 23) connected to each contact plug, for example, a conductive layer is formed on the interlayer insulating film 90 after the contact plug 92 is formed, and an etching mask having a predetermined shape is formed on the conductive layer. Later, the conductive film can be formed by etching. It is also possible to use damascene wiring as the upper wiring 94. By forming the upper wiring 94, a BiCMOS device having the same structure as the BiCMOS device 100 shown in FIG. 23 can be obtained.

  In the BiCMOS device thus manufactured, the floating gate polysilicon film 33a and the emitter electrode 62, which are the basis of each floating gate electrode 33 (see FIG. 23), are formed in the same process, and thereafter each insulating film is formed. A floating gate laminated film 35a which is a source of 35 is formed. Further, after forming a conductive film 37a and an inorganic insulating film 39a (see FIG. 5-1) covering the floating gate laminated film 35a and patterning them to form the control gate electrode 37 and the protective film 39, the insulating film 35 and the floating gate electrode 33 are formed. The upper surface of the floating gate laminated film 35a (insulating film 35) is not exposed to the etching process throughout the entire process.

  For this reason, the electrical insulating characteristics of the floating gate laminated film 35a are reduced during the manufacturing process of the BiCMOS device, and the variation in the film thickness of the floating gate laminated film 35a is suppressed. As a result, the electrical insulation characteristics of the individual insulating films 35 constituting the nonvolatile memory element 40 (see FIG. 23) and the coupling capacitance between the floating gate electrode 33 and the control gate electrode 37 are within the desired ranges, respectively. It becomes easy to accommodate, and it becomes easy to form the nonvolatile memory element 40 having desired storage characteristics, erasing characteristics, and writing characteristics. Also, the total number of masks used in the BiCMOS device manufacturing process is reduced. Therefore, it becomes easy to obtain a BiCMOS device having desired characteristics at a low manufacturing cost.

Embodiment 2. FIG.
In the second embodiment, a BiCMOS device is manufactured by the manufacturing method II described above. In the BiCMOS device manufactured by the manufacturing method II, each of the floating gate electrode and the emitter electrode has a two-layer structure.

  FIG. 8 is a cross-sectional view schematically showing a BiCMOS device having the above structure. In the BiCMOS device 200 shown in the figure, the floating gate electrode 133 in the nonvolatile memory element 140 has a two-layer structure of a first floating gate electrode 133a and a second floating gate electrode 133b stacked thereon, and The bipolar transistor 170 has the same structure as that of the BiCMOS device 100 shown in FIG. 23 except that the emitter electrode 162 has a two-layer structure of the first emitter electrode 162a and the second emitter electrode 162b. Yes. Of the constituent members shown in FIG. 8, those common to the constituent members shown in FIG. 23 are assigned the same reference numerals as those used in FIG. 23, and descriptions thereof are omitted.

  In manufacturing the BiCMOS device 200 having such a structure by the manufacturing method II, the first polysilicon film forming step, the second polysilicon film forming step, the patterning step, the stacked film forming step, and the gate electrode forming step are sequentially performed. After performing, a predetermined post process is performed. Hereinafter, the reference numerals used in FIG. Description of the components already described in the first embodiment is omitted here.

(First polysilicon film forming step)
In the first polysilicon film forming step, element regions are formed corresponding to the nonvolatile memory element 140, the field effect transistor 60, and the bipolar transistor 170 (see FIG. 8), and each of the element areas is locally exposed. On the semiconductor substrate on which the element isolation film having a predetermined pattern to be formed is formed, an electrical insulating film is formed to cover the exposed surface of each of the element regions, and at least an element region corresponding to the nonvolatile memory element 140 and the bipolar transistor 170 A first polysilicon film is formed so as to cover the element isolation film and the electrical insulating film formed in each of the regions corresponding to.

  As the semiconductor substrate, for example, a P-type silicon substrate 2 shown in FIG. 1-2 is used. Further, a polysilicon film doped with impurities, for example, an N-type polysilicon film, is used as the first polysilicon film, and the film thickness can be set to, for example, about 50 nm.

  In order to improve the performance of each of the nonvolatile memory element 140 and the CMOS transistor 60 (see FIG. 8), the P-type silicon substrate 2 is formed with a P-type in the same manner as in the case of obtaining the intermediate product 25B shown in FIG. After forming up to the impurity diffusion region 22a, the electrical insulating film 31a (see FIG. 1-2) on the surface is removed by wet etching, for example, and the exposed surface of the P-type silicon substrate 2 is newly added by a method such as thermal oxidation. It is preferable to form an electrical insulating film. In this case, the first polysilicon film is formed after a new electrical insulating film is formed.

FIG. 9 is a cross-sectional view schematically showing an example of the first polysilicon film formed in the first polysilicon film forming step. The first polysilicon film 132a shown in the figure is formed on the P-type silicon substrate 2 up to the P-type impurity diffusion region 22a in the same manner as in the case of obtaining the intermediate product 25B shown in FIG. The film 31a (see FIG. 1-2) is removed to form a new electric insulating film 131a, and then formed so as to cover each of the element isolation film 24 and the electric insulating film 131a. The first polysilicon film 132a is formed by N-type polysilicon, over the device region R ₃ corresponding to the element region R ₂ and the bipolar transistor corresponds to the CMOS transistors from the element region R ₁ corresponding to the non-volatile memory device Yes. Note that the new electrical insulating film 131a is formed of silicon oxide or the like. The thickness of the electrical insulating film 131a can be set to, for example, about 10 to 12 nm. Hereinafter, the semiconductor substrate in which the electric insulating film 31a (see FIG. 1-2) is removed and a new electric insulating film 131a is formed is referred to as “semiconductor substrate with insulating film 25E”. In FIG. Show.

(Second polysilicon film forming step)
In the second polysilicon film forming step, in the first polysilicon film 132a, a region located on a region where the emitter electrode 162 (see FIG. 8) and the P-type silicon substrate 2 are in contact with each other and below the region. After removing the electrical insulating films 131a to form openings, a second polysilicon film is formed to cover the first polysilicon film 132a and fill the openings.

  The opening may be formed, for example, by forming an etching mask having a predetermined shape on the first polysilicon film 132a and then performing an etching process on the first polysilicon film 132a and the electrical insulating film therebelow. it can. Further, as the second polysilicon film, a polysilicon film doped with impurities, for example, an N-type polysilicon film is used, and the film thickness can be set to, for example, about 100 nm.

FIG. 10 is a cross-sectional view schematically showing an example of the second polysilicon film formed in the second polysilicon film forming step. As shown in the figure, in the first polysilicon film 132a, a region located on a region where the emitter electrode 162 (see FIG. 8) and the P-type silicon substrate 2 are in contact with each other, and an electric insulating film 131a below the region. Is formed with an opening OP ₁₀ reaching the P-type silicon substrate 2. The second polysilicon film 132b covers the first poly-silicon film 132a so as to fill the opening OP _10, are formed on element regions R ₁ to R _3.

(Patterning process)
In the patterning step, the first polysilicon film and the second polysilicon film described above are patterned together to form a floating gate polysilicon stack that is the basis of each floating gate electrode 133 (see FIG. 8). An emitter polysilicon laminate is formed at the formation position of the emitter electrode 162 (see FIG. 8).

FIG. 11 is a cross-sectional view schematically showing an example of each of the floating gate polysilicon laminate and the emitter polysilicon laminate formed in the patterning step. As shown in the drawing, the floating gate polysilicon stacked body 133A is composed of a first floating gate polysilicon film 133a composed of a region of the first polysilicon film 132a and a region of the second polysilicon film 132b. It is a laminated body with the second floating gate polysilicon film 133b. The floating gate polysilicon laminate 133A is non-volatile memory device 140 so as to cover the electrical insulating film 131a on the element region R ₁ corresponding to (see FIG. 8), are formed on the element region R ₁ .

  The emitter polysilicon laminate 162 includes a first emitter polysilicon film 162a composed of a region of the first polysilicon film 132a and a second emitter polysilicon film composed of a region of the second polysilicon film 132b. The second emitter polysilicon film 162b is in contact with the P-type impurity diffusion region 22a. In patterning the first polysilicon film 132a and the second polysilicon film 132b together, an etching mask having a predetermined shape is formed on the second polysilicon film 132b, and then the first polysilicon film 132a and the second polysilicon film 132b are formed. Etching is performed on the polysilicon film 132b.

  As described above, each of the first polysilicon film 132a and the second polysilicon film 132b is a polysilicon film doped with impurities. Therefore, the floating gate polysilicon laminate 133A is the same as that in the first embodiment. This corresponds to the floating gate polysilicon film 33a (see FIG. 2-2). Further, the emitter polysilicon laminate 162 becomes an emitter electrode (hereinafter referred to as “emitter electrode 162”) as it is. Hereinafter, a portion of the emitter electrode 162 formed from the first polysilicon film 132a is referred to as a first emitter electrode 162a, and a portion formed from the second polysilicon film 132b is referred to as a second emitter electrode 162b.

  After performing the patterning process in this way, a donor is ion-implanted into the P-type impurity diffusion region 22a using an ion implantation mask having a predetermined shape, and an activation process is performed to form an emitter region composed of an N-type impurity diffusion region. Is formed in the P-type impurity diffusion region 22a. The ion implantation at this time can be performed through the emitter electrode 162.

  FIG. 12 is a cross-sectional view schematically showing an example of the emitter region 23 formed as described above. The emitter region 23 extends mainly below the interface between the emitter electrode 162 and the P-type impurity diffusion region 22a, and the depth thereof is greater than the depth of the P-type impurity diffusion region 22a before the emitter region 23 is formed. Also shallow. Since the P-type silicon substrate 2 formed up to the emitter region 23 corresponds to the semiconductor substrate 25D shown in FIG. 3, it is also denoted by reference numeral “25D” in FIG.

(Laminated film formation process)
In the laminated film forming step, the insulating film 35 (see FIG. 8) in each of the plurality of memory cells constituting the nonvolatile memory element is formed so as to cover the floating gate polysilicon laminated body 133A (see FIG. 12). A laminated film for a floating gate is formed. Since this laminated film forming step is performed in the same manner as the laminated film forming step in the first embodiment, the description thereof is omitted here.

(Gate electrode formation process)
In the gate electrode formation step, a conductive film covering the electrical insulating film 131a and the floating gate laminated film 133A on the element region R ₂ (see FIG. 12), and patterning the conductive film, a CMOS transistor Then, each gate electrode 44 (see FIG. 8) and each control gate electrode 37 (see FIG. 8) constituting the nonvolatile memory element are formed. Since this gate electrode forming step is performed in the same manner as the second electrode forming step in the first embodiment, the description thereof is omitted here.

  In order to improve the performance of the CMOS transistor 60 (see FIG. 8), a region located on the element region corresponding to the nonvolatile memory element 140 (see FIG. 8) in the electrical insulating film 131a is used. The removed remaining region is removed by, for example, wet etching, and an electric insulating film is newly formed on the exposed surface of the P-type silicon substrate 2 by a method such as thermal oxidation, and then the conductive film is formed. It is preferable.

  After performing the above-described gate electrode formation step, (1) formation of floating gate electrode, (2) tunnel oxide film in the nonvolatile memory element and gate insulating film in the CMOS transistor, respectively, as in the first embodiment. Formation, (3) formation of sidewall spacers, (4) formation of source and drain regions in each of the nonvolatile memory element and the CMOS transistor, (5) formation of collector contact region and base contact region in the bipolar transistor, (6) The BiCMOS device 200 shown in FIG. 8 can be obtained by sequentially forming the contact plug and (7) the upper wiring.

  In the BiCMOS device 200 manufactured in this way, the floating gate polysilicon laminate 133A and the emitter electrode 162, which are the basis of the floating gate electrode 133 (see FIG. 8), are formed in the same process (FIG. 12). As in the first embodiment, the upper surface of the floating gate laminated film formed in the laminated film forming process is not exposed to the etching process throughout the entire process.

  As a result, the electric insulation characteristics of the individual insulating films 35 (see FIG. 8) constituting the nonvolatile memory element 140 and the coupling capacitance between the floating gate electrode 33 and the control gate electrode 37 are within desired ranges, respectively. It is easy to form the nonvolatile memory element 140 having desired storage characteristics, erasing characteristics, and writing characteristics. Also, the total number of masks used in the manufacturing process of the BiCMOS device 200 is reduced. Therefore, it becomes easy to obtain a BiCMOS device having desired characteristics at a low manufacturing cost.

  Further, after forming an electrical insulating film as a source of the tunnel oxide film 31 and the gate insulating film 42 (see FIG. 8), a first polysilicon film 132a and a second polysilicon film 132b are stacked on the electrical insulating film. Therefore (see FIG. 10), the upper surfaces of the tunnel oxide film 31 and the gate insulating film 42 are prevented from coming into contact with the etching mask or the ion implantation mask throughout the entire process. When the tunnel oxide film 31 and the gate insulating film 42 are formed in this way, the high-quality tunnel oxide film 31 and the gate insulating film 42 can be obtained. Therefore, the highly reliable nonvolatile memory element 140 and the CMOS transistor 60 are manufactured. It becomes easy.

Embodiment 3 FIG.
The third embodiment relates to another manufacturing method of the BiCMOS device 200 (see FIG. 8) in which the floating gate electrode in the nonvolatile memory element and the emitter electrode in the bipolar transistor each have a two-layer structure. . In this manufacturing method as well as in the second embodiment described above, the first polysilicon film forming step, the second polysilicon film forming step, the patterning step, the laminated film forming step, and the gate electrode forming step are sequentially performed before the predetermined process. The BiCMOS device 200 is obtained by performing the post-process.

  The difference from the manufacturing method described in the second embodiment is that an undoped polysilicon film, that is, a polysilicon film not doped with impurities is formed in the first polysilicon film forming step and the second polysilicon film forming step, respectively. The “doping step” is performed after the second polysilicon film forming step. In this doping step, arsenic (As) is doped into the undoped polysilicon films formed in the first polysilicon film forming step and the second polysilicon film forming step, respectively, and these polysilicon films are made into N-type polysilicon. The emitter region 23 (see FIG. 8) of the bipolar transistor 170 is formed while forming a film.

  The undoped polysilicon is changed to N-type polysilicon and arsenic (As) for forming the emitter region 23 can be doped after the patterning step. However, from the viewpoint of reducing the total number of masks used for manufacturing the BiCMOS device, it is preferable to perform the doping process described above after the second polysilicon film forming process and before the patterning process.

FIG. 13 is a cross-sectional view schematically showing a state when arsenic (As) is doped by an ion implantation method in a doping step. As shown in the figure, the ion implantation of arsenic (As), without providing the ion implantation mask is formed on the second polysilicon film 132U _2, carried out in the second polysilicon film 132U ₂ entirely. The acceleration voltage of arsenic ions at this time can be about 40 keV, for example, and the concentration of arsenic ions to be implanted can be about 1 × 10 ¹⁶ / cm ^2, for example. By this ion implantation, arsenic ions are implanted into the first polysilicon film 132U ₁ and the second polysilicon film 132U ₂ and also into the P-type impurity diffusion region 22a via these polysilicon films 132U ₁ and 132U _2. Arsenic ions are implanted. Since other regions in the P-type silicon substrate 2 are covered with the electrical insulating film 131a or the element isolation film 24, the implantation of arsenic ions is suppressed.

FIG. 14 is a cross-sectional view schematically showing an example of each of the N-type polysilicon films 132c and 132d and the emitter region 23 formed by activating the arsenic ions implanted as described above. The 1 N-type polysilicon film 132c of the polysilicon film 132U ₁ is formed, N-type polysilicon film 132d from the second polysilicon film 132U ₂ is formed. N-type polysilicon film 132c corresponds to the first polysilicon film in the second embodiment, and N-type polysilicon film 132d corresponds to the second polysilicon film in the second embodiment. The activation of the ion-implanted arsenic (As) can be performed, for example, by performing a heat treatment at 850 ° C. for 30 minutes in a nitrogen gas atmosphere.

  Thereafter, the patterning step, the laminated film forming step, and the gate electrode forming step are sequentially performed in the same manner as in the second embodiment. Then, after performing the gate electrode formation step, (1) formation of the floating gate electrode, and (2) formation of the tunnel oxide film in the nonvolatile memory element and the gate insulating film in the CMOS transistor as in the second embodiment. , (3) formation of sidewall spacers, (4) formation of source and drain regions in each of the nonvolatile memory element and the CMOS transistor, (5) formation of collector contact region and base contact region in the bipolar transistor, (6) contact The BiCMOS device 200 shown in FIG. 8 can be obtained by sequentially forming the plug and (7) forming the upper wiring.

  Even when the BiCMOS device 200 is manufactured in this manner, it is easy to form the nonvolatile memory element 140 having desired storage characteristics, erase characteristics, and write characteristics for the same reason as in the second embodiment. Also, the total number of masks used in the manufacturing process of the BiCMOS device 200 is reduced. Therefore, it becomes easy to obtain a BiCMOS device having desired characteristics at a low manufacturing cost. In addition, it becomes easy to manufacture the highly reliable nonvolatile memory element 140 and the CMOS transistor 60.

  Further, since the emitter region 23 is formed by doping arsenic (As) in the doping step, the impurity diffusion constant is smaller than that in the case of doping with phosphorus (P), and as a result, doping with phosphorus (P) is performed. Thus, the emitter region 23 can be made shallower than when the emitter region 23 is formed. As a result, the P-type impurity diffusion region 22 can also be made shallower. As a result, it is easy to increase the operation speed of the bipolar transistor 170 compared to the second embodiment.

Embodiment 4 FIG.
The fourth embodiment is an example of a BiCMOS device provided with a capacitive element in addition to a nonvolatile memory element, a CMOS transistor, and a bipolar transistor, and a method for manufacturing the BiCMOS device. The method for manufacturing the BiCMOS device is described in the first embodiment. As in the manufacturing method described above, the first electrode forming step, the laminated film forming step, and the second electrode forming step are included. After the second electrode formation process, a predetermined post-process is performed.

  FIG. 15 is a cross-sectional view schematically showing an example of a BiCMOS device also including a capacitive element. The BiCMOS device 300 shown in the figure includes a capacitive element 280 in addition to the nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70 shown in FIG. Of the constituent elements shown in FIG. 15, those common to the constituent elements shown in FIG. 23 are given the same reference numerals as those used in FIG. 23, and descriptions thereof are omitted.

  The semiconductor substrate 225 constituting the BiCMOS device 300 has an element region corresponding to the capacitive element 280 in addition to the element regions corresponding to the nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70. A P-type well 205 is formed in the element region. The element isolation film 24 covers an element region corresponding to the capacitor element 280.

  The capacitive element 280 is formed on the lower electrode 272 formed on the element isolation film 24, the insulating film 274 covering the lower electrode 272, the upper electrode 276 formed on the insulating film 274, and the upper electrode 276. And a protective film 278. The lower electrode 272 is formed from a polysilicon film (“first polysilicon film” in the first embodiment) from which the floating gate electrode 33 and the emitter electrode 62 are derived. The insulating film 274 is formed from a laminated film that is the base of the insulating film 35. The upper electrode 276 is formed from the conductive film that is the source of the control gate electrode 37, and the protective film 278 is formed from the film that is the source of the protective film 39.

  The interlayer insulating film 90 covers the corresponding capacitive element 280 in addition to the nonvolatile memory element 40, the CMOS transistor 60, and the bipolar transistor 70, and a plurality of contacts provided so as to penetrate through the interlayer insulating film 90. Plug 92 is connected to capacitive element 280. That is, two contact plugs 92 are connected to the lower electrode 272 of the capacitor 280, and three contact plugs 92 are connected to the upper electrode 276. A predetermined upper wiring 94 is also connected to each of the contact plugs 92 corresponding to the capacitive element 280.

  In such a BiCMOS device 300, in the first electrode formation step, the lower electrode 272 is also formed on the semiconductor substrate having the P-type well 205 in addition to the floating gate polysilicon film and the emitter electrode. In the laminated film forming step, the insulating film 274 is formed in addition to the floating gate laminated film, and in the second electrode forming step, the upper electrode 276 is formed in addition to the gate electrodes and the control gate electrodes. Except for this, it can be manufactured according to the manufacturing method (manufacturing method I) described in the first embodiment. Hereinafter, these steps will be described with reference to FIGS.

FIG. 16 is a cross-sectional view schematically showing an example of each electrode formed in the first electrode formation step. As shown in the figure, the first electrode forming step, in addition to the floating gate polysilicon film 33a and the emitter electrode 62, a lower electrode 272 of the capacitor element on the element regions R ₄ corresponding to the capacitive element. The element region R ₄ is formed a P-type well 205, the isolation layer 24 so as to cover the element region R ₄ are on the P-type well 205 is formed. The lower electrode 272 is formed on the element isolation film 24.

The P-type silicon substrate 2 has the element region R ₄ and the element isolation film 24 is formed so as to cover the element region R _{4. The} P-type silicon substrate shown in FIG. It has the same structure as the substrate 2. Since the P-type silicon substrate 2 is formed with the same electrical insulating film 31b as that in the semiconductor substrate with an insulating film 25C shown in FIG. 2-2, the P-type silicon substrate 2 having the element region R ₄ is formed on the P-type silicon substrate 2. The layer formed up to the electrical insulating film 31b is hereinafter referred to as “semiconductor substrate with insulating film 225C”, and is also denoted by reference numeral “225C” in FIG.

In order to form the lower electrode 272 described above, in the first electrode formation step, the first polysilicon film is formed so as to cover the element isolation film 24 on the element region R _{4 as} well. The first polysilicon film is formed in the same manner as in the first electrode forming step 1. Then, the first polysilicon film is patterned to form the lower electrode 272 described above in addition to the floating gate polysilicon film 33 a and the emitter electrode 62. 16 that are the same as those shown in FIG. 2B are given the same reference numerals as those used in FIG. 2B, and descriptions thereof are omitted. .

FIG. 17 is a cross-sectional view schematically showing an example of each of the floating gate laminated film and the capacitive element insulating film formed in the laminated film forming step. As shown in the figure, in the laminated film forming step, the laminated film 34 (see FIG. 4-1) that is the source of the insulating film 35 (see FIG. 15) is patterned to form the floating gate laminated film 35a and the capacitor element. An insulating film 274 is formed. The insulating film 274 is formed on the element region R ₄ so as to cover the upper surface and each side surface of the lower electrode 272. Therefore, in the laminated film forming step, the laminated film 34 is formed so as to cover the floating gate polysilicon film 33 a and the lower electrode 272.

  Similarly to the first embodiment, the emitter region 23 is formed on the semiconductor substrate 225C with an insulating film (see FIG. 16) prior to the laminated film forming step. The semiconductor substrate with an insulating film formed up to the emitter region 23 is hereinafter referred to as “semiconductor substrate with an insulating film 225D”, and is also denoted by reference numeral “225D” in FIG. 17 that are the same as those shown in FIG. 4B are given the same reference numerals as those shown in FIG. .

  FIG. 18 is a cross-sectional view schematically showing an example of each electrode formed in the second electrode formation step. As shown in the figure, in the second electrode formation step, a conductive film 37a (see FIG. 5-1) or the conductive film 37a and an inorganic insulating film 39a (see FIG. 5-1) stacked thereon are formed. By patterning, in addition to each control electrode 37 and each gate electrode 44, an upper electrode 276 of the capacitive element is also formed. When the inorganic insulating film 39 a is laminated on the conductive film 37 a, the protective film 39 is formed on each control electrode 37 and each gate electrode 44, and the protective film 278 is formed on the upper electrode 276.

Thus in the second electrode forming step, the electrical insulation on the element region R ₂ corresponding to the CMOS transistors film 31a (see FIG. 17) or the electrical insulating film 31a is removed newly deposited electrical insulating film 42a ( In addition to the floating gate laminated film 35a, the conductive film 37a is formed so as to cover the insulating film 274 as well. The same applies to the inorganic insulating film 39a. By forming up to the upper electrode 276, the capacitor element 280 is obtained. 18 that are the same as those shown in FIG. 5B are assigned the same reference numerals as those shown in FIG. 5B, and descriptions thereof are omitted. .

  After performing up to the second electrode forming step in this way, a predetermined post-process is performed in the same manner as in the first embodiment, whereby the BiCMOS device 300 shown in FIG. 15 can be obtained. The capacitance of the capacitive element 280 in the BiCMOS device 300 is substantially determined only by the dielectric constant of the insulating film 274 and has no voltage dependency. Therefore, it is easy to improve the performance of the capacitor 280.

Embodiment 5 FIG.
The fifth embodiment is another example of a BiCMOS device provided with a capacitive element in addition to a nonvolatile memory element, a CMOS transistor, and a bipolar transistor, and a method for manufacturing the BiCMOS device. As in the manufacturing method (manufacturing method II) described in Embodiment 2, the first polysilicon film forming step, the second polysilicon film forming step, the patterning step, the stacked film forming step, and the gate electrode forming step are included. . After the gate electrode forming process, a predetermined post process is performed.

  FIG. 19 is a cross-sectional view schematically showing another example of a BiCMOS device also including a capacitive element. The BiCMOS device 400 shown in the figure includes a capacitive element 380 in addition to the nonvolatile memory element 140, the CMOS transistor 60, and the bipolar transistor 170 shown in FIG. The semiconductor substrate constituting the BiCMOS device 400 is the same as the semiconductor substrate 225 in the BiCOM device 300 shown in FIG. Among the constituent elements shown in FIG. 19, the same constituent elements as those shown in FIG. 8 or FIG. 15 are denoted by the same reference numerals as those used in FIG. 8 or FIG. .

  The capacitive element 380 constituting the BiCMOS device 400 includes a lower electrode 372, an insulating film 374 covering the lower electrode 372, an upper electrode 376 disposed on the insulating film 374, and a protective film disposed on the upper electrode 376. 378, and the lower electrode 372 has a two-layer structure of a first lower electrode 372a and a second lower electrode 372b stacked thereon. As in the fourth embodiment, the semiconductor substrate 225 has an element region corresponding to the capacitor 380, and a P-type well 205 is formed in the element region. An element isolation film 24 is formed so as to cover the P-type well 205, and a lower electrode 372 is formed on the element isolation film 24 on the element region corresponding to the capacitor element 380.

  The first lower electrode 372a constituting the lower electrode 372 is formed of a polysilicon film that is the source of the first floating gate electrode 133a and the first emitter electrode 162a, and the second lower electrode 372b The two floating gate electrodes 133b and the second emitter electrode 162b are each formed from a polysilicon film. The insulating film 374 is formed from a laminated film that is the source of the insulating film 35, the upper electrode 376 is formed from the conductive film that is the source of the control gate electrode 37, and The protective film 378 is formed from an inorganic insulating film that is the basis of the protective film 39.

  As in the BiCMOS device 300 shown in FIG. 15, the capacitive element 380 is covered with an interlayer insulating film 90, and a plurality of contact plugs 92 provided so as to penetrate through the interlayer insulating film 90 include a capacitor. It is connected to the element 380. That is, the two contact plugs 92 are connected to the lower electrode 372 of the capacitor 380 and the three contact plugs 92 are connected to the upper electrode 376. A predetermined upper wiring 94 is connected to each contact plug 92.

  Such a BiCMOS device 400 can be manufactured according to the manufacturing method (manufacturing method II) described in the second embodiment. At this time, in the first polysilicon film forming step, the first polysilicon film 132a (see FIG. 9) is formed so as to cover the element isolation film 24 also on the element region corresponding to the capacitor element 380. In the second polysilicon film forming step, the second polysilicon film 132b (see FIG. 10) is formed so as to cover the first polysilicon film 132a also over the element region corresponding to the capacitor element 380. The patterning step, the laminated film forming step, and the gate electrode forming step will be described in detail below with reference to FIGS.

  FIG. 20 is a cross-sectional view schematically showing an example of each laminate formed in the patterning step. As shown in the drawing, in the patterning step, the first polysilicon film 132a and the second polysilicon film 132b are patterned together to form a floating gate polysilicon laminate 133A and an emitter electrode polysilicon laminate 162. In addition, a polysilicon laminate 372 for the lower electrode is formed. Since the first polysilicon film 132a and the second polysilicon film 132b are respectively doped with impurities, the emitter electrode polysilicon laminate 162 is used as it is in the emitter electrode (hereinafter referred to as "emitter") as in the second embodiment. The lower electrode polysilicon laminate 372 becomes the lower electrode (hereinafter referred to as “lower electrode 372”) as it is.

The lower electrode 372 has a two-layer structure of a first lower electrode 372a formed from the first polysilicon film 132a and a second lower electrode 372b formed from the second polysilicon film 132b. Is formed on the element region R ₄ corresponding to. The P-type silicon substrate 2 in which the element region R ₄ is formed has the element region R ₄ and the element isolation film 24 is formed so as to cover the element region R ₄ . It has the same structure as the P-type silicon substrate 2 shown. Since this P-type silicon substrate 2 is formed with the same electrical insulating film 131a as in the semiconductor substrate with an insulating film 25E shown in FIG. 11, the P-type silicon substrate 2 having the element region R ₄ is formed on the P-type silicon substrate 2. The layer formed up to the electrical insulating film 131a is hereinafter referred to as “semiconductor substrate with insulating film 225E” and is also denoted by reference numeral “225E” in FIG. Of the components shown in FIG. 20, those common to the components shown in FIG. 11 are given the same reference numerals as those used in FIG. 11 and description thereof is omitted.

FIG. 21 is a cross-sectional view schematically showing an example of each of the floating gate laminated film and the capacitor element insulating film formed in the laminated film forming step. As shown in the figure, in the laminated film forming step, the laminated film 34 (see FIG. 4-1) that is the source of the insulating film 35 (see FIG. 19) is patterned to form the floating gate laminated film 35a and the capacitor element. An insulating film 374 is formed. The insulating film 374 is formed on the element region R ₄ so as to cover the upper surface and each side surface of the lower electrode 372. Therefore, in the laminated film forming step, the laminated film 34 is formed so as to cover the floating gate polysilicon laminated body 133Aa and the lower electrode 372. As in the second embodiment, the emitter region 23 is formed in the semiconductor substrate 225E with an insulating film prior to the laminated film forming step. The semiconductor substrate with an insulating film formed up to the emitter region 23 is referred to as a “semiconductor substrate with an insulating film 225D”, and is also denoted by reference numeral “225D” in FIG.

  FIG. 22 is a cross-sectional view schematically showing an example of each of the electrodes formed in the gate electrode formation step. As shown in the figure, in the gate electrode formation step, the conductive film 37a (see FIG. 5-1) or the conductive film 37a and the inorganic insulating film 39a (see FIG. 5-1) stacked thereon are patterned. In addition to the control electrodes 37 and the gate electrodes 44, an upper electrode 376 of the capacitor 380 is also formed. When the inorganic insulating film 39a is laminated on the conductive film 37a, the protective film 39 is formed on each control electrode 37 and each gate electrode 44, and the protective film 378 is formed on the upper electrode 376.

  Therefore, in the gate electrode formation step, the electric insulating film 131a (see FIG. 20) on the element region corresponding to the CMOS transistor or the electric insulating film 42a newly formed by removing the electric insulating film 131a (see FIG. 22). In addition to the floating gate laminated film 35a, the conductive film 37a is formed so as to cover the insulating film 374. The same applies to the inorganic insulating film 39a. By forming the upper electrode 376 in this way, the capacitor element 380 is obtained. 22 that are the same as those shown in FIG. 5B are given the same reference numerals as those used in FIG. 5B, and descriptions thereof are omitted. .

  After performing the gate electrode forming step in this manner, the BiCMOS device 400 shown in FIG. 19 can be obtained by performing a predetermined post-process in the same manner as in the second embodiment. The capacitance of the capacitive element 380 constituting the BiCMOS device 400 is substantially determined only by the dielectric constant of the insulating film 374 and has no voltage dependency. Therefore, it is easy to improve the performance of the capacitor 380. The BiCMOS device 400 can also be manufactured according to the manufacturing method described in the third embodiment.

It is sectional drawing which shows roughly an example of the intermediate product obtained in the process of producing the semiconductor substrate with an insulating film in which the electrical insulating film was formed on the semiconductor substrate at the 1st electrode formation process in the manufacturing method I of this invention. . Sectional drawing which shows roughly the other example of the intermediate product obtained in the process of producing the semiconductor substrate with an insulating film in which the electrical insulating film was formed on the semiconductor substrate at the 1st electrode formation process in the manufacturing method I of this invention It is. It is sectional drawing which shows roughly an example of the semiconductor substrate with an insulating film obtained by forming an electrical insulating film on a semiconductor substrate at the 1st electrode formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the 1st polysilicon film formed in the 1st electrode formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of each of the polysilicon film for floating gates formed at the 1st electrode formation process in the manufacturing method I of this invention, and an emitter electrode. It is sectional drawing which shows roughly an example of the emitter area | region formed after the 1st electrode formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the laminated film used as the origin of the laminated film for floating gates formed at the laminated film formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the laminated film for floating gates formed at the laminated film formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the electrically conductive film formed by the 2nd electrode formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of each of the control gate electrode and gate electrode formed at the 2nd electrode formation process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the floating gate electrode formed by the post process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the ion implantation mask used when ion-implanting an acceptor after ion-implanting a donor to a semiconductor substrate in the post process in the manufacturing method I of this invention. It is sectional drawing which shows roughly an example of the semiconductor device (BiCMOS device) manufactured by the manufacturing method II of this invention. It is sectional drawing which shows roughly an example of the 1st polysilicon film formed by the 1st polysilicon film formation process in 1 aspect which concerns on the manufacturing method II of this invention. It is sectional drawing which shows roughly an example of the 2nd polysilicon film formed by the 2nd polysilicon film formation process in 1 aspect which concerns on the manufacturing method II of this invention. It is sectional drawing which shows roughly an example of each of the polysilicon laminated body for floating gates and the polysilicon laminated body for emitters formed at the patterning process in one mode concerning manufacturing method II of this invention. It is sectional drawing which shows roughly an example of the emitter area | region formed after the patterning process in 1 aspect which concerns on the manufacturing method II of this invention. It is sectional drawing which shows roughly the mode of the ion implantation of arsenic (As) performed at the doping process in the other aspect which concerns on the manufacturing method II of this invention. It is sectional drawing which shows roughly an example of each of the N type polysilicon film and emitter area | region formed at the doping process in the other aspect which concerns on the manufacturing method II of this invention. It is sectional drawing which shows roughly the other example of the semiconductor device (BiCMOS device) manufactured by the manufacturing method I of this invention. FIG. 16 is a cross sectional view schematically showing an example of each of the electrodes formed in the first electrode formation step when manufacturing the semiconductor device shown in FIG. 15 according to manufacturing method I. 16 is a cross-sectional view schematically showing an example of each of a floating gate laminated film and a capacitive element insulating film formed in a laminated film forming step when the semiconductor device shown in FIG. FIG. 16 is a cross sectional view schematically showing an example of each of the electrodes formed in the second electrode formation step when manufacturing the semiconductor device shown in FIG. 15 according to manufacturing method I. It is sectional drawing which shows roughly the other example of the semiconductor device (BiCMOS device) manufactured by the manufacturing method II of this invention. FIG. 20 is a cross sectional view schematically showing an example of each stacked body formed in a patterning step when manufacturing the semiconductor device shown in FIG. 19 according to manufacturing method II. FIG. 20 is a cross-sectional view schematically showing an example of each of a floating gate stacked film and a capacitor element insulating film formed in a second patterning step when the semiconductor device shown in FIG. 19 is manufactured according to Manufacturing Method II. FIG. 20 is a cross sectional view schematically showing an example of each of the electrodes formed in the gate electrode forming step when manufacturing the semiconductor device shown in FIG. 19 according to manufacturing method II. It is sectional drawing which shows schematically the semiconductor device (BiCMOS apparatus) which is an example of the conventional semiconductor device and is also an example of the semiconductor device which can be manufactured with the manufacturing method I of this invention.

Explanation of symbols

23 Emitter region 24 Element isolation film 25,225 Semiconductor substrate 31 Tunnel oxide film 31b Large electrical insulating film 32 First polysilicon film 33 Floating gate electrode 33a Floating gate polysilicon film 34 Large laminated film 35 Insulating film 35a Layered film for floating gate 37 Control gate electrode 37a Large conductive film 40 Nonvolatile memory 44 Gate electrode 50 P-channel MOS transistor 55 N-channel MOS transistor 60 CMOS transistor 62 Emitter electrode 70 Bipolar transistors 100, 200, 300, 400 Semiconductor device (BiCMOS device)
132a first polysilicon film 132b second polysilicon film 132U ₁ first polysilicon film 132U ₂ not doped with impurities second polysilicon film 133A not doped with impurities 133A floating gate polysilicon stack 162 emitter poly Silicon laminate (emitter electrode having a two-layer structure)
280, 380 Capacitor element 272 Capacitor element lower electrode 274, 374 Capacitor element insulating film 276, 376 Capacitor element upper electrode 372 Lower electrode R ₁ , R ₂ , R ₃ , R ₄ element region having a two-layer structure

Claims (8)

A semiconductor substrate, a non-volatile memory element having a plurality of memory cells, a field effect transistor having at least one gate electrode, and a bipolar transistor having an emitter electrode, each of the memory cells being formed on the semiconductor substrate An insulating film and a control gate electrode are stacked in this order on a floating gate electrode formed via a tunnel oxide film, and the gate electrode is formed on the semiconductor substrate via a gate insulating film. A method of manufacturing a semiconductor device, wherein the emitter electrode is disposed in contact with the semiconductor substrate,
A semiconductor substrate in which element regions are formed corresponding to each of the nonvolatile memory element, the field effect transistor, and the bipolar transistor, and an element isolation film having a predetermined pattern that locally exposes each of the element regions An electrical insulating film is formed on the region corresponding to the region where the emitter electrode and the semiconductor substrate are in contact with each other, leaving an opening, and covering the exposed surface of each of the device regions, and at least the nonvolatile memory device After forming the first polysilicon film so as to cover the element isolation film and the electric insulating film formed in each of the element region corresponding to the bipolar transistor and the region corresponding to the bipolar transistor and to fill the opening, The first polysilicon film is patterned so that the first polysilicon film is formed on the element region corresponding to the nonvolatile memory element. The former become floating gate polysilicon film of the floating gate electrode in each of a plurality of memory cells formed, said the device on a region corresponding to the bipolar transistor and the first electrode forming step of forming the emitter electrode,
A laminated film forming step of forming a floating gate laminated film serving as an insulating film in each of the plurality of memory cells so as to cover the floating gate polysilicon film;
A conductive film is formed to cover the electrical insulating film on the element region corresponding to the field effect transistor and the laminated film for the floating gate, and the conductive film is patterned to form the gate electrode and the control gate electrode. A second electrode forming step;
A method for manufacturing a semiconductor device, comprising: The semiconductor substrate further includes an element region corresponding to a capacitive element having a structure in which an insulating film and an upper electrode are stacked in this order on a lower electrode, and the nonvolatile memory element, the field effect transistor, and the bipolar An element isolation film having a predetermined pattern covering the element region corresponding to the capacitive element while locally exposing each element region corresponding to each transistor;
Corresponding to each of the nonvolatile memory element, the field effect transistor, and the bipolar transistor while leaving an opening in a region corresponding to a region where the emitter electrode and the semiconductor substrate are in contact with each other in the first electrode forming step. Forming an electrical insulating film covering the exposed surface of the element region to be formed on the semiconductor substrate, and further, an element region corresponding to at least the nonvolatile memory element, an element region corresponding to the bipolar transistor, and an element corresponding to the capacitor element Covering the element isolation film formed in each region, and at least the element region corresponding to the nonvolatile memory element and the electric insulating film formed in each element region corresponding to the bipolar transistor, and the opening After forming the first polysilicon film so as to fill First polysilicon film is patterned to further form the lower electrode in addition to said emitter electrode and the floating gate polysilicon film,
In the laminated film forming step, in addition to the floating gate laminated film, an insulating film having the same layer configuration as the floating gate laminated film is further formed on the lower electrode,
In the second electrode forming step, the conductive film is formed so as to cover the insulating film in addition to the element region corresponding to the field effect transistor and the laminated film for the floating gate, and then the conductive film is formed. The method of manufacturing a semiconductor device according to claim 1, wherein the upper electrode is further formed in addition to the gate electrode and the control gate electrode by patterning. A semiconductor substrate, a non-volatile memory element having a plurality of memory cells, a field effect transistor having at least one gate electrode, and a bipolar transistor having an emitter electrode, each of the memory cells being formed on the semiconductor substrate An insulating film and a control gate electrode are stacked in this order on a floating gate electrode formed via a tunnel oxide film, and the gate electrode is formed on the semiconductor substrate via a gate insulating film. A method of manufacturing a semiconductor device, wherein the emitter electrode is disposed in contact with the semiconductor substrate,
A semiconductor substrate in which element regions are formed corresponding to each of the nonvolatile memory element, the field effect transistor, and the bipolar transistor, and an element isolation film having a predetermined pattern that locally exposes each of the element regions An electrical insulating film covering the exposed surface of each of the element regions is formed thereon, and further, the element isolation film formed at least in each of the element region corresponding to the nonvolatile memory element and the region corresponding to the bipolar transistor And a first polysilicon film forming step of forming a first polysilicon film so as to cover the electrical insulating film;
After the first polysilicon film is removed by removing the region located on the region where the emitter electrode and the semiconductor substrate are in contact with each other and the electrical insulating film below the region, the opening is formed. A second polysilicon film forming step of forming a second polysilicon film so as to cover the polysilicon film and fill the opening;
The first polysilicon film and the second polysilicon film are patterned together to form a floating gate serving as a source of a floating gate electrode in each of the plurality of memory cells on an element region corresponding to the nonvolatile memory element. A patterning step of forming a polysilicon laminate, and forming an emitter polysilicon laminate at a position where the emitter electrode is formed;
A laminated film forming step of forming a floating gate laminated film serving as an insulating film in each of the plurality of memory cells so as to cover the floating gate polysilicon laminated body;
A conductive film is formed to cover the electrical insulating film on the element region corresponding to the field effect transistor and the laminated film for the floating gate, and the conductive film is patterned to form the gate electrode and the control gate electrode. A gate electrode forming step;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein each of the first polysilicon film and the second polysilicon film is made of polysilicon doped with impurities. Each of the first polysilicon film and the second polysilicon film is made of polysilicon not doped with impurities,
Before performing the patterning step, the first polysilicon film and the second polysilicon film are doped with arsenic (As), and the first polysilicon film and the second polysilicon film are formed into an N-type polysilicon film. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a doping step of forming an emitter region in an element region corresponding to the bipolar transistor. The semiconductor substrate further includes an element region corresponding to a capacitive element having a structure in which an insulating film and an upper electrode are stacked in this order on a lower electrode, and the nonvolatile memory element, the field effect transistor, and the bipolar An element isolation film having a predetermined pattern covering the element region corresponding to the capacitive element while locally exposing each element region corresponding to each transistor;
In the first polysilicon film forming step, the first polysilicon film is formed so as to cover the element isolation film also on the element region corresponding to the capacitive element,
In the second polysilicon film forming step, the second polysilicon film is formed so as to cover the first polysilicon film also on the element region corresponding to the capacitive element,
In the patterning step, the first polysilicon film and the second polysilicon film are patterned together, and in addition to the floating gate polysilicon laminate and the emitter polysilicon laminate, the lower electrode polysilicon is formed. Further forming a laminate,
In the laminated film forming step, in addition to the floating gate laminated film, an insulating film having the same layer configuration as the floating gate laminated film is formed on the lower electrode,
In the gate electrode formation step, the conductive film is formed so as to cover the insulating film in addition to the element region corresponding to the field effect transistor and the laminated film for the floating gate, and then the conductive film is patterned. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the upper electrode is further formed in addition to the gate electrode and the control gate electrode. A semiconductor substrate, a non-volatile memory element having a plurality of memory cells, a field effect transistor having at least one gate electrode, and a bipolar transistor having an emitter electrode, each of the memory cells being formed on the semiconductor substrate A semiconductor in which an insulating film and a control gate electrode are stacked in this order on a floating gate electrode formed through a tunnel oxide film, and the emitter electrode is disposed in contact with the semiconductor substrate A device,
The semiconductor device, wherein each of the floating gate electrode and the emitter electrode has a two-layer structure.   2. A capacitor element having a structure in which an insulating film and an upper electrode are stacked in this order on a lower electrode having a two-layer structure formed on the semiconductor substrate via an element isolation film. 8. The semiconductor device according to 7.

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