JP2013004791A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology of achieving high integration of a nonvolatile semiconductor device.SOLUTION: A semiconductor manufacturing method comprises: forming a semiconductor region functioning as a source/drain region SDH of a switch nMIS (Qs) and concurrently functioning as a drain region D of a memory nMIS (Qm), between a switch gate electrode SG of the switch nMIS (Qs) and a memory gate electrode MG of the memory nMIS (Qm), which is adjacent to the switch nMIS (Qs) in a direction crossing a word line; and forming a shape of the semiconductor region composing the source/drain region SDH of the switch nMIS (Qs) on the memory nMIS (Qm) side and a shape of the semiconductor region composing the source/drain region SDL of the switch nMIS (Qs) on the opposite side (bit line side) to the memory nMIS (Qm) to be asymmetry.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a nonvolatile semiconductor device having a MONOS (Metal Oxide Nitride Oxide Silicon) type nonvolatile memory cell and a technique effective when applied to the manufacturing thereof.

  For example, Japanese Patent Laying-Open No. 2009-245958 (Patent Document 1) discloses a MONOS-type NAND nonvolatile semiconductor memory device using an aluminum oxide film as a block insulating film, and a selection transistor adjacent to a memory cell transistor. In this source / drain region, a manufacturing method is described in which the impurity concentration of the source / drain region on the memory cell transistor side is higher than the impurity concentration of the other source / drain region.

  Japanese Patent Laying-Open No. 2002-233182 (Patent Document 2) discloses a NAND-type nonvolatile semiconductor memory device in which the shape of the source / drain diffusion layer region of the selection transistor is asymmetric, and is adjacent to the memory cell transistor. In the source / drain region of the select transistor, the impurity concentration of the source / drain region on the memory cell transistor side is higher than the impurity concentration of the other source / drain region.

JP 2009-245958 A JP 2002-231832 A

  Nonvolatile memories that can electrically write and erase data can be rewritten, for example, on a wiring board, and are easy to use. Widely used.

  In particular, electrical batch erasable EEPROM (Electric Erasable Programmable Real Only Memory: hereinafter referred to as “flash memory”) collects data in a certain range (all memory cells or a predetermined group of memory cells) of the memory array. And has a function to electrically erase. Further, since the flash memory has a one-transistor stacked gate structure, the size of the cell has been reduced, and there is a great expectation for higher integration.

  In the one-transistor stacked gate structure, one memory cell is basically composed of one two-layer gate field effect transistor. The two-layer gate field effect transistor is formed by providing a floating gate on a semiconductor substrate via a tunnel insulating film, and further stacking a control gate thereon via an interlayer film. Data is stored by injecting electrons into the floating gate or extracting electrons from the floating gate.

  A non-volatile semiconductor device studied by the present inventor before the present invention is applied will be described with reference to FIGS. 24 to 28 show a part of a memory array constituting a nonvolatile semiconductor device (a plurality of memory transistors connected in parallel and a switch provided at an end of the plurality of memory transistors on the bit line side. FIG. 29 is a fragmentary cross-sectional view of a partial region of a memory array for explaining an example of processing defects occurring in the process of manufacturing a nonvolatile semiconductor device. FIG. 30 is a memory constituting the nonvolatile semiconductor device. It is a principal part top view of the partial area | region of an array. Note that the cross sections shown in FIGS. 24 to 29 correspond to the cross section along the line BB ′ shown in FIG. 30.

  A method for manufacturing a nonvolatile semiconductor device before the present invention is applied will be described with reference to FIGS.

  First, as shown in FIG. 24, for example, a trench-type element isolation portion STI and an active region arranged so as to be surrounded by the trench-type element isolation portion are formed on the main surface of the semiconductor substrate 51. Subsequently, a p-type impurity is selectively ion-implanted into the semiconductor substrate 51 to form a p-well 52, and then a tunnel insulating film 53 made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 51. Subsequently, a first conductive film 54 made of low-resistance polycrystalline silicon is deposited on the main surface of the semiconductor substrate 51.

  Next, as shown in FIG. 25, the first conductive film 54 and the tunnel insulating film 53 are sequentially processed by dry etching using the resist pattern 55 as a mask, and the first conductive film 54 and the tunnel insulating film are formed in the memory transistor region. The film 53 is left. Thereafter, the resist pattern 55 is removed.

  Next, as illustrated in FIG. 26, an insulating film 56 b made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 51. The thickness of the insulating film 56b is 4 nm, for example. Subsequently, an insulating film 56 c made of silicon nitride and an insulating film 56 t made of silicon oxide are sequentially formed on the main surface of the semiconductor substrate 51. Subsequently, a second conductive film 57 made of, for example, low-resistance polycrystalline silicon and a cap insulating film 58 made of, for example, silicon oxide are formed on the main surface of the semiconductor substrate 51.

  Next, as shown in FIG. 27, the cap insulating film 58, the second conductive film 57, and the insulating films 56t, 56c, and 56b are sequentially processed by dry etching using the resist pattern 59 as a mask. As a result, the control gate electrode CG made of the second conductive film 57 of the memory transistor and the interlayer film 56M made of the insulating films 56t, 56c, and 56b are formed in the memory transistor region. At the same time, a switch gate electrode SG made of the second conductive film 57 of the switch transistor and a gate insulating film 56S made of the insulating films 56t, 56c, and 56b are formed in the switch transistor region. Thereafter, the resist pattern 59 is removed.

  Next, as shown in FIG. 28, the switch transistor region is covered with a resist pattern 60, and the first conductive film 54 is processed by dry etching using the resist pattern 60 as a mask. Thus, the floating gate electrode FG made of the first conductive film 54 of the memory transistor is formed in the memory transistor region. Here, the switch transistor region is covered with a resist pattern 60 in order to prevent the active region of the switch transistor region from being removed. Thereafter, the resist pattern 60 is removed. As a result, a two-layer gate composed of a control gate electrode CG and a floating gate electrode FG of a plurality of memory transistors is formed in the memory transistor region, and a switch gate electrode SG of the switch transistor is formed in the switch transistor region It is formed.

  Meanwhile, an element isolation portion STI is formed at the boundary between the switching transistor region and the memory transistor region. If the first conductive film 54 is processed so that the element isolation portion STI is not formed in the boundary portion and the first conductive film 54 is not left in the boundary portion, for example, as shown in FIG. A part of the substrate 51 (p-well 52) is shaved to form a step 61. When the step 61 is formed, there arises a problem that conductivity of a source region, a drain region, or a silicide layer formed in a later process is hindered. Therefore, in order to avoid such a problem, as shown in FIG. 28 described above, an element isolation portion STI is formed at the boundary portion, and an end portion of the first conductive film 54 is formed on the element isolation portion STI. Further, the second conductive film 57 covers the end portion of the first conductive film 54.

  However, the element isolation portion STI formed at the boundary between the switching transistor region and the memory transistor region is not a part necessary for the operation of the nonvolatile memory cell, and becomes an obstacle to the high integration of the nonvolatile semiconductor device. ing.

  For example, as shown in FIG. 30, when the layout is viewed in the direction crossing the channel region of the memory transistor with respect to the word line (the x direction shown in FIG. 30), the memory transistor region has 2 A space S2 between the layer gates (the control gate electrode CG and the floating gate electrode FG) can be 2F (F (minimum feature size)). On the other hand, at the boundary between the switch transistor region and the memory transistor region, the two-layer gate (control gate electrode CG and floating gate electrode FG) of the memory transistor located at the end of the memory array and the switch gate of the switch transistor 6F (F: minimum processing dimension) is required as the space S3 between the electrodes SG. This is for considering the alignment margin of the element isolation part STI and the connection hole.

  An object of the present invention is to provide a technique capable of achieving high integration of a nonvolatile semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  This embodiment is a semiconductor device having a plurality of memory transistors connected in parallel on the main surface of a semiconductor substrate and a switching transistor provided at an end of the plurality of memory transistors on the bit line side. The semiconductor substrate between the switch gate electrode of the switch transistor and the memory gate electrode of the memory transistor adjacent to the switch transistor functions as one source / drain region of the switch transistor, and at the same time for the memory A semiconductor region functioning as a drain region of the transistor is formed, the shape of the semiconductor region constituting one source / drain region on the memory transistor side of the switching transistor, and the opposite side of the switching transistor to the memory transistor ( The other source / drain on the bit line side) The shape of the semiconductor region constituting the emission region are asymmetrical.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  By reducing the area of the boundary portion between the switching transistor region and the memory transistor region, high integration of the nonvolatile semiconductor device can be achieved.

An arrangement of a plurality of memory transistors connected in parallel constituting the memory array of the nonvolatile semiconductor device according to the first embodiment of the present invention, and an arrangement of switching transistors provided at the ends of the plurality of memory transistors FIG. Main parts of a plurality of memory transistors and switch transistors corresponding to a cross section taken along the line AA ′ in FIG. 1 (a line obtained by cutting the channel region of the memory transistor along the direction intersecting the word line). It is sectional drawing. A partial region of a memory array constituting a nonvolatile semiconductor device during the manufacturing process of the nonvolatile semiconductor device according to Embodiment 1 of the present invention (a plurality of memory transistors connected in parallel and ends of the plurality of memory transistors) It is principal part sectional drawing of the transistor for a switch provided in the part. A partial region of a memory array constituting a nonvolatile semiconductor device during the manufacturing process of the nonvolatile semiconductor device according to Embodiment 1 of the present invention (a plurality of memory transistors connected in parallel and ends of the plurality of memory transistors) FIG. 3 is a plan view of a main part of a switching transistor provided in the part. FIG. 5 is a fragmentary cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 3 and FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 5; FIG. 7 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 6; FIG. 7 is a plan view of main parts of the same portions as those in FIG. 4 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 6; FIG. 9 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 7 and FIG. 8; FIG. 10 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 9; FIG. 11 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 10; FIG. 11 is a plan view of main parts of the same portions as those in FIG. 4 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 10; FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 11 and FIG. 12; FIG. 14 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 13; FIG. 15 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 14; FIG. 16 is a principal part cross-sectional view of the same place as in FIG. 3 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 15; FIG. 17 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 16; FIG. 18 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 17; FIG. 19 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 18; FIG. 19 is an essential part plan view of the same place as in FIG. 4 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 18; FIG. 21 is an essential part cross-sectional view of the same place as that in FIG. 3 during the manufacturing process of the nonvolatile semiconductor device, following FIGS. 19 and 20; FIG. 21 is a plan view of main parts of the same portions as those in FIG. 4 during the manufacturing process of the nonvolatile semiconductor device, following FIGS. 19 and 20; A plurality of memory transistors connected in parallel constituting a memory array of a nonvolatile semiconductor device according to Embodiment 2 of the present invention, and a switch transistor provided at an end of the plurality of memory transistors FIG. 4 is a partial cross-sectional view showing a cross section of a channel region of a memory transistor cut along a direction intersecting a word line. A partial region of a memory array constituting a nonvolatile semiconductor device during a manufacturing process of the nonvolatile semiconductor device before the present invention is applied (a plurality of memory transistors connected in parallel and ends of the plurality of memory transistors) It is principal part sectional drawing of the transistor for a switch provided in the part. FIG. 25 is an essential part cross-sectional view of the same place as that in FIG. 24 during the manufacturing process of the nonvolatile semiconductor device, following FIG. 24; FIG. 26 is a principal part cross-sectional view of the same place as in FIG. 24 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 25; FIG. 27 is a principal part cross-sectional view of the same place as in FIG. 24 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 26; FIG. 28 is a principal part cross-sectional view of the same place as in FIG. 24 in the process of manufacturing the nonvolatile semiconductor device, following FIG. 27; It is principal part sectional drawing of the one part area | region of a memory array explaining an example of the processing defect which arises in the manufacture process of the non-volatile semiconductor device before this invention is applied. A partial region of a memory array constituting a nonvolatile semiconductor device before the present invention is applied (a plurality of memory transistors connected in parallel and a switch transistor provided at an end of the plurality of memory transistors) FIG.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. It shall refer to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, and an n-channel type MISFET is abbreviated as nMIS. An n-channel memory transistor is referred to as a memory nMIS, and an n-channel switch transistor is referred to as a switching nMIS.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The structure of the nonvolatile semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an arrangement of a plurality of memory nMISs connected in parallel that constitute a memory array of a nonvolatile semiconductor device, and a switch nMIS provided at an end portion (end portion on the bit line side) of the plurality of memory nMISs. FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1 (a line obtained by cutting the channel region of the memory nMIS along the direction intersecting the word line). It is principal part sectional drawing of the corresponding nMIS for memory and nMIS for switches.

  In FIG. 1, only the memory nMIS (Qm) and two switch nMISs (Qs) for 4 bits (the area surrounded by the dotted line in FIG. 1 is 1 bit (one unit)) are shown. It is not limited. In the first embodiment of the present invention, the configuration of the switching nMIS (Qs) connected to the bit line side of the memory nMIS (Qm) will be described unless otherwise specified. Therefore, FIG. 1 shows only the planar layout of the switch nMIS (Qs) provided at the end of the plurality of memory nMISs (Qm) on the bit line side. The planar layout of the switch nMIS provided at the end of the nMIS is substantially the same as that shown in FIG.

As shown in FIGS. 1 and 2, a plurality of memory nMISs (Qm) are arranged in the active region ACT surrounded by the element isolation portion STI on the main surface (device formation surface) of the semiconductor substrate 1. The source region S and drain region D of this memory nMIS (Qm) have a so-called LDD (Lightly Doped Drain) structure, and each has a relatively low concentration n ⁻ type semiconductor region 10 and its n ⁻ type semiconductor. The n ⁺ type semiconductor region 13 having a relatively higher impurity concentration than the region 10 and a relatively high concentration is formed. The n ⁻ -type semiconductor region 10 is arranged on the channel region side of the memory nMIS (Qm), and the n ⁺ -type semiconductor region 13 is the n ⁻ -type semiconductor region 10 from the channel region side of the memory nMIS (Qm). It is located at a distance. The depth of the n ⁻ type semiconductor region 10 from the main surface of the semiconductor substrate 1 is, for example, 0.1 μm.

  On the main surface of the semiconductor substrate 1 between the source region S and the drain region D, the memory gate electrode MG of the memory nMIS (Qm) extends in the second direction (y direction in FIG. 1; the word line extends). A plurality of memory nMISs (Qm) are adjacent to each other via the element isolation part STI along the second direction (y direction). The gate length of the memory gate electrode MG is, for example, 0.1 μm.

  Also, a plurality of memory nMISs (Qm) are arranged along a first direction (x direction in FIG. 1; a direction perpendicular to the direction in which the word lines extend) orthogonal to the second direction (y direction). However, the adjacent memory nMIS (Qm) shares the source region S or the drain region D. Accordingly, in the memory nMIS (Qm) adjacent in the first direction (x direction), the memory gate electrode MG of each memory nMIS (Qm) is disposed with the drain region D or the source region S interposed therebetween. .

Further, a switching nMIS (Qs) is arranged at the bit line side end of the plurality of memory nMISs (Qm) arranged along the first direction (x direction). The source / drain regions SDH and SDL of the switch nMIS (Qs) have a so-called LDD structure. Further, the source / drain region SDH on the memory nMIS (Qm) side has a relatively low concentration n ⁻ type semiconductor region 10 and a relatively high impurity concentration higher than that of the n ⁻ type semiconductor region 10. is composed of a concentration of n ⁺ -type semiconductor region 13. the source / drain regions SDL memory for nMIS (Qm) and the opposite side (bit line side) is relatively low concentration of n ^- -type semiconductor regions 9 and a relatively high-concentration n ⁺ -type semiconductor region 13 having a higher impurity concentration than that of the n ⁻ -type semiconductor region 9. The depth of the n ⁻ type semiconductor region 9 from the main surface of the semiconductor substrate 1 is, for example, 0.2 μm. That is, the shape of the source / drain region SDH on the memory nMIS (Qm) side and the shape of the source / drain region SDL on the opposite side (bit line side) to the memory nMIS (Qm) are asymmetric.

  On the main surface of the semiconductor substrate 1 between the source / drain region SDH and the source / drain region SDL, the switch gate electrode SG of the switching nMIS (Qs) is in the second direction (y direction in FIG. 1). A plurality of switch nMISs (Qs) are adjacent to each other through the element isolation portion STI along the second direction (y direction). The gate length of the switch gate electrode SG is, for example, 0.4 μm.

Further, the element isolation portion STI is not formed at the boundary portion along the first direction (x direction) between the memory nMIS region and the switch nMIS region. At this boundary, the semiconductor region (n ⁻ type semiconductor region 10 and n ⁺ type) functions as the drain region D of the memory nMIS (Qm) and simultaneously functions as the source / drain region SDH of the switching nMIS (Qs). The semiconductor region 13) is formed on the main surface of the semiconductor substrate 1.

  Note that, similarly to the bit line side, switching nMISs are also arranged at the source line side ends of the plurality of memory nMISs (Qm) arranged along the first direction (x direction). However, the source / drain regions of the switch nMIS on the source line side may have the same configuration (asymmetric shape) as the source / drain regions SDH and SDL of the switch nMIS on the bit line side, or for memory A configuration (symmetric shape) similar to that of the source region S or the drain region D of nMIS (Qm) may be used.

  The memory gate electrode MG of the memory nMIS (Qm) is formed of a conductive film made of, for example, n-type low-resistance polycrystalline silicon. Between the semiconductor substrate 1 and the memory gate electrode MG, a gate insulation composed of a laminated film of an insulating film 4b, a charge storage layer CSL, and an insulating film 5t (hereinafter referred to as insulating films 4b and 5t and a charge storage layer CSL). A film (first gate insulating film) is provided. The charge storage layer CSL is made of, for example, silicon nitride and has a thickness of, for example, 15 nm. The insulating films 4b and 5t are made of, for example, silicon oxide. The insulating film 4b has a thickness of, for example, 1.5 nm, and the insulating film 5t has a thickness of, for example, 2.5 nm or more. The insulating films 4b and 5t can be formed of silicon oxide containing nitrogen. For example, arsenic is introduced into the main surface of the semiconductor substrate 1 (p well PW) under the gate insulating film composed of the insulating films 4b and 5t and the charge storage layer CSL to form an n-type semiconductor region 3n. The semiconductor region 3n is a semiconductor region for forming a channel of the memory nMIS (Qm), and the threshold voltage of the memory nMIS (Qm) is set to a predetermined value by the semiconductor region 3n.

  The switch gate electrode SG of the switch nMIS (Qs) is formed of a conductive film made of, for example, n-type low-resistance polycrystalline silicon. A gate insulating film 5 (second gate insulating film) is provided between the semiconductor substrate 1 and the switch gate electrode SG. The gate insulating film 5 is made of, for example, silicon oxide, and the thickness thereof is, for example, 20 nm. On the main surface of the semiconductor substrate 1 (p well PW) under the gate insulating film 5, for example, boron is introduced to form a p-type semiconductor region 3p. The semiconductor region 3p is a semiconductor region for forming a channel of the switching nMIS (Qs), and the threshold voltage of the switching nMIS (Qs) is set to a predetermined value by the semiconductor region 3p.

Sidewalls 12 made of, for example, silicon oxide are formed on both side surfaces of the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs). A silicide layer 14 such as nickel silicide (NiSi), cobalt silicide (CoSi ₂ ), or the like is formed on the upper surface of the memory gate electrode MG and the upper surface of the switch gate electrode SG. By forming the silicide layer 14, the resistance of the memory gate electrode MG and the switch gate electrode SG can be reduced. The silicide layer 14 includes the surface of the n ⁺ -type semiconductor region 13 constituting part of the source region S and the drain region D of the memory nMIS (Qm), and the source / drain regions SDH, nDH (Qs) of the switch. It is also formed on the surface of the n ⁺ type semiconductor region 13 constituting a part of the SDL.

Further, the plurality of memory nMISs (Qm) and the switch nMISs (Qs) are covered with an interlayer insulating film 15. The interlayer insulating film 15 is made of a laminated film in which, for example, the lower layer is silicon nitride and the upper layer is silicon oxide. The interlayer insulating film 15 includes a silicide layer 14 formed on the surface of the n ⁺ -type semiconductor region 13 constituting a part of the source region S and the drain region D of the memory nMIS (Qm), and the switch nMIS (Qs ) Of the source / drain regions SDH and SDL, and connection holes CNT reaching the silicide layers 14 formed on the surface of the n ⁺ -type semiconductor region 13 are formed.

  A plug 16 is embedded in the connection hole CNT, and the first layer wiring M1 is connected to the source region S or drain region D of the memory nMIS (Qm) and the switch nMIS (Qs) via the plug 16. ) Source / drain regions SDH and SDL. The plug 16 is, for example, a barrier film made of a relatively thin conductive film made of a laminated film of titanium and titanium nitride, etc., and a relatively thick conductive made of tungsten, aluminum, or the like formed so as to be surrounded by the barrier film. It is comprised by the laminated film which consists of a film | membrane. The wiring M1 is made of a metal film made of tungsten or aluminum, for example.

Thus, at the boundary between the memory nMIS region and the switch nMIS region, it functions as the drain region D of the memory nMIS (Qm) and at the same time functions as the source / drain region SDH of the switch nMIS (Qs). Semiconductor regions (n ⁻ type semiconductor region 10 and n ⁺ type semiconductor region 13) are formed. Accordingly, the space S1 between the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs) adjacent to each other along the first direction (x direction) via the boundary portion is Thus, a space can be formed in which the connection hole CNT connected to the semiconductor region (the n ⁻ type semiconductor region 10 and the n ⁺ type semiconductor region 13) can be formed. For example, when the minimum processing dimension is F, the space S1 can be set to 2F even if an alignment margin is taken into consideration. Since the space S2 between the memory gate electrodes MG of the memory nMIS (Qm) adjacent in the first direction (x direction) formed in the memory nMIS region can also be 2F, the first direction (x direction) ) Along the space S1 between the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs) adjacent to each other along the first direction (x The space S2 between the memory gate electrodes MG of the memory nMISs (Qm) adjacent to each other along the (direction) can be the same (2F).

  For example, when the element isolation portion STI is provided at the boundary portion between the memory nMIS region and the switch nMIS region described with reference to FIG. 30 described above, the first portion (x direction) passes through this boundary portion. A space S3 between the memory gate electrode MG of the adjacent memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs) is 6F. Accordingly, the boundary portion according to the first embodiment is shorter than the boundary portion having the element isolation portion STI by 8F (4F × 2) along the first direction (x direction) when the source side is also combined. Further, when the cell size of 1 bit (area surrounded by a dotted line in FIG. 1) of the memory nMIS (Qm) according to the first embodiment is configured to be, for example, 5F × 3F, the cell size is converted to 2.7. There is a reduction effect of cells.

By the way, in the first embodiment, it functions as the drain region D of the memory nMIS (Qm) at the boundary between the memory nMIS region and the switch nMIS region, and at the same time, the source / drain of the switch nMIS (Qs). Semiconductor regions (n ⁻ type semiconductor region 10 and n ⁺ type semiconductor region 13) functioning as region SDH are formed. This semiconductor region needs to be set to an impurity distribution necessary for the operating characteristics of the memory nMIS (Qm). However, the impurity distribution of the source / drain region SDL on the opposite side (bit line side) of the memory nMIS (Qm) of the switch nMIS (Qs) is the impurity distribution of the source / drain region SDH of the memory nMIS (Qm). If the same, if a high external voltage is applied to the source / drain region SDL on the opposite side (bit line side) of the memory nMIS (Qm) of the switch nMIS (Qs), there is a risk that defects such as junction leakage may occur. There is.

Therefore, in the switching nMIS (Qs), the shape of the semiconductor region constituting the source / drain region SDH on the memory nMIS (Qm) side, and the source / drain on the side opposite to the memory nMIS (Qm) (bit line side) The shape of the semiconductor region constituting the region SDL is asymmetric. Specifically, the shape (impurity concentration and depth from the main surface of the semiconductor substrate 1) of the n ⁻ type semiconductor region 10 constituting a part of the source / drain region SDH on the memory nMIS (Qm) side, Shape of n ⁻ -type semiconductor region 9 constituting a part of source / drain region SDL on the opposite side (bit line side) to memory nMIS (Qm) (impurity concentration and depth from main surface of semiconductor substrate 1) Are formed on the main surface of the semiconductor substrate 1 on both sides of the switch gate electrode SG, so that the n ⁻ type semiconductor region 9 and the n ⁻ type semiconductor region 10 are formed.

That is, the depth from the main surface of the semiconductor substrate 1 of the n ⁻ type semiconductor region 9 constituting a part of the source / drain region SDL on the opposite side (bit line side) to the memory nMIS (Qm) is, for example, 0 The depth of the n ⁻ -type semiconductor region 10 constituting a part of the source / drain region SDH on the memory nMIS (Qm) side from the main surface of the semiconductor substrate 1 is set to 0.1 μm, for example. It is formed so as to be deeper from the main surface of the semiconductor substrate 1 than in the latter. Further, the impurity concentration of the n ⁻ -type semiconductor region 9 constituting a part of the source / drain region SDL on the opposite side (bit line side) to the memory nMIS (Qm) is determined based on the source / drain on the memory nMIS (Qm) side. The n ⁻ type semiconductor region 10 constituting a part of the drain region SDH is formed to have a lower impurity concentration. Therefore, the n ⁻ type semiconductor region 9 constituting a part of the source / drain region SDL on the opposite side (bit line side) to the memory nMIS (Qm) is located on the memory nMIS (Qm) side. / Drain region SDH is formed deeper and lower in concentration from the main surface of semiconductor substrate 1 than n ⁻ type semiconductor region 10 constituting a part of drain region SDH.

As a result, in the memory nMIS (Qm) adjacent to the boundary between the memory nMIS region and the switch nMIS region, the n ⁻ type semiconductor region 10 having the impurity distribution necessary for its operating characteristics and the n ⁺ type semiconductor region 10 A drain region D composed of the semiconductor region 13 can be provided. On the other hand, in the switching nMIS (Qs), the n ⁻ type semiconductor region 9 having an impurity distribution lower in concentration than the n ⁻ type semiconductor region 10 and the n ⁺ type semiconductor region 10 on the opposite side (bit line side) to the memory nMIS. Since the source / drain region SDL composed of the semiconductor region 13 can be provided, even if a high external voltage is applied to the source / drain region SDL, junction leakage can be suppressed and the breakdown voltage can be maintained. .

  A method of manufacturing the nonvolatile semiconductor device according to the first embodiment of the present invention will be described in the order of steps with reference to FIGS. 3, 5 to 7, 9 to 11, 13 to 19, and 21 are cross-sectional views of main parts of the memory nMIS region and the switch nMIS region on the bit line side (the same as FIG. 2 described above). 4, FIG. 8, FIG. 12, FIG. 20, and FIG. 22 are plan views of relevant parts of the memory nMIS region and the switch nMIS region on the bit line side (as shown in FIG. 1 and FIG. 1). It is a principal part top view of the same area | region.

  First, as shown in FIG. 3 and FIG. 4, for example, a groove type is formed on the main surface of a semiconductor substrate 1 made of, for example, p-type single crystal silicon (planar substantially circular semiconductor thin plate called a semiconductor wafer at this stage) 1. An element isolation part STI and an active region ACT arranged so as to be surrounded by the element isolation part STI are formed. That is, after an isolation groove is formed at a predetermined location of the semiconductor substrate 1, an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate 1, and the insulating film is left only in the isolation groove. By polishing the insulating film by a CMP (Chemical Mechanical Polishing) method or the like, the insulating film is embedded in the isolation trench. In this way, the element isolation portion STI is formed.

Next, by subjecting the semiconductor substrate 1 to oxidation treatment, an insulating film 2 made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 1. The thickness of the insulating film 2 is 20 nm, for example. Subsequently, a p-type impurity is selectively ion-implanted into the semiconductor substrate 1 to form a p-well PW. The ion implantation concentration of the p-type impurity is, for example, 5 × 10 ¹² to 1 × 10 ¹³ cm ⁻² .

  Next, the switch nMIS region is covered with a resist pattern RP1, and an n-type impurity such as arsenic is selectively ion-implanted into the semiconductor substrate 1 in the memory nMIS region. Thus, an n-type semiconductor region 3n for forming a channel of the memory nMIS (Qm) is formed on the semiconductor substrate 1 in the memory nMIS region. Thereafter, the resist pattern RP1 is removed. Similarly, the memory nMIS region is covered with a resist pattern, and a p-type impurity such as boron is selectively ion-implanted into the semiconductor substrate 1 in the switch nMIS region. As a result, the n-type semiconductor region 3p for forming the channel of the switch nMIS (Qs) is formed in the semiconductor substrate 1 of the switch nMIS region.

  Next, as shown in FIG. 5, after removing the insulating film 2 in the memory nMIS region, the semiconductor substrate 1 is subjected to a heat treatment to activate n-type impurities implanted into the semiconductor substrate 1.

  Next, as shown in FIG. 6, an insulating film 4 b made of, for example, silicon oxide is formed on the main surface of the semiconductor substrate 1 in the memory nMIS region. The insulating film 4b is formed by, for example, a thermal oxidation method or an ISSG (In-Site Steam Generation) oxidation method, and the thickness thereof is, for example, 1.5 nm. Subsequently, a charge storage layer CSL made of silicon nitride and an insulating film 4t made of silicon oxide are sequentially formed on the main surface of the semiconductor substrate 1. The charge storage layer CSL is formed by a CVD (Chemical Vapor Deposition) method, and its thickness is, for example, 15 nm. The insulating film 4t is formed by, for example, the CVD method or the ISSG oxidation method, and the thickness thereof is, for example, 2 nm. The insulating films 4b and 4t may be formed of silicon oxide containing nitrogen.

  Next, as shown in FIGS. 7 and 8, the memory nMIS region is covered with a resist pattern RP2, the insulating film 4t in the switch nMIS region is removed by hydrofluoric acid (wet etching), and the switch nMIS region The charge storage layer CSL is exposed. Thereafter, the resist pattern RP2 is removed.

  Next, as shown in FIG. 9, after the charge storage layer CSL in the switching nMIS region is removed by hot phosphoric acid (wet etching), the insulating film 2 in the switching nMIS region and the insulating film 4t in the memory nMIS region are further removed. Is removed by hydrofluoric acid (wet etching). Subsequently, after cleaning the surfaces of the charge storage layer CSL (memory nMIS region) and the semiconductor substrate 1 (switch nMIS region), the semiconductor substrate 1 is oxidized. For this oxidation treatment, for example, a method of performing ISSG oxidation after performing wet oxidation or a method of performing wet oxidation after performing ISSG oxidation can be used.

  Thus, the insulating film 5t is formed on the charge storage layer CSL in the memory nMIS region, and the insulating film 5 is formed on the main surface of the semiconductor substrate 1 in the switch nMIS region. The insulating films 5t and 5 are made of, for example, silicon oxide, and the thickness of the insulating film 5t formed on the charge storage layer CSL is, for example, 2.5 nm or more, and the insulating film formed on the main surface of the semiconductor substrate 1 is used. The thickness of the film 5 is, for example, 20 nm. In the memory nMIS region, the insulating films 4b and 5t and the charge storage layer CSL become the gate insulating film (first gate insulating film) of the memory nMIS (Qm), and in the switching nMIS region, the insulating film 5 is the switching nMIS (Qs). Gate insulating film (second gate insulating film).

Next, as shown in FIG. 10, a conductive film 6 made of low-resistance polycrystalline silicon and an insulating film 7 made of silicon oxide are sequentially deposited on the main surface of the semiconductor substrate 1. The conductive film 6 is formed by a CVD method and has a thickness of, for example, 200 nm. The insulating film 7 is formed by a plasma CVD method using TEOS (tetraethyl orthosilicate: Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as source gases, and the thickness thereof is, for example, 20 nm. is there.

  Next, as shown in FIGS. 11 and 12, the insulating film 7 is processed using the conductive film 6 as an etching stopper film by dry etching using the resist pattern as a mask, and then the resist pattern is removed and processed. The conductive film 6 and the insulating films 5t and 5 are processed by dry etching using the insulating film 7 as a mask, using the electric field storage layer CSL as an etching stopper film. Thus, the memory gate electrode MG of the memory nMIS (Qm) made of the conductive film 6 is formed in the memory nMIS region, and the switch gate electrode SG of the switch nMIS (Qs) made of the conductive film 6 is formed in the switch nMIS region. Form. The gate length of the memory gate electrode MG of the memory nMIS (Qm) is, for example, 0.1 μm, and the switch gate electrode SG of the switch nMIS (Qs) is, for example, 0.4 μm.

  Thus, the memory gate electrode MG of the memory nMIS (Qm) is composed of one layer of the conductive film 6. Therefore, for example, as described with reference to FIG. 29 and the like described above, a memory including the floating gate electrode FG (first conductive film 54) and the control gate electrode CG (second conductive film 57) through the interlayer film 56M. In the case of the gate, an element isolation portion is required at the boundary between the memory nMIS region and the switch nMIS region when the first conductive film 54 is processed. In the first embodiment, this element isolation portion is used. Is no longer necessary.

  Next, as shown in FIG. 13, oxidation is performed on the side walls of the conductive film 6 constituting the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs) by performing an oxidation process. Film 8

  Next, as shown in FIG. 14, the exposed charge storage layer CSL is removed by hot phosphoric acid. Since the side walls of the conductive film 6 constituting the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs) are protected by the oxide film 8, the exposed charge storage layer CSL Only is removed by hot phosphoric acid. Subsequently, the insulating film 4b exposed in the memory nMIS region is removed with hydrofluoric acid. At this time, a part of the insulating film 5 exposed in the switch nMIS region is removed by hydrofluoric acid and becomes thin.

Next, as shown in FIG. 15, a part of the switch gate electrode SG on the memory nMIS (Qm) side and the memory gate electrode are positioned at the upper surface of the switch gate electrode SG of the switch nMIS (Qs). After forming the photoresist pattern RP3 covering the MG, the main surface of the semiconductor substrate 1 is ion-implanted into the main surface of the semiconductor substrate 1 by using the switch gate electrode SG and the photoresist pattern RP3 as a mask to implant n-type impurities, for example, phosphorus. The n ⁻ type semiconductor region 9 is formed in a self-aligned manner with respect to the switch gate electrode SG. The implantation energy of the n-type impurity (phosphorus) is, for example, 70 keV, and the implantation amount is, for example, 1 × 10 ¹³ cm ⁻² . Thereafter, the photoresist pattern RP3 is removed.

Next, as shown in FIG. 16, the end portion of the switch gate electrode SG is located on the upper surface of the switch gate electrode SG of the switch nMIS (Qs) and is opposite to the memory nMIS (Qm) (bit line side). After forming a photoresist pattern RP4 covering a part of the substrate, n-type impurities such as arsenic are ion-implanted into the main surface of the semiconductor substrate 1 using the switch gate electrode SG, the memory gate electrode MG, and the photoresist pattern RP4 as a mask. Thus, an n ⁻ type semiconductor region 10 is formed on the main surface of the semiconductor substrate 1 in a self-aligned manner with respect to the switch gate electrode SG and the memory gate electrode MG. The implantation energy of the n-type impurity (arsenic) is, for example, 10 keV, and the implantation amount is, for example, 5 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . Thereafter, the photoresist pattern RP4 is removed.

Here, the n ⁻ type semiconductor region 9 is formed first, and then the n ⁻ type semiconductor region 10 is formed. However, the n ⁻ type semiconductor region 10 is formed first, and then the n ⁻ type semiconductor region 9 is formed. May be formed. Further, following the ion implantation of the n-type impurity forming the n ⁻ -type semiconductor region 10, a p-type impurity such as boron is ion-implanted into the main surface of the semiconductor substrate 1, and the lower portion of the n ⁻ -type semiconductor region 10 is formed. A p-type semiconductor region may be formed so as to surround it. The implantation amount of this p-type impurity (boron) is, for example, 1 × 10 ¹³ cm ⁻² .

15 and FIG. 16, in the switching nMIS (Qs), the n ⁻ type semiconductor region 10 is formed on the memory nMIS (Qm) side, and the memory nMIS (Qm) An n ⁻ type semiconductor region 9 is formed on the opposite side (bit line side), and the main surface of the semiconductor substrate 1 on both sides of the switch gate electrode SG of the switch nMIS (Qs) has a shape (impurity concentration and semiconductor). N ⁻ type semiconductor regions 9 and 10 having different depths from the main surface of the substrate 1 are formed.

In the switch nMIS (Qs) shown in FIG. 16 described above, only the n ⁻ type semiconductor region 10 is formed at the boundary between the memory nMIS region on the memory nMIS (Qm) side and the switch nMIS region. However, the present invention is not limited to this.

For example, as shown in FIG. 17, n it is formed at the boundary between the memory for nMIS region and the switching TFT nMIS region ^- in type semiconductor region, in the memory for nMIS (Qm) side adjacent to the boundary n ^- type The n ⁻ -type semiconductor region 9 having a lower concentration than the n ⁻ -type semiconductor region 10 can be formed on the switch nMIS (Qs) side. Even with such a configuration, the memory nMIS (Qm) has the n ⁻ type semiconductor region 10 having an impurity distribution required for its operating characteristics.

  Next, as shown in FIG. 18, an insulating film made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate 1 by a CVD method, and then the insulating film is etched back by anisotropic dry etching. Thus, the sidewalls 12 are formed on both side surfaces of the memory gate electrode MG of the memory nMIS (Qm) and on both side surfaces of the switch gate electrode SG of the switch nMIS (Qs).

Next, n-type impurities, for example, arsenic and phosphorus are ion-implanted into the main surface of the semiconductor substrate 1 so that the n ⁺ -type semiconductor region 13 is formed on the main surface of the semiconductor substrate 1 in the memory region by the switch gate electrode SG and the memory gate. It is formed in a self-aligned manner with respect to the electrode MG. Thus, in the memory nMIS region, the source region S and the drain region D composed of the n ⁻ type semiconductor region 10 and the n ⁺ type semiconductor region 13 of the memory nMIS (Qm) are formed. In the switching nMIS region, a source / drain region SDH including the n ⁻ type semiconductor region 10 and the n ⁺ type semiconductor region 13 of the switching nMIS (Qs) is formed on the memory nMIS (Qm) side. On the opposite side (bit line side) to the memory nMIS (Qm), a source / drain region SDL composed of the n ⁻ type semiconductor region 9 and the n ⁺ type semiconductor region 13 of the switch nMIS (Qs) is formed. The

  Next, after removing the insulating film 7 on the memory gate electrode MG of the memory nMIS (Qm) and the switch gate electrode SG of the switch nMIS (Qs), the upper surface of the memory gate electrode MG of the memory nMIS (Qm) The silicide layer 14 is formed on the surface of the source region S and the drain region D, the upper surface of the switch gate electrode SG of the switching nMIS (Qs), and the surfaces of the source / drain regions SDH and SDL. The silicide layer 14 is formed by, for example, a salicide (Self align silicide) process. For the silicide layer 14, for example, nickel silicide or cobalt silicide is used.

  By forming the silicide layer 14, the connection resistance between the silicide layer 14 and a plug or the like formed on the silicide layer 14 can be reduced. Further, the resistances of the memory gate electrode MG, the source region S and the drain region D of the memory nMIS (Qm), and the switch gate electrode SG and the source / drain regions SDH, SDL of the switch nMIS (Qs) can be reduced. .

  Next, as shown in FIGS. 19 and 20, a first insulating film made of, for example, silicon nitride is deposited on the main surface of the semiconductor substrate 1 by a CVD method. This first insulating film functions as an etching stopper when a connection hole described later is formed. Subsequently, a second insulating film made of, for example, silicon oxide is deposited by a CVD method to form an interlayer insulating film 15 made of the first insulating film and the second insulating film. Subsequently, the surface of the interlayer insulating film 15 is polished and planarized by, for example, a CMP method.

  Next, the silicide layer 14 on the source region S and the silicide layer 14 on the drain region D of the memory nMIS (Qm) and the silicide layer 14 on the source / drain regions SDH and SDL of the switch nMIS (Qs) are reached. Connection holes CNT are formed in the interlayer insulating film 15. Subsequently, the plug 16 is formed inside the connection hole CNT. The plug 16 includes, for example, a barrier film made of a relatively thin conductive film made of a laminated film of titanium and titanium nitride, and a relatively thick conductive film made of tungsten, aluminum, or the like formed so as to be surrounded by the barrier film. It is comprised by the laminated film which consists of. Thereafter, a first layer wiring M1 containing, for example, tungsten or aluminum as a main component is formed on the interlayer insulating film 15.

  Next, as shown in FIGS. 21 and 22, an interlayer insulating film 17 made of, for example, silicon oxide is deposited on the main surface of the semiconductor substrate 1 by a CVD method. Subsequently, a connection hole TH reaching the first layer wiring M <b> 1 is formed in the interlayer insulating film 17. Subsequently, the plug 18 is formed in the connection light TH in the same manner as the plug 16 described above. Thereafter, a second-layer wiring M2 containing, for example, tungsten or aluminum as a main component is formed on the interlayer insulating film 17.

  Thereafter, an upper layer wiring is formed on the main surface of the semiconductor substrate 1 above the second layer wiring M2, and a surface protective film is further formed. Then, a part of the uppermost layer wiring is exposed at a part thereof. A non-volatile semiconductor device is manufactured by forming a bonding hole by forming a simple opening.

  Thus, according to the first embodiment, the boundary between the memory nMIS region and the switch nMIS region in the first direction (x direction) orthogonal to the second direction (y direction) in which the word line extends. In the section, the space S1 between the memory gate electrode MG and the switch gate electrode SG of the memory nMIS (Qm) is, for example, 2F (minimum) as the space S2 between the memory gate electrodes MG of the adjacent memory nMIS (Qm). Therefore, the area of the memory array can be reduced, and the high integration of the nonvolatile semiconductor device can be achieved.

Further, at the boundary between the memory nMIS region and the switch nMIS region, a semiconductor region that functions as the drain region D of the memory nMIS (Qm) and simultaneously functions as the source / drain region SDH of the switch nMIS (Qs). This semiconductor region is composed of an n ⁻ type semiconductor region 10 and an n ⁺ type semiconductor region 13 having an impurity distribution required for the operating characteristics of the memory nMIS (Qm). Therefore, desired operation characteristics of the memory nMIS (Qm) can be obtained. On the other hand, on the opposite side (bit line side) of the memory nMIS (Qm) of the switch nMIS (Qs), an n ⁻ type semiconductor region 9 having an impurity distribution lower in concentration than the n ⁻ type semiconductor region 10. By forming the source / drain region SDL composed of the n ⁺ type semiconductor region 13, the breakdown voltage of the source / drain region SDL can be maintained.

(Embodiment 2)
The structure of the nonvolatile semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 23 shows a plurality of memory nMISs connected in parallel constituting a memory array of a nonvolatile semiconductor device, and a switch nMIS provided at an end (end on the bit line side) of the plurality of memory nMISs. It is principal part sectional drawing to demonstrate, and has shown the cross section along the line | wire cut | disconnected along the direction which cross | intersects the channel area | region of nMIS for memory to a word line.

  The nonvolatile semiconductor device according to the second embodiment of the present invention is the same as that of the first embodiment described above, and has a boundary between the memory nMIS region and the switch nMIS region along the direction intersecting the word line. Although it is constituted only by the semiconductor region, the structure of the well region is different from that of the first embodiment.

  That is, in the first embodiment described above, the plurality of memory nMISs (Qm) and the switch nMISs (Qs) are formed in the region of the p-well PW formed in the semiconductor substrate 1, and the switch nMISs (Qs). The shape of the semiconductor region constituting the source / drain region SDH on the memory nMIS (Qm) side and the shape of the semiconductor region constituting the source / drain region SDL on the opposite side (bit line side) from the memory nMIS (Qm) Is asymmetric.

On the other hand, in the second embodiment of the present invention, the plurality of memory nMISs (Qm) are formed in the region of the first p well HPW, and the switch nMIS has a lower impurity concentration than the first p well HPW. It is formed in the well LPW region. The impurity concentration of the first p well HPW in which the plurality of memory nMISs (Qm) are formed is, for example, 1 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻³ , and the switch nMISs (Qs) are formed. The impurity concentration of the second p well LPW is, for example, 5 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻³ .

  As described above, according to the second embodiment, by increasing the impurity concentration of the first p well HPW in which the plurality of memory nMISs (Qm) are formed, in addition to the effect of the first embodiment described above, The operating characteristics of the memory nMIS can be further improved.

In the second embodiment of the present invention, the case where only the n ⁻ type semiconductor region 10 is formed in the n ⁻ type semiconductor region at the boundary between the memory nMIS region and the switch nMIS region is exemplified. As described above with reference to FIG. 17, in the n ⁻ type semiconductor region formed at the boundary between the memory nMIS region and the switch nMIS region, the memory nMIS (Qm) side adjacent to the boundary The n ⁻ type semiconductor region 10 may be formed on the switching nMIS (Qs) side, and the n ⁻ type semiconductor region 9 having a lower concentration than the n ⁻ type semiconductor region 10 may be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a nonvolatile semiconductor device including MONOS type nonvolatile memory cells.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3n, 3p Semiconductor region 4b, 4t, 5, 5t Insulating film 6 Conductive film 7 Insulating film 8 Oxide film 9, 10 Semiconductor region 12 Side wall 13 Semiconductor region 14 Silicide layer 15 Interlayer insulating film 16 Plug 17 Interlayer insulating film 18 Plug 51 Semiconductor substrate 52 P well 53 Tunnel insulating film 54 First conductive film 55 Resist pattern 56b, 56c, 56t Insulating film 56M Interlayer film 56S Gate insulating film 57 Second conductive film 58 Cap insulating film 59, 60 Resist Pattern 61 Step ACT Active region CG Control gate electrode CNT Connection hole CSL Charge storage layer D Drain region FG Floating gate electrode HPW First p well LPW Second p well M1, M2 Wiring MG Memory gate electrode PW p well Qm Memory transistor Qs For switch Transistors RP1, R P2, RP3, RP4 resist pattern S source region S1, S2, S3 space SDH source / drain region (first source / drain region)
SDL source / drain region (second source / drain region)
SG Switch gate electrode STI Element isolation part TH Connection hole

Claims (15)

A semiconductor device comprising: a plurality of memory transistors connected in parallel on a main surface of a semiconductor substrate; and a switching transistor provided at an end of the plurality of memory transistors on the bit line side,
Between the first memory gate electrode of the first memory transistor adjacent to the switch transistor and the switch gate electrode of the switch transistor along the direction intersecting the word line, the memory transistor And a first semiconductor region that functions as a first source / drain region of the switching transistor at the same time,
The shape of the first semiconductor region constituting the first source / drain region on the memory transistor side of the switching transistor, and the second source / drain region on the opposite side of the switching transistor from the memory transistor. A semiconductor device characterized in that the shape of a second semiconductor region to be formed is asymmetric. The semiconductor device according to claim 1,
The space between the first memory gate electrode of the first memory transistor adjacent to the switch transistor and the switch gate electrode of the switch transistor is twice the minimum processing size. Semiconductor device. The semiconductor device according to claim 1,
The shape of the first semiconductor region formed between the first memory gate electrode of the first memory transistor adjacent to the switch transistor and the switch gate electrode of the switch transistor is: A semiconductor device having the same shape as a third semiconductor region constituting a source region of a memory transistor. The semiconductor device according to claim 3.
The semiconductor device, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the second semiconductor region. The semiconductor device according to claim 3.
A depth of the first semiconductor region from the main surface of the semiconductor substrate is smaller than a depth of the second semiconductor region from the main surface of the semiconductor substrate. The semiconductor device according to claim 1,
The first semiconductor region formed between the first memory gate electrode of the first memory transistor adjacent to the switch transistor and the switch gate electrode of the switch transistor is the first memory region. A first portion formed on the transistor side, and a second portion formed on the switch transistor side,
The impurity concentration of the first portion is higher than the impurity concentration of the second portion, and the depth of the first portion from the main surface of the semiconductor substrate is different from the main surface of the semiconductor substrate of the second portion. A semiconductor device characterized by being shallower than the depth. The semiconductor device according to claim 6.
The impurity concentration of the first portion is the same as the impurity concentration of the third semiconductor region constituting the source region of the first memory transistor, and the impurity concentration of the second portion is the same as that of the switch transistor. A semiconductor device, wherein the impurity concentration of the second semiconductor region constituting the second source / drain region opposite to the memory transistor is the same. The semiconductor device according to claim 6.
The depth of the first portion from the main surface of the semiconductor substrate is the same as the depth of the third semiconductor region constituting the source region of the first memory transistor from the main surface of the semiconductor substrate, The depth of the second portion from the main surface of the semiconductor substrate is such that the second semiconductor region of the second semiconductor region constituting the second source / drain region opposite to the memory transistor of the switching transistor A semiconductor device having the same depth as the main surface.   2. The semiconductor device according to claim 1, wherein the plurality of memory transistors and the switching transistor are formed in the same well region formed in the semiconductor substrate.   2. The semiconductor device according to claim 1, wherein the plurality of memory transistors are formed in a region of a first well formed in the semiconductor substrate, and the switching transistor is formed in a second well formed in the semiconductor substrate. A semiconductor device formed in a region, wherein the impurity concentration of the first well is higher than the impurity concentration of the second well. The semiconductor device according to claim 1,
An element isolation portion is not formed between the first memory gate electrode of the first memory transistor adjacent to the switch transistor and the switch gate electrode of the switch transistor. . A method of manufacturing a semiconductor device, comprising: forming a plurality of memory transistors connected in parallel on a main surface of a semiconductor substrate; and a switching transistor provided at an end of the plurality of memory transistors on a bit line side. ,
(A) forming a well in a first region of the main surface of the semiconductor substrate in which the plurality of memory transistors are formed and a second region in which the switch transistor is formed;
(B) forming a first insulating film on the main surface of the semiconductor substrate in the second region;
(C) sequentially depositing a second insulating film, a charge storage layer, and a third insulating film on the main surface of the semiconductor substrate;
(D) The third insulating film in the first region is removed, and the third insulating film, the charge storage layer, the second insulating film, and the first insulating film in the second region are sequentially removed. Process,
(E) After the step (d), the semiconductor substrate is thermally oxidized to form a fourth insulating film on the charge storage layer in the first region, and the second region in the second region. Forming a fifth insulating film on the main surface of the semiconductor substrate, and forming a first gate comprising the second insulating film, the charge storage layer, and the fourth insulating film on the main surface of the semiconductor substrate in the first region; Forming an insulating film and forming a second gate insulating film made of the fifth insulating film on a main surface of the semiconductor substrate in the second region;
(F) After the step (e), sequentially forming a conductive film and a sixth insulating film on the main surface of the semiconductor substrate;
(G) sequentially processing the sixth insulating film and the conductive film to form a plurality of memory gate electrodes of the plurality of memory transistors in the first region, and to switch the switch transistor in the second region; Forming a gate electrode;
(H) The first impurity is ion-implanted into the main surface of the semiconductor substrate in the first region and the main surface of the semiconductor substrate in the second region and on the side of the plurality of memory transistors of the switch gate electrode. A first low-concentration semiconductor region is formed, and a second impurity is ion-implanted into a main surface of the semiconductor substrate in the second region and opposite to the plurality of memory transistors in the switch gate electrode. Forming a semiconductor region;
(I) forming a sidewall on each of the sidewalls of the plurality of memory gate electrodes and the sidewall of the switch gate electrode;
(J) forming a high-concentration semiconductor region by ion-implanting a third impurity into the main surface of the semiconductor substrate in the first region and the second region;
Including
A method of manufacturing a semiconductor device, wherein an ion implantation amount of the first impurity in the step (h) is larger than an ion implantation amount of the second impurity. In the manufacturing method of the semiconductor device according to claim 12,
In the step (d), the third insulating film, the charge storage layer, the second insulating film, and the first insulating film are removed by wet etching. In the manufacturing method of the semiconductor device according to claim 12,
In the step (a), the well includes a first well formed on the semiconductor substrate in the first region and a second well formed on a main surface of the semiconductor substrate in the second region, A method of manufacturing a semiconductor device, wherein the impurity concentration of the first well is higher than the impurity concentration of the second well. In the manufacturing method of the semiconductor device according to claim 12,
After the step (j),
(K) forming a silicide layer on the upper surface of the memory gate electrode, the upper surface of the switch gate electrode, and the surface of the high-concentration semiconductor region after removing the sixth insulating film;
A method for manufacturing a semiconductor device, further comprising:

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