KR20020056395A - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR20020056395A KR20020056395A KR1020000085747A KR20000085747A KR20020056395A KR 20020056395 A KR20020056395 A KR 20020056395A KR 1020000085747 A KR1020000085747 A KR 1020000085747A KR 20000085747 A KR20000085747 A KR 20000085747A KR 20020056395 A KR20020056395 A KR 20020056395A
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- region
- field oxide
- gate electrode
- predetermined
- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title description 12
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000010410 layer Substances 0.000 claims abstract description 23
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 23
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 6
- 239000000470 constituent Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 실리사이드를 형성하기전에 소정의 공정을 이용하여 필드산화막과 액티브영역간의 경계면에 생성된 틈을 질화막을 이용하여 매립함으로써, 액티브영역의 종단부에서 반도체 기판의 노출을 방지하여 실리사이드의 측면 퍼짐을 방지할 수 있는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, before forming silicide, a gap formed in the interface between the field oxide film and the active region is filled with a nitride film using a nitride film, using a predetermined process, thereby forming a semiconductor at the end of the active region. It relates to a method for manufacturing a semiconductor device that can prevent the exposure of the substrate to prevent the side spread of the silicide.
반도체 소자의 고집적화 추세에 따라 소자의 임계 면적은 작이지고 있으며, 실리콘을 이용한 반도체 소자에서 미세 선 폭을 만드는 노광 공정은 광학 노광 장비상 이미 한계에 도달해 있다. 또한 설계 규칙이 낮아짐에 따라 공정 여유도 역시 낮아져 오 배열 및 오 정렬의 문제점을 가지고 있다.With the trend toward higher integration of semiconductor devices, the critical area of the devices is becoming smaller, and the exposure process for making fine line widths in semiconductor devices using silicon has already reached its limit in optical exposure equipment. In addition, as design rules are lowered, process margins are also lowered, which leads to problems of misalignment and misalignment.
최근, 로직 소자의 공정중 소자 분리공정은 STI(Shallow Trench Isolation)공정을 채용하고 게이트 전극 및 액티브영역의 저항을 낮추기 위해서 Ti 또는 Co를 이용한 자기정합 실리사이드(SALICIDE)를 사용하고 있으며, 소자의 면적을 축소 시키기 위해 콘택의 노광 정시 오 배열에 관한 여유도(mis-align margin)를 설정하지 않는 무 경계 콘택(Borderless Contact : 이하 "BLC"라 함)의 설계 규칙(design rule)을 채용하고 있다.Recently, the device isolation process of the logic device employs a shallow trench isolation (STI) process, and uses self-aligned silicide (SALICIDE) using Ti or Co to reduce the resistance of the gate electrode and the active region. The design rule of borderless contact (hereinafter referred to as "BLC") that does not set a mis-align margin for the exposure exposure misalignment of the contact is adopted to reduce the size of the contact.
도 1에 도시된 바와 같이, BLC 소자의 면적 축소에 따라 각 층간의 정렬에 관한 여유도 (margin)를 영(0)으로 설정하고 오 배열일 경우에도 정상적으로 소자를 동작 시키기 위한 것으로써, 게이트전극과 층간절연막 사이에 질화막(Nitride)을 증착하여 식각방지막으로 사용되는 구조를 말한다.As shown in FIG. 1, the margin of alignment between layers is set to zero as the area of the BLC device is reduced, and the device is normally operated even when the array is misaligned. It is a structure used as an etch stop layer by depositing a nitride (Nitride) between the insulating film and the interlayer insulating film.
또한, STI공정을 형성하는 경우 필드산화막이 게이트산화막 전세정, 식각 후, 세정 등의 공정에서 식각이 되어서 액티브영역의 끝 부분이 노출되게 되는데 이는 살리사이드를 형성할 때, 측면 살리사이드 퍼짐(Salicide diffusion) 으로 인해 액티브영역에서의 누설전류가 증가하게 된다.In addition, when forming the STI process, the field oxide film is etched in a process such as pre-cleaning, etching, and cleaning the gate oxide film so that the end portion of the active region is exposed. When forming the salicide, the side salicide spreads (Salicide). diffusion) increases the leakage current in the active region.
또한, 상기 언급된 자기 정합 실리사이드 및 BLC의 두 가지 공정을 동시에 채용할 경우, 그 공정 순서는 살리사이드 공정 후, BLC에 사용될 질화막을 증착해야 하는데, 이 경우 증착 공정시 가해지는 높은 온도(예를 들면, 600∼800℃)의해 실리사이드의 응고 현상(agglomeration)으로 인해 결국 실리사이드의 단선 현상이 발생한다. 현재까지는 낮은 온도로 질화막을 증착 하는 것 외에는 이에 관한 특별한 해결책이 없으며, 저온 질화막 증착은 장비 개발이 이루어지지 않아서 양산 단계에서 소자의 수명과 수율에 악 영향을 끼칠 것으로 예상 된다.In addition, in the case of employing the two processes of self-aligned silicide and BLC mentioned above at the same time, the process sequence must deposit a nitride film to be used for the BLC after the salicide process, in which case the high temperature (e.g., For example, due to the agglomeration of silicide (600-800 ° C.), the disconnection of silicide occurs. Until now, there is no special solution except for the deposition of nitride film at low temperature, and low temperature nitride deposition is expected to adversely affect the lifetime and yield of the device in the mass production stage due to the lack of equipment development.
따라서, 본 발명의 목적은 소정의 반도체 소자를 제조하기 위한 공정중 이용되는 BLC 형성공정시 발생되는 실리사이드의 측면 퍼짐 및 단선 현상을 방지하기 위한 반도체 소자의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device for preventing side spreading and disconnection of silicide generated during the BLC forming process used in the process of manufacturing a predetermined semiconductor device.
본 발명의 또 다른 목적은 실리사이드를 형성하기전에 소정의 공정을 이용하여 필드산화막과 액티브영역간의 경계면에 생성된 틈을 질화막을 이용하여 매립함으로써, 액티브영역의 종단부에서 반도체 기판의 노출을 방지하여 실리사이드의 측면 퍼짐을 방지할 수 있는 반도체 소자의 제조 방법을 제공함에 있다.It is still another object of the present invention to fill a gap formed in the interface between the field oxide film and the active region using a nitride film before forming silicide, thereby preventing exposure of the semiconductor substrate at the end of the active region. It is to provide a method for manufacturing a semiconductor device that can prevent the side spread of the silicide.
도 1은 종래 기술에 따른 반도체 소자의 제조 방법에 의해 실리사이드 퍼짐을 도시한 SEM 사진.1 is a SEM photograph showing the silicide spread by the method of manufacturing a semiconductor device according to the prior art.
도 2(a) 내지 도 2(f)는 본 발명의 일 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도.2 (a) to 2 (f) are cross-sectional views of semiconductor devices sequentially shown to explain a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 3은 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 반도체 소자의 단면도.3 is a cross-sectional view of a semiconductor device for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 반도체 소자의 SEM 사진.4 is a SEM photograph of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1,21 : 반도체 기판 2,22 : 필드산화막1,21 semiconductor substrate 2,22 field oxide film
3,23 : 게이트산화막 4,24 : 다결정실리콘3,23 gate oxide film 4,24 polysilicon
5,25 : 게이트전극 6,27 : 스페이서5,25 gate electrode 6,27 spacer
7 : 저농도 접합영역 8 : 고농도 접합영역7: low concentration junction area 8: high concentration junction area
9,28 : 매립층 10 : 실리사이드9,28: buried layer 10: silicide
11 : 층간절연막 12 : 콘택홀11 interlayer insulating film 12 contact hole
본 발명은 소정의 반도체 기판내에 액티브영역과 필드영역을 분리하기 위한 필드산화막을 형성하는 단계와; 상기 액티브영역에 대응되는 영역에 게이트전극을 형성하는 단계와; 상기 게이트전극을 마스크로 하여 상기 반도체 기판의 소정 부위에 이온을 주입하여 접합영역을 형성하는 단계와; 상기 필드산화막을 식각한 후, 상기 필드산화막과 접합영역의 접촉부위를 덮도록 매립층을 형성하는 단계와; 상기 게이트전극 및 접합영역 상부에 실리사이드를 형성하는 단계와; 상기 실리사이드를 포함한 전체 구조 상부에 층간절연막이 증착된 후, 상기 접합영역이 노출되도록 식각The present invention includes forming a field oxide film for separating an active region and a field region in a predetermined semiconductor substrate; Forming a gate electrode in a region corresponding to the active region; Forming a junction region by implanting ions into a predetermined portion of the semiconductor substrate using the gate electrode as a mask; Etching the field oxide film and forming a buried layer to cover a contact portion between the field oxide film and a junction region; Forming a silicide on the gate electrode and the junction region; After the interlayer insulating film is deposited on the entire structure including the silicide, the etching region is etched to expose the junction region.
하여 콘택홀을 형성하는 단계를 포함한다.Forming a contact hole.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(f)는 본 발명의 제 1 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 반도체 소자의 단면도이다.2 (a) to 2 (f) are cross-sectional views sequentially illustrating the semiconductor device manufacturing method according to the first embodiment of the present invention.
도 2(a)를 참조하면, 우선 소정의 반도체 기판(1) 상부에 도시되지 않은 패드산화막 및 질화막이 순차적으로 증착된 후, 그 상부에 감광막이 코팅된 후, 소정 마스크를 이용한 노광 및 현상 공정을 통해 소자분리용 감광막패턴이 형성된다. 이후, 감광막패턴을 마스크로 이용한 소정의 식각 공정으로 질화막 및 패드산화막이 순차적으로 패터닝된다.Referring to FIG. 2A, first, a pad oxide film and a nitride film not shown on a predetermined semiconductor substrate 1 are sequentially deposited, and then a photosensitive film is coated thereon, followed by an exposure and development process using a predetermined mask. Through the photosensitive film pattern for device isolation is formed. Thereafter, the nitride film and the pad oxide film are sequentially patterned by a predetermined etching process using the photoresist pattern as a mask.
이후, 패터닝된 질화막을 마스크로 이용한 소정의 식각공정에 의해 반도체기판(1)이 식각되어 도시되지 않은 트렌치가 형성된다. 이후, 감광막패턴이 제거된 후, 트렌치를 포함한 전체 구조 상부에 필드산화막(2)이 증착된 후, 질화막 및 패드산화막을 제거하기 위한 식각공정과 필드산화막(2)을 평탄화하기 위한 CMP공정에 의해 연마되어 트렌치가 매립되도록 형성된다.Thereafter, the semiconductor substrate 1 is etched by a predetermined etching process using the patterned nitride film as a mask to form a trench (not shown). Thereafter, after the photoresist pattern is removed, the field oxide film 2 is deposited on the entire structure including the trench, and then, by the etching process for removing the nitride film and the pad oxide film and the CMP process for planarizing the field oxide film 2. It is polished to form a trench.
이후, 필드산화막(2)을 포함한 전체 구조 상부에 소정의 마스크를 이용한 이온 주입공정(n 또는 p-type 도펀트)을 행하여 반도체 기판(1)의 소정 영역에 N-Well 및 P-Well이 각각 형성된다. 이후, 전체 구조 상부에 도시되지 않은 스크린산화막이 형성된 후, 소정의 마스크를 이용하여 N-Well 및 P-Well에 문턱전압을 조정하기 위한 이온 주입공정이 행해진다.Thereafter, an ion implantation process (n or p-type dopant) using a predetermined mask is performed on the entire structure including the field oxide film 2 to form N-Well and P-Well in predetermined regions of the semiconductor substrate 1, respectively. do. Thereafter, after the screen oxide film (not shown) is formed over the entire structure, an ion implantation process is performed to adjust the threshold voltages on the N-Well and P-Well using a predetermined mask.
이후, 소정의 세정공정에 의해 스크린산화막이 제거된다. 이때, "A"와 같이,세정공정에 의해 필드산화막(2)의 소정 부위가 식각되어 액티브영역의 소정 부위가 노출된다.Thereafter, the screen oxide film is removed by a predetermined cleaning process. At this time, as in " A ", a predetermined portion of the field oxide film 2 is etched by the cleaning process to expose a predetermined portion of the active region.
도 2(b)를 참조하면, 이후, 전체 구조 상부에 게이트산화막(3) 및 다결정실리콘(4)이 소정의 증착공정에 의해 순차적으로 증착된 후, 소정의 감광막패턴을 이용한 식각공정에 의해 다결정실리콘(4) 및 게이트산화막(3)이 순차적으로 식각되어게이트전극(5)이 형성된다.Referring to FIG. 2 (b), the gate oxide film 3 and the polycrystalline silicon 4 are sequentially deposited on the entire structure by a predetermined deposition process, and then polycrystalline by an etching process using a predetermined photoresist pattern. The silicon 4 and the gate oxide film 3 are sequentially etched to form the gate electrode 5.
이후, 게이트전극(5)을 마스크로 하여 반도체 기판(1)의 액티브영역에 LDD 이온 주입공정에 의해 저농도 액티브영역(7)이 형성된다.Thereafter, the low concentration active region 7 is formed by the LDD ion implantation process in the active region of the semiconductor substrate 1 using the gate electrode 5 as a mask.
이후, 게이트전극(5)을 포함한 전체 구조 상부에 스페이서막이 증착된 후, 소정의 식각공정에 의해 식각되어 게이트전극(5)의 양측면에 스페이서(6)가 형성된다.Thereafter, a spacer film is deposited on the entire structure including the gate electrode 5, and then etched by a predetermined etching process to form spacers 6 on both sides of the gate electrode 5.
이후, 스페이서(6)를 마스크로 이용한 이온 주입공정에 의해 저농도 액티브영역(7)의 하부에 고농도 액티브영역(8)이 형성된다.Thereafter, a high concentration active region 8 is formed below the low concentration active region 7 by an ion implantation process using the spacer 6 as a mask.
도 2(c)를 참조하면, 이후, 소정의 감광막패턴을 이용한 식각공정에 의해 반도체 기판(1)의 상단부로부터 500 내지 1000Å의 두께로 필드산화막(2)이 식각된다.Referring to FIG. 2C, the field oxide film 2 is etched from the upper end of the semiconductor substrate 1 to a thickness of 500 to 1000 Å by an etching process using a predetermined photoresist pattern.
여기서, 식각공정을 습식식각을 사용할 경우에는 습식용액으로 BOE가사용된다.Here, when wet etching is used for the etching process, BOE is used as the wet solution.
도 2(d)를 참조하면, 이후, 전체 구조 상부에 BLC의 배리어(barrier)로 500 내지 1500Å 정도의 두께, 바람직하게는 1000Å의 두께로 매립층(9)이 증착된다.Referring to FIG. 2 (d), the buried layer 9 is deposited on the entire structure to a thickness of about 500 to 1500 mW, preferably 1000 mW, as a barrier of the BLC.
여기서, 매립층(9)은 후속공정에서 형성되는 층간절연막의 구성물질인 산화막과 선택비가 우수한 질화막 또는 산화질화막(예를 들면,SiOxNy)으로 형성된다.Here, the buried layer 9 is formed of an oxide film which is a constituent material of the interlayer insulating film formed in a subsequent step, and a nitride film or an oxynitride film (for example, SiOxNy) having excellent selectivity.
도 2(e)를 참조하면, 이후, 매립층(9)에 블랭킷트 식각공정을 행하여 필드산화막(2)과 액티브영역간의 생성된 틈이 매립되도록 증착된 매립층(9)과 스페이서(6) 상부에 형성된 매립층(9)을 제외한 다른 부위에 증착된 매립층(9)은모두 제거된다.Referring to FIG. 2E, a buried etching process is performed on the buried layer 9, and then the buried layer 9 and the spacer 6 are deposited on the buried layer 9 and the spacer 6 to fill the gap formed between the field oxide film 2 and the active region. All of the buried layers 9 deposited on other portions except the formed buried layers 9 are removed.
도 2(f)를 참조하면, 이후, 전체 구조 상부에 Ti가 증착된 후, 소정의 급속 열처리공정에 의해 다결정실리콘(4) 및 저농도 액티브영역(7)의 구성물질과 Ti가 반응하여 다결정실리콘(4) 및 저농도 액티브영역(7) 상부에 TiSi2의 실리사이드(10)가 형성된다. 이후, 다결정실리콘(4) 및 저농도 액티브영역(7)의 구성물질과 반응하지 않고 전체 구조 상부에 잔재하는 Ti는 소정의 식각공정에 의해 제거된다.Referring to FIG. 2 (f), after Ti is deposited on the entire structure, Ti and the constituent materials of the polycrystalline silicon 4 and the low concentration active region 7 react with the polycrystalline silicon by a predetermined rapid heat treatment process. Silicide 10 of TiSi 2 is formed on the upper portion (4) and the low concentration active region 7. Thereafter, Ti remaining on the entire structure without reacting with the constituent materials of the polysilicon 4 and the low concentration active region 7 is removed by a predetermined etching process.
이후, 전체 구조 상부에는 BPSG 또는 TEOS 산화막등이 증착된 후, 낮은 온도(예를 들면 600℃이하)를 이용한 후속공정에 의해 콘택홀(12)이 형성된 층간절연막(11)이 형성된다.Thereafter, after the BPSG or TEOS oxide film is deposited on the entire structure, the interlayer insulating film 11 having the contact hole 12 is formed by a subsequent process using a low temperature (for example, 600 ° C. or less).
콘태홀(12)내에는 도시되지 않은 콘택플러그가 형성되어 액티브영역과 후속공정에서 형성될 캐패시터 또는 상부 금속배선과 전기적인 접속이 이루어진다.A contact plug (not shown) is formed in the contact hole 12 to make electrical connection with an active region and a capacitor or upper metal wiring to be formed in a subsequent process.
도 3은 본 발명의 제 2 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.3 is a cross-sectional view of a semiconductor device for explaining the method of manufacturing the semiconductor device according to the second embodiment of the present invention.
도 3을 참조하면, 우선, 소정의 식각공정을 통해 소정의 반도체 기판(21)이 식각되어 반도체 기판(21)내에 도시되지 않은 트렌치가 형성된다. 이후, 감광막패턴이 제거된 후, 트렌치를 포함한 전체 구조 상부에 필드산화막(22)이 증착된 후, 소정의 평탄화공정에 의해 연마되어 트렌치가 매립되도록 형성된다.Referring to FIG. 3, first, a predetermined semiconductor substrate 21 is etched through a predetermined etching process to form trenches not shown in the semiconductor substrate 21. Thereafter, after the photoresist pattern is removed, the field oxide film 22 is deposited on the entire structure including the trench, and then polished by a predetermined planarization process to form the trench.
이후, 필드산화막(22)을 포함한 전체 구조 상부에 소정의 마스크를 이용한이온 주입공정(n 또는 p-type 도펀트)을 행하여 반도체 기판(21)의 소정 영역에 N-Well 및 P-Well이 각각 형성된다. 이후, 전체 구조 상부에 도시되지 않은 스크린산화막이 형성된 후, 소정의 마스크를 이용하여 N-Well 및 P-Well에 문턱전압을 조정하기 위한 이온 주입공정이 행해진다.Thereafter, an ion implantation process (n or p-type dopant) using a predetermined mask is performed on the entire structure including the field oxide film 22 to form N-Well and P-Well in predetermined regions of the semiconductor substrate 21, respectively. do. Thereafter, after the screen oxide film (not shown) is formed over the entire structure, an ion implantation process is performed to adjust the threshold voltages on the N-Well and P-Well using a predetermined mask.
이후, 전체 구조 상부에 게이트산화막(23) 및 다결정실리콘(24)이 소정의 증착공정에 의해 순차적으로 증착된 후, 소정의 감광막패턴을 이용한 식각공정에 의해 다결정실리콘(24) 및 게이트산화막(23)이 순차적으로 식각되어 게이트전극(25)이 형성된다.Subsequently, the gate oxide film 23 and the polycrystalline silicon 24 are sequentially deposited on the entire structure by a predetermined deposition process, and then the polysilicon 24 and the gate oxide film 23 by an etching process using a predetermined photosensitive film pattern. ) Is sequentially etched to form the gate electrode 25.
이어서, 소정의 감광막패턴을 이용한 식각공정에 의해 반도체 기판(21)의 상단부로부터 500 내지 1000Å의 두께로 필드산화막(22)이 식각된 후, 전체 구조 상부에 스페이서막이 증착된다. 이후, 소정의 제거공정 또는 블랭킷트 식각공정에 의해 스페이서막이 제거되어 게이트전극(25)의 양측면과, 필드산화막(2)과 액티브영역간의 생성된 틈이 매립되도록 스페이서(27)와 매립층(28)이 형성된다. 여기서, 스페이서막은 후속공정에서 형성되는 층간절연막의 구성물질인 산화막과 선택비가 우수한 질화막 또는 산화질화막(예를 들면,SiOxNy)으로 형성된다.Subsequently, the field oxide film 22 is etched from the upper end of the semiconductor substrate 21 to a thickness of 500 to 1000 Å by an etching process using a predetermined photosensitive film pattern, and then a spacer film is deposited on the entire structure. Thereafter, the spacer film is removed by a predetermined removal process or a blanket etching process, so that the gaps between both sides of the gate electrode 25 and the gap formed between the field oxide film 2 and the active region are filled. Is formed. Here, the spacer film is formed of an oxide film, which is a constituent material of the interlayer insulating film formed in a subsequent step, and a nitride film or an oxynitride film (for example, SiOxNy) having excellent selectivity.
이후, 공정은 전술한 본 발명의 제 1 실시예와 동일한 방법으로 이루어진다.The process is then carried out in the same manner as in the first embodiment of the present invention described above.
전술한 본 발명은 도 4에 도시된 바와 같이, 실리사이드를 형성하기전에 소정의 공정을 이용하여 필드산화막과 액티브영역간의 경계면에 생성된 틈을 질화막 또는 산화질화막 물질로 구성된 매립층으로 매립함으로써, BLC공정시 이루어진 열처리 공정이 생략되어 그 만큼 공정을 단순화 할 수 있다.As described above, the present invention described above shows a BLC process by filling a gap formed at the interface between the field oxide film and the active region with a buried layer made of a nitride film or an oxynitride film material using a predetermined process before forming the silicide. Since the heat treatment process is omitted, the process can be simplified.
상술한 바와 같이, 본 발명은 실리사이드를 형성하기전에 소정의 공정을 이용하여 필드산화막과 액티브영역간의 경계면에 생성된 틈을 질화막을 이용하여 매립함으로써, 액티브영역의 종단부에서 반도체 기판의 노출을 방지하여 실리사이드의 측면 퍼짐을 방지할 수 있다. 따라서, 액티브영역의 누설전류를 효과적으로 감소시킬 수 있다.As described above, the present invention prevents exposure of the semiconductor substrate at the end of the active region by filling a gap formed in the interface between the field oxide film and the active region using a nitride film using a predetermined process before forming the silicide. The side spread of the silicide can be prevented. Therefore, the leakage current of the active region can be effectively reduced.
또한, 자기정합 실리사이드를 형성한 후, 질화막 증착을 할 필요가 없어 실리사이드의 단선 현상을 방지함과 아울러 스트레스에 의한 반도체 소자의 열화를 방지할 수 있다.In addition, after forming the self-aligned silicide, it is not necessary to perform nitride film deposition, thereby preventing the disconnection of the silicide and preventing deterioration of the semiconductor device due to stress.
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| KR980012244A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Method for manufacturing semiconductor device |
| US5949126A (en) * | 1997-12-17 | 1999-09-07 | Advanced Micro Devices, Inc. | Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench |
| KR20000014735A (en) * | 1998-08-24 | 2000-03-15 | 김영환 | Semiconductor device and fabrication method thereof |
| KR20000031464A (en) * | 1998-11-06 | 2000-06-05 | 김영환 | Method for forming silicide of semiconductor device |
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| KR980012244A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Method for manufacturing semiconductor device |
| US5949126A (en) * | 1997-12-17 | 1999-09-07 | Advanced Micro Devices, Inc. | Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench |
| KR20000014735A (en) * | 1998-08-24 | 2000-03-15 | 김영환 | Semiconductor device and fabrication method thereof |
| KR20000031464A (en) * | 1998-11-06 | 2000-06-05 | 김영환 | Method for forming silicide of semiconductor device |
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