JP2004165527A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device employing an STI (shallow trench isolation) method, which keeps high degree of flatness without causing dishing or erosion in an CMP (chemical mechanical polishing) process for forming an element isolation region. <P>SOLUTION: The semiconductor device having a region isolated by the STI method on a semiconductor substrate comprises a device region for forming the semiconductor device, a dummy device region 13b, and an oxide film 4 for isolating the device region from the dummy device region 13b. The dummy device region 13b is provided with a cap layer 15 for preventing the dummy device region 13b from turning into silicide. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a region on a semiconductor substrate which is isolated by a shallow trench isolation method.
[0002]
[Prior art]
With the recent increase in the degree of integration of semiconductor devices, miniaturization of element isolation regions has been progressing, and an isolation method based on STI (Shallow Trench Isolation) has been increasingly used from the conventional LOCOS method. In the element isolation by the STI, formation of an oxide film for element isolation and a CMP (chemical mechanical polishing) process of the oxide film are essential, and the CMP method is one of important techniques related to the STI. The steps of manufacturing a semiconductor device using element isolation by STI including the above-described CMP step will be described step by step with reference to FIGS. 1A to 1C and 2D to 2E.
[0003]
Referring to FIG. 1A, first, a 10-nm-thick silicon oxide film 102 is formed on a surface of a semiconductor substrate 101 by hydrochloric acid oxidation at 900 ° C., and then a 110-nm-thick silicon nitride film 103 is deposited by a CVD method. Thereafter, a resist (not shown) is applied on the silicon nitride film 103, and then exposed and developed using a mask for element isolation, and the resist pattern (not shown) is used as a mask to form the resist. The silicon oxide film 102 and the silicon nitride film 103 are anisotropically etched to form a pattern as shown in FIG.
[0004]
Next, in FIG. 1B, after the resist is removed by ashing, the semiconductor substrate 101 is anisotropically etched by 300 nm using the silicon nitride film 103 as a mask, so that the pattern of the silicon nitride film is Transfer to the substrate 101. Thereafter, a silicon oxide film 104 is deposited to a thickness of 500 nm by the CVD method.
[0005]
Next, in FIG. 1C, the silicon oxide film 104 is polished by a CMP (chemical mechanical polishing) method. Thereafter, the silicon nitride film 103 is removed with a boiling phosphoric acid solution, and the silicon oxide film 102 is removed with a hydrofluoric acid-based aqueous solution. Thereafter, a resist (not shown) is applied, and is exposed and developed using a mask for forming a well. As a result, the resist (not shown) which has been patterned is used as a mask to remove 1 × 10 n-type impurities.^ThirteenPieces / cm³The P well 105 is formed by implantation. Similarly, a resist (not shown) is applied, and exposure and development are performed using a mask for forming a well. As a result, a p-type impurity is added to the resist (not shown) at a pattern of 1 × 10^ThirteenPieces / cm³The N well 106 is formed by implantation.
[0006]
Next, in FIG. 2D, a gate oxide film 107 is formed to a thickness of 2.5 nm on the exposed surface of the semiconductor substrate 101 by partial pressure oxidation at 1000 ° C., and a polysilicon film is deposited to a thickness of 180 nm. Next, after applying a resist (not shown), exposure and development are performed using a mask for forming a gate electrode. As a result, the polysilicon film is anisotropically etched using the patterned resist (not shown) as a mask to form a gate electrode 108. Subsequently, to form P-type and N-type LDD regions (not shown), a p-type impurity of 5 × 10¹⁴Pieces / cm³, N-type impurity 1 × 10^{1 4}Pieces / cm³Ions are implanted.
[0007]
Next, in FIG. 2E, after a silicon oxide film is deposited to a thickness of 100 nm by a CVD method, the silicon oxide film is anisotropically etched to form a sidewall 109. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation. Next, after depositing a 10 nm cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 108 and the device region 117.₂The layer 10 is self-aligned (salicide). After that, the unreacted cobalt film is selectively removed.
[0008]
The above is the step before the formation of the contact for wiring. In the CMP step shown in FIG. 1C, the following problem occurs.
[0009]
Referring to FIG. 1C, for example, a silicon oxide film buried in the trenches A1 and A2 of the semiconductor substrate 101 having a large width and trenches B1 and B2 having a smaller width than the trenches A1 and A2. The polished silicon oxide film has a different shape polished by CMP. This is a characteristic inherent to polishing by CMP. Specifically, the polished shape of the oxide film buried in the grooves A1 and A2 is more polished at the center than the polished shape of the oxide film buried in the grooves B1 and B2. The problem that progresses more than this occurs. Such a characteristic is called dishing, and the dishing is indicated by reference numeral 111 in FIG. Further, for example, in a minute device region surrounded by wide grooves indicated by the grooves A1 and A2, for example, in a portion exposed to the surface of the N well 106, polishing of the CMP by the silicon nitride film 103 is stopped. A problem of so-called erosion, in which the semiconductor substrate 101 cannot be cut away, occurs. Reference numeral 112 in the drawing indicates the state of erosion. Since a step on the semiconductor substrate caused by dishing or erosion affects the depth of focus of photolithography, a problem arises in that the patterning shape of the resist varies. For example, in the step of forming the gate electrode shown in FIG. 2D, a problem occurs that the width of the gate electrode varies. In addition, dishing and erosion generally occur when the proportion of the device isolation region where a groove is formed in a semiconductor substrate and an insulating film is formed as described above occupies a large portion of a device region where a device is formed on a semiconductor substrate. It is known to be easier to do.
[0010]
The following methods have been proposed as measures against the dishing and erosion described above. For example, there is a method of forming a dummy region having a structure similar to a device region in a wide element isolation region. Specifically, in the above-described CMP process of FIG. 1C, a structure is adopted in which, for example, a portion where the semiconductor substrate 101 is exposed is increased in the trenches A1 and A2. As a result, the ratio of the device region and the dummy region other than the element isolation region to the element isolation region is increased so that the above-described problem due to the CMP polishing does not occur.
[0011]
[Patent Document 1]
JP-A-2000-77514
[0012]
[Patent Document 2]
JP-A-2001-144171
[0013]
[Problems to be solved by the invention]
However, when the dummy region is formed by the above-described method, the area where the dummy region can be formed may actually be limited. In that case, the ratio of the device region and the dummy region to the element isolation region becomes insufficient, and the above-described dishing and erosion may occur. The reason why the area for forming the dummy region is limited as described above will be described below.
[0014]
First, FIG. 3 is a plan view of the structure of the semiconductor device illustrated in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0015]
When forming a dummy region in this semiconductor device, there is a method of forming a plurality of dummy regions 113 as shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted. Since the dummy region cannot be formed so as to overlap the device region, the gate electrode, and the gate wiring, it is natural that the dummy region 113a overlapping the device region, the gate electrode, and the gate wiring is excluded.
[0016]
However, there is a region where the dummy region cannot be formed for a reason other than contact between the dummy region and a structure such as a device or a gate electrode. For example, CoSi₂In the step of forming a metal silicide such as a layer, the surface of the dummy region 113 is converted into a metal silicide to form CoSi in the same manner as the device region.₂A layer is formed. As described above, the CoSi₂When the layer is formed, if the dummy region overlaps a boundary of the pn-type impurity diffusion layer such as a well or a source / drain, a current flows at the well boundary, causing a problem that a short circuit occurs. For example, a dummy region indicated by 113b in FIG. 4 is formed in a boundary layer between the P well 105 and the N well 106. The problem caused by silicidation of the surface of the dummy region will be described below with reference to FIGS.
[0017]
FIGS. 5A and 5B show examples of the dummy region 113b formed at the well boundary between the P well and the N well. FIG. 5A is a plan view and FIG. 5B is a sectional view thereof. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted. When the surface of the dummy region 113b is silicided as described above, CoSi₂Current flows between the P-well 105 and the N-well 106 via the layer 110 to cause a short circuit, which causes a problem in a circuit. Therefore, it is impossible to arrange the dummy region 113b on the well boundary as it is. FIG. 6 shows a case where the problematic dummy area 113b is deleted as described above. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 6, when the dummy region 113b at the well boundary is deleted, the density of the dummy region around the device region is reduced, and the effect of inserting the dummy region is reduced, so that the dishing and erosion described above occur. There is a problem that occurs. Therefore, for example, Japanese Patent Application Laid-Open No. 2001-118858 proposes a method of arranging a well boundary so as to correspond to a position where an oxide film for element isolation exists, that is, a dummy region does not overlap a well boundary. . FIGS. 7A and 7B show an example of such a dummy region formation. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted. FIG. 7A is a plan view, and FIG. 7B is a cross-sectional view thereof. Referring to FIGS. 7A and 7B, the gap Y is configured so that the well boundary does not contact the dummy region 113b. With this configuration, even if the upper surface of the dummy region 113b is silicided, conduction does not occur between the P well and the N well.
[0018]
However, this method has the following problems. When actually designing the layout of the dummy area, the number of dummy areas formed on the semiconductor substrate is enormous, so it may be necessary to automatically determine the insertion position of the dummy area using a computer program or the like. Most. It is difficult to apply this technique as it is to the layout design of the dummy regions as shown in FIGS. 7A and 7B. That is, it is necessary to newly design a program that can determine the arrangement of the well boundary and the dummy region, and the arrangement of the entire dummy region, and it is necessary to spend new time, labor, and expense for creating and verifying the program.
[0019]
Further, recently, a method of forming a dummy region shown in FIG. 8 has been proposed. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted. Referring to FIG. 6, in consideration of the capacitance between the wiring and the substrate, the dummy regions are arranged obliquely shifted so as to keep the capacitance as uniform as possible even when the dummy regions are inserted. In this case, enabling the dummy region to be automatically inserted so as not to contact the well or the source / drain boundary requires a more complicated program design, and requires more time, labor, and cost.
[0020]
In view of the above, an object of the present invention is to provide a new and useful semiconductor device and a method of manufacturing a semiconductor device that solve the above-mentioned problems.
[0021]
A specific object of the present invention is to provide a highly reliable semiconductor device that maintains good flatness without causing dishing or erosion in a CMP process for forming an element isolation region in a semiconductor device using STI. It is.
[0022]
Another object of the present invention is to make it possible to form a dummy region formed for preventing dishing and erosion in a well boundary layer which is a boundary between a P well and an N well in the CMP step. The purpose of this is to increase the dummy area installation area by relaxing the installation restrictions.
[0023]
[Means for Solving the Problems]
According to the present invention, in a semiconductor device including an element region and an element isolation region formed on a semiconductor substrate, the element region includes a device region in which an element is formed, and the element region and the element isolation region. A device dummy region provided for adjusting an area ratio with respect to the region, and a cap layer for preventing the device dummy region from being silicided is formed in the device dummy region. The problem is solved by a semiconductor device.
[0024]
According to the semiconductor device of the present invention, by forming the device dummy region in which the cap layer is formed, it is possible to prevent dishing and erosion from occurring in the CMP process of the oxide film for element isolation, thereby achieving good flatness. Is obtained. Since a cap layer is provided in the device dummy region after CMP, for example, when a device dummy region is formed at a well boundary between a P well and an N well, silicidation of the surface of the device dummy region is prevented. As a result, it is possible to prevent the P-well and the N-well from being electrically short-circuited and flowing current. Therefore, a device dummy region can be formed at the well boundary. That is, the surface on which the device dummy region can be formed on the semiconductor substrate increases. As a result, the effect of suppressing the dishing and erosion is enhanced, and the flatness is improved. Further, since the device dummy area can be arranged at the well boundary, the restriction in designing the device dummy area is reduced, and the dummy area can be easily arranged by a conventional extension method. Become.
[0025]
The present invention also provides a method of manufacturing a semiconductor device including forming a device region and a device isolation region on a semiconductor substrate, and including a silicide process, wherein the device region is a device region in which a device is formed. And a device dummy region provided for adjusting an area ratio between the element region and the element isolation region, and a cap layer is provided in the device dummy region, and the device dummy region is provided in the silicide process. The problem is solved by a method for manufacturing a semiconductor device characterized in that silicidation is prevented.
[0026]
According to the method for manufacturing a semiconductor device of the present invention, by forming the device dummy region in which the cap layer is formed, it is possible to prevent dishing and erosion from occurring in the CMP process of the oxide film for element isolation. The flatness after the perfect CPM polishing can be obtained. Since a cap layer is provided in the device dummy region after CMP, for example, when a device dummy region is formed at a well boundary between a P well and an N well, silicidation of the surface of the device dummy region is prevented. As a result, it is possible to prevent the P-well and the N-well from being electrically short-circuited and flowing current. Therefore, a device dummy region can be formed at the well boundary. That is, the surface on which the device dummy region can be formed on the semiconductor substrate increases. As a result, the effect of suppressing the dishing and erosion is enhanced, and the flatness is improved. Further, since the device dummy area can be arranged at the well boundary, the restriction in designing the device dummy area arrangement is reduced, and the dummy area can be easily arranged.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
In the present invention, a dummy region is formed to prevent dishing and erosion in a CMP process of an oxide film for element isolation of STI. Further, a cap layer is formed on the dummy region after the CMP step to prevent the surface of the dummy area from being silicided in a step after the CMP step. Therefore, a dummy region can be formed at the boundary of the pn-type impurity diffusion layer on the semiconductor substrate, and the above-mentioned dishing and erosion can be effectively prevented by increasing the dummy region formation area.
[0028]
Next, a specific method for forming the cap layer on the dummy region will be described below with reference to the drawings.
[First embodiment]
FIG. 9 is a plan view showing a device region formed on the semiconductor substrate 1 and a dummy region according to the present invention.
[0029]
Referring to FIG. 9, a P-well 5 formed by ion-implanting an n-type impurity and an N-well 6 formed by ion-implanting a p-type impurity are formed on the semiconductor substrate 1. Further, a device region 17 as an active region and a dummy region 13b separated by the oxide film 4 are formed. A gate electrode 8 made of polysilicon is formed on the device region 17 and a part of the oxide film 4 so as to extend over the device region 17.
[0030]
A gate oxide film described later is formed on the dummy region 13b, a polysilicon cover 14 is formed on the gate oxide film, and a sidewall 9 is formed on a side wall of the polysilicon cover.
[0031]
FIG. 10 is a cross-sectional view taken along line xx of the device region and the dummy region shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0032]
Referring to FIG. 10, a device region 17 separated by the oxide film 4 is formed on the semiconductor substrate 1, and a surface of the device region 17 covered with the gate electrode 8 has a gate. An oxide film 7 is formed. Sidewalls 9 are formed on the side walls of the gate electrode.
[0033]
The dummy region 13b is formed around the device region 17, and the dummy region 13b is covered with the gate oxide film 7 and the polysilicon cover 14. Further, the sidewall 9 is formed on the side wall of the polysilicon cover 14.
[0034]
On the gate electrode 8 and the polysilicon cover 14, CoSi formed in a silicide process is formed.₂A layer 10 has been formed.
[0035]
Here, an enlarged view of the dummy region 13b is shown in FIG.
[0036]
Referring to FIG. 11, since the portion where the dummy region 13b is arranged has no element or gate wiring which can be a device, there is no problem even if the polysilicon cover 14 is formed. After the formation of the polysilicon cover 14, the side wall 9 and the CoSi₂The layer 10 is formed. Since the polysilicon cover 14 can be formed simultaneously with the gate electrode 8, the polysilicon cover 14 can be formed in the same process as the conventional process without newly adding a mask layer or adding the number of processes.
[0037]
According to the present embodiment, even if the device region 17 and the gate electrode 8 are made of metal silicide, the gate oxide film 7 insulates the dummy region 13b and the polysilicon cover 14 from each other. Therefore, even if the dummy region 13b is arranged on the well boundary between the N well and the P well, no short circuit occurs between the wells. Therefore, it is possible to arrange the dummy region at the well boundary, and the area for installing the dummy region increases. As a result, dishing and erosion can be effectively prevented in the CMP process of the STI element isolation oxide film. In addition, when the dummy area is set, the restriction that the dummy area cannot be set at the well boundary is eliminated, and the burden of designing the dummy area is reduced.
[0038]
Next, FIGS. 12A to 12C and FIGS. 13D to 13F show manufacturing steps of the semiconductor device including the dummy region 13b of the present embodiment. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0039]
Referring to FIG. 12A, first, a 10 nm-thick silicon oxide film 2 is formed on the surface of a semiconductor substrate 1 by 900 ° C. hydrochloric acid oxidation, and then a 110 nm silicon nitride film 3 is deposited by a CVD method. Thereafter, a resist (not shown) is applied on the nitride film 3 and then exposed and developed using a mask for element isolation, and the silicon (Si) is formed using the formed resist pattern (not shown) as a mask. The oxide film 2 and the silicon nitride film 3 are anisotropically etched to form a pattern as shown in FIG.
[0040]
Next, in FIG. 12B, after the resist is removed by ashing, the semiconductor substrate 1 is anisotropically etched by 300 nm using the silicon nitride film 3 as a mask to change the pattern of the silicon nitride film to the semiconductor. Transfer to the substrate 1. Thereafter, a silicon oxide film 4 is deposited to a thickness of 500 nm by the CVD method. Thus, the device region De where the device region is formed and the dummy region Du where the dummy region according to the present invention is formed are separated by the silicon oxide film 4. The dummy region 13b according to the present invention is formed in the dummy region Du.
[0041]
Next, in FIG. 12C, the silicon oxide film 4 is polished by a CMP (Chemical Mechanical Polishing) method. In this case, since the dummy region 13b according to the present invention is formed, it is possible to prevent problems such as dishing and erosion by CMP and obtain good flatness. Thereafter, the silicon nitride film 3 is removed with a boiling phosphoric acid solution, and the silicon oxide film 2 is removed with a hydrofluoric acid-based aqueous solution. Thereafter, a resist (not shown) is applied, and is exposed and developed using a mask for forming a well. As a result, the resist (not shown) which has been patterned is used as a mask to remove 1 × 10 n-type impurities.^ThirteenPieces / cm³The P well region 5 is formed by implantation. Similarly, a resist (not shown) is applied, and exposure and development are performed using a mask for forming a well. As a result, a p-type impurity is added to the resist (not shown) at a pattern of 1 × 10^ThirteenPieces / cm³The N well region 6 is formed by implantation.
[0042]
Next, in FIG. 13D, a gate oxide film 7 is formed to a thickness of 2.5 nm on the exposed surface of the semiconductor substrate 1 by partial pressure oxidation at 1000 ° C., and a polysilicon film is deposited to a thickness of 180 nm. Next, after applying a resist (not shown), exposure and development are performed using a mask for forming a gate electrode and a polysilicon cover. As a result, the polysilicon film is anisotropically etched using the patterned resist (not shown) as a mask to form gate electrode 8 and polysilicon cover 14. Subsequently, to form P-type and N-type LDD regions (not shown), a p-type impurity of 1 × 10¹⁴Pieces / cm³, N-type impurity 5 × 10¹⁴Pieces / cm³Ions are implanted.
[0043]
Next, in FIG. 13E, a silicon oxide film 9 'for depositing a sidewall is deposited to a thickness of 100 nm by a CVD method.
[0044]
Next, in FIG. 13 (F), a side wall 9 is formed by anisotropically etching the silicon oxide film 9 '. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation. Next, after depositing a 10 nm-thick cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 8 and the device section 17.₂The layer 10 is self-aligned (salicide). In this case, the dummy region 13b is covered with the gate oxide film 7 and the polysilicon cover 14, which are cap layers according to the present invention. Therefore, the dummy region 13b is not turned into metal silicide, and the problem that a current flows on the boundary of the pn-type impurity diffusion layer and short-circuit does not occur. Therefore, it is possible to form the dummy region 13b at the well boundary as described above.
[0045]
Thereafter, the unreacted cobalt film is selectively removed, and the state shown in FIG. 10 is obtained.
[Second embodiment]
FIG. 14 is a plan view showing a device region formed on the semiconductor substrate 1 and a dummy region according to the present invention. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0046]
Referring to FIG. 14, in the case of the present embodiment, the size of the polysilicon cover 14 is smaller than in the case of the first embodiment. The details will be described later.
[0047]
FIG. 15 is a cross-sectional view taken along line xx of the device region and the dummy region shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0048]
The dummy region 13b is formed around the device region 17, and the dummy region 13b is covered with the gate oxide film 7 and the polysilicon cover 14. Further, the side wall 9 is formed on the side wall of the polysilicon cover 14. In this embodiment, since the polysilicon cover 14 is small, a part of the side wall 9 is partially formed on the dummy region 13b. Covering.
[0049]
Here, an enlarged view of the dummy region 13b is shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0050]
Referring to FIG. 16, the width W3 of the polysilicon cover 14 is smaller than the width W2 of the dummy region 13b. This is a structure as shown in this figure when it is necessary to limit the interval between the dummy regions 14 of polysilicon due to, for example, the limitation on the width of the gate electrode. In this case, silicidation of the dummy region 13b can be prevented by covering the portion of the dummy region 13b protruding from the polysilicon cover 14 with the sidewall 9. This embodiment can be applied when the width W1 of the sidewall 9 is larger than the dummy region 13b. Also in this embodiment, as in the case of the first embodiment, the polysilicon cover 14 can be formed simultaneously with the gate electrode. Can be formed in the same process as in the related art without adding the same.
[0051]
According to the present embodiment, even if the device region 17 and the gate electrode 8 are made into metal silicide, the space between the dummy region 13b and the polysilicon cover 14 is insulated by the gate oxide film 7 and further covered by the sidewall 9. Has been done. Therefore, even if the dummy region 13b is arranged on the well boundary between the N well and the P well, no short circuit occurs between the wells. Therefore, it is possible to arrange the dummy region at the well boundary, and the area for installing the dummy region increases. As a result, dishing and erosion can be effectively prevented in the CMP process of the STI element isolation oxide film. In addition, when the dummy area is set, the restriction that the dummy area cannot be set at the well boundary is eliminated, and the burden of designing the dummy area is reduced.
[0052]
17 (A) to 17 (C) and FIGS. 18 (D) to 18 (F) show the steps of manufacturing the semiconductor device including the dummy region 13b according to the present embodiment. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0053]
The steps of FIGS. 17A to 17C are the same as the steps of FIGS. 12A to 12C described in the first embodiment.
[0054]
18D, a gate oxide film 7 is formed to a thickness of 2.5 nm on the exposed surface of the semiconductor substrate 1 by partial pressure oxidation at 1000 ° C., and a polysilicon film is deposited to a thickness of 180 nm. Next, after applying a resist (not shown), exposure and development are performed using a mask for forming a gate electrode and a polysilicon cover. As a result, the polysilicon film is anisotropically etched using the patterned resist (not shown) as a mask to form gate electrode 8 and polysilicon cover 14. Subsequently, to form P-type and N-type LDD regions (not shown), a p-type impurity of 1 × 10¹⁴Pieces / cm³, N-type impurity 5 × 10¹⁴Pieces / cm³Ions are implanted.
[0055]
Next, in FIG. 18E, a silicon oxide film 9 'for depositing a sidewall is deposited to a thickness of 100 nm by a CVD method.
[0056]
Next, in FIG. 18F, the sidewalls 9 are formed by anisotropically etching the silicon oxide film 9 '. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation. Next, after depositing a 10 nm-thick cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 8 and the device section 17.₂The layer 10 is self-aligned (salicide). In this case, a part of the dummy region 13b is covered with the gate oxide film 7 and the polysilicon cover 14, which are cap layers according to the present invention. Further, in the case of the present embodiment, since the width of the gate oxide film 7 and the polysilicon cover 14 is smaller than the width of the dummy region 13b, the surface on the dummy region 13b is further covered by the sidewall 9, The entire surface of the dummy region 13b is covered. Therefore, the dummy region 13b is not turned into metal silicide, and the problem that a current flows on the boundary of the pn-type impurity diffusion layer and short-circuit does not occur. Therefore, it is possible to form the dummy region 13b at the well boundary as described above.
[0057]
Thereafter, the unreacted cobalt film is selectively removed to obtain the state shown in FIG.
[Third embodiment]
FIG. 19 is a plan view showing a device region formed on the semiconductor substrate 1 and a dummy region according to the present invention. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0058]
Referring to FIG. 19, in the case of the present embodiment, a protective layer 15 made of a silicon oxide film is formed on the dummy region 13b.
[0059]
FIG. 20 is a cross-sectional view taken along line xx of the device region and the dummy region shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0060]
The dummy region 13b is formed around the device region 17, and a protective layer 15 made of a silicon oxide film is formed on the dummy region 13b.
[0061]
Here, an enlarged view of the dummy region 13b is shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0062]
Referring to FIG. 21, a protective layer 15 made of an insulating film such as a silicon oxide film is formed on the dummy region 13b so as to completely cover the dummy region 13b. The protective layer 15 can be formed simultaneously, for example, in the step of forming the sidewall 9. Usually, in the step of forming the side wall, an oxide film is deposited after the formation of the gate electrode 8, and the side wall is formed by performing anisotropic etching without using a mask. In this embodiment, in order to form the protective layer 15, a resist is coated, exposed and developed after the oxide film is deposited for forming the side wall to form a mask for forming the protective layer 15. It is necessary to provide a step of performing Thereafter, by performing anisotropic etching, the side wall 9 of the gate electrode in the device region 17 and the protective layer 15 can be simultaneously formed. Since the formation of the sidewall is usually performed without a mask, a mask step needs to be added in the case of this embodiment. However, since the oxide film of the protective layer 15 is deposited simultaneously with the deposition of the oxide film on the sidewall, it is not necessary to add an oxide film deposition step. Further, for example, when a polysilicon electrode is used as a resistance element without being converted into a metal silicide, an oxide film is formed on the polysilicon electrode by adding a mask step after depositing an insulating film for forming a sidewall. . In that case, it is possible to form a mask for the protective layer 15 formed in this embodiment in the step of forming a mask on polysilicon, and it is necessary to add a new step even if the protective layer 15 is formed. There is no.
[0063]
According to this embodiment, the dummy region 13b is covered with the protective layer 15 made of an oxide film even if the device region 17 and the gate electrode 8 are made of metal silicide. Therefore, even if the dummy region 13b is arranged on the well boundary between the N well and the P well, no short circuit occurs between the wells. Therefore, it is possible to arrange the dummy region at the well boundary, and the area for installing the dummy region increases. As a result, dishing and erosion can be effectively prevented in the CMP process of the STI element isolation oxide film. In addition, when the dummy area is set, the restriction that the dummy area cannot be set at the well boundary is eliminated, and the burden of designing the dummy area is reduced.
[0064]
Next, FIGS. 22A to 22C, FIGS. 23D to 23F, and FIG. 24G show the manufacturing steps of the semiconductor device including the dummy region 13b of this embodiment. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0065]
The steps of FIGS. 22A to 22C are the same as the steps of FIGS. 12A to 12C described in the first embodiment.
[0066]
Next, in FIG. 23D, a gate oxide film 7 is formed to a thickness of 2.5 nm on the exposed surface of the semiconductor substrate 1 by partial pressure oxidation at 1000 ° C., and a polysilicon film is deposited to a thickness of 180 nm. Next, after applying a resist (not shown), exposure and development are performed using a mask for forming a gate electrode. As a result, the polysilicon film is anisotropically etched using the patterned resist (not shown) as a mask to form a gate electrode 8. Subsequently, to form P-type and N-type LDD regions (not shown), a p-type impurity of 1 × 10¹⁴Pieces / cm³, N-type impurity 5 × 10^{1 4}Pieces / cm³Ions are implanted.
[0067]
Next, in FIG. 23E, a silicon oxide film 9 'for depositing a sidewall and a protective layer is deposited to a thickness of 100 nm by a CVD method.
[0068]
Next, in FIG. 23F, after applying a resist for patterning the protective layer, exposure and development are performed to form a resist pattern 18 for forming the protective layer.
[0069]
Next, in FIG. 24G, the silicon oxide film 9 'is anisotropically etched to form the sidewalls 9 and the protective layer 15 at the same time. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation. Next, after depositing a 10 nm-thick cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 8 and the device section 17.₂The layer 10 is self-aligned (salicide). In this case, the dummy region 13b is covered with the protective layer 15, which is a cap layer according to the present invention. Therefore, the dummy region 13b is not turned into metal silicide, and the problem that a current flows on the boundary of the pn-type impurity diffusion layer and short-circuit does not occur. Therefore, it is possible to form the dummy region 13b at the well boundary as described above.
[0070]
Thereafter, the unreacted cobalt film is selectively removed to obtain the state shown in FIG.
[Fourth embodiment]
FIG. 25 is a plan view showing a device region formed on the semiconductor substrate 1 and a dummy region according to the present invention. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0071]
Referring to FIG. 25, in the case of the present embodiment, a protective layer 16 made of a silicon oxide film is formed on the dummy region 13b.
[0072]
FIG. 26 is a cross-sectional view taken along line xx of the device region and the dummy region shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0073]
The dummy region 13b is formed around the device region 17, and a protective layer 16 made of a silicon oxide film is formed on the dummy region 13b.
[0074]
Here, an enlarged view of the dummy region 13b is shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0075]
Referring to FIG. 27, a protective layer 16 made of an insulating film, for example, a silicon oxide film is formed on the dummy region 13b so as to completely cover the dummy region 13b. The protective layer 16 is formed, for example, after forming the sidewall 9. In the present embodiment, a step of depositing an oxide film to form the protective layer 16 and a step of forming a mask for forming the protective layer 16 by applying a resist and exposing and developing the resist thereafter. Must be provided. Thereafter, the protective layer 16 can be formed by performing anisotropic etching. In this case, it is necessary to add an oxide film deposition step and a mask step. However, for example, in consideration of a device forming process, when a diffusion layer in a device region is used as a resistance element without being converted into metal silicide, an insulating film layer is formed on the diffusion layer in the device region. In this case, since it can be formed simultaneously with the protective layer 16 in this embodiment, it is not necessary to increase the number of steps. According to the present embodiment, the dummy region 13b is covered with the protective layer 16 made of a silicon oxide film even if the device region 17 and the gate electrode 8 are made of metal silicide. Therefore, even if the dummy region 13b is arranged on the well boundary between the N well and the P well, no short circuit occurs between the wells. Therefore, it is possible to arrange the dummy region at the well boundary, and the area for installing the dummy region increases. As a result, dishing and erosion can be effectively prevented in the CMP process of the STI element isolation oxide film. In addition, when the dummy area is set, the restriction that the dummy area cannot be set at the well boundary is eliminated, and the burden of designing the dummy area is reduced.
[0076]
Next, FIGS. 28A to 28C, FIGS. 29D to 29F, and FIGS. 30G to 30I show the manufacturing steps of the semiconductor device including the dummy region 13b of this embodiment. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0077]
28 (A) to (C) and FIGS. 29 (D) to (E) correspond to FIGS. 22 (A) to (C) and FIGS. 23 (D) to (E) of the third embodiment, respectively. Is the same as that of the step.
[0078]
Next, in FIG. 29F, a sidewall 9 is formed by anisotropically etching the silicon oxide film 9 '. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation.
[0079]
Next, in FIG. 30G, a silicon oxide film 16 'for depositing a protective layer is deposited to a thickness of 50 nm by a CVD method.
[0080]
Next, in FIG. 30H, after a resist for patterning the protective layer of the oxide film is applied, exposure and development are performed to form a resist pattern 19 for forming the protective layer.
[0081]
Next, in FIG. 30I, the protective layer 16 is formed by anisotropically etching the silicon oxide film 16 '. Next, after depositing a 10 nm-thick cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 8 and the device section 17.₂The layer 10 is self-aligned (salicide). In this case, the dummy region 13b is covered with the protective layer 16, which is a cap layer according to the present invention. Therefore, the dummy region 13b is not turned into metal silicide, and the problem that a current flows on the boundary of the pn-type impurity diffusion layer and short-circuit does not occur. Therefore, it is possible to form the dummy region 13b at the well boundary in this way.
[0082]
Thereafter, the unreacted cobalt film is selectively removed to obtain the state shown in FIG.
[Fifth embodiment]
FIG. 31 is a plan view showing a device region formed on the semiconductor substrate 1 and a dummy region according to the present invention. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0083]
Referring to FIG. 31, in the case of the present embodiment, a gate oxide film is formed on the dummy region 13b, a polysilicon cover 14 is formed on the gate oxide film, and further covers the polysilicon cover 14. Thus, protective layer 21 made of a silicon oxide film is formed.
[0084]
FIG. 32 is a sectional view of the device region and the dummy region shown in FIG. 14 taken along line xx. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0085]
The dummy region 13b is formed around the device region 17, the gate oxide film 7 is formed on the dummy region 13b, and the polysilicon cover 14 is formed on the gate oxide film 7. I have. Further, a protective layer 21 made of a silicon oxide film is formed so as to cover the polysilicon cover 14 and the dummy region 13b. In this embodiment, since the polysilicon cover 14 is small, a part of the protective layer 21 covers a part of the dummy region 13b.
[0086]
Here, an enlarged view of the dummy region 13b is shown in FIG. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0087]
This embodiment is an application example of the present invention when the width W3 of the polysilicon cover 14 shown in FIG. 16 in the second embodiment is further reduced. This is because, in recent years, in controlling the width of a gate electrode in polysilicon processing, it is necessary to insert a polysilicon cover because the ratio of a gate electrode pattern occupying in a semiconductor device largely depends on the width of the gate electrode. This is because the polysilicon cover must be smaller than in the second embodiment. In this embodiment, since the width W3 'of the polysilicon cover 14 is smaller than the width W3 of the second embodiment, when the sidewall is formed by the usual method, the sidewall forms the surface of the dummy region 13b. It is impossible to cover all. Therefore, for example, in the step of forming a sidewall, after depositing an oxide film for forming the sidewall, a mask for forming a protective layer 21 that covers the entire surface of the dummy region 13b by applying a resist, exposing and developing the resist is used. It is necessary to provide a forming step. Thereafter, by performing anisotropic etching, the side wall of the gate electrode in the device portion and the protective layer 21 covering the entire surface of the dummy region 13b can be simultaneously formed. Since the formation of the sidewall is usually performed without a mask, a mask step needs to be added in the case of this embodiment. However, since the protective layer 21 is deposited simultaneously with the deposition of the oxide film on the sidewall, it is not necessary to add an oxide film deposition step. Further, for example, when a polysilicon electrode is used as a resistance element without being converted into a metal silicide, an oxide film is formed on the polysilicon electrode by adding a mask step after depositing an insulating film for forming a sidewall. . In that case, it is possible to form a mask for the protective layer 21 formed in this embodiment in the step of forming a mask on polysilicon, and it is necessary to add a new step even if the protective layer 21 is formed. There is no. Further, when forming the protective layer 21 in this embodiment, the step of forming the protective layer 16 described in the fourth embodiment may be applied.
[0088]
According to the present embodiment, the dummy region 13b is covered with the protective layer 21 made of an oxide film even if the device region 17 and the gate electrode 8 are made of metal silicide. Therefore, even if the dummy region 13b is arranged on the well boundary between the N well and the P well, no short circuit occurs between the wells. Therefore, it is possible to arrange the dummy region at the well boundary, and the area for installing the dummy region increases. As a result, dishing and erosion can be effectively prevented in the CMP process of the STI element isolation oxide film. In addition, when the dummy area is set, the restriction that the dummy area cannot be set at the well boundary is eliminated, and the burden of designing the dummy area is reduced.
[0089]
Next, FIGS. 34 (A) to (C), FIGS. 35 (D) to (F), and FIG. 36 (G) show the manufacturing steps of the semiconductor device including the dummy region 13b of this embodiment. However, in the figure, the parts described above are denoted by the same reference numerals, and description thereof will be omitted.
[0090]
The steps of FIGS. 34A to 34C are the same as the steps of FIGS. 12A to 12C of the first embodiment, respectively.
[0091]
Next, in FIG. 35D, a gate oxide film 7 is formed to a thickness of 2.5 nm on the exposed surface of the semiconductor substrate 1 by partial pressure oxidation at 1000 ° C., and a polysilicon film is deposited to a thickness of 180 nm. Next, after applying a resist (not shown), exposure and development are performed using a mask for forming a gate electrode and a polysilicon cover. As a result, the polysilicon film is anisotropically etched using the patterned resist (not shown) as a mask to form gate electrode 8 and polysilicon cover 14. Subsequently, to form P-type and N-type LDD regions (not shown), a p-type impurity of 1 × 10¹⁴Pieces / cm³, N-type impurity 5 × 10¹⁴Pieces / cm³Ions are implanted.
[0092]
Next, in FIG. 35E, a silicon oxide film 9 'for depositing a sidewall and a protective layer is deposited to a thickness of 100 nm by a CVD method.
[0093]
Next, in FIG. 35F, after applying a resist for patterning the protective layer of the oxide film, exposure and development are performed to form a resist pattern 20 for forming the protective layer.
[0094]
Next, in FIG. 36 (G), the side wall 9 and the protective layer 21 are simultaneously formed by anisotropically etching the silicon oxide film 9 '. Further, the P-type and N-type source / drain regions (not shown) are each formed with a p-type impurity of 1 × 10^FifteenPieces / cm³, N-type impurity 1 × 10^FifteenPieces / cm³It is formed by ion implantation. Next, after depositing a 10 nm-thick cobalt film by sputtering, annealing is performed at 850 ° C. to deposit CoSi on the gate electrode 8 and the device section 17.₂The layer 10 is self-aligned (salicide). In this case, the dummy region 13b is covered with the gate oxide film 7, which is a cap layer according to the present invention, and the polysilicon cover 14. Further, in the case of the present embodiment, since the width of the gate oxide film 7 and the polysilicon cover 14 is smaller than the width of the dummy region 13b, the surface over the dummy region 13b is further covered by the protective layer 21, The entire surface of the dummy region 13b is covered. Therefore, the dummy region 13b is not turned into metal silicide, and the problem that a current flows on the boundary of the pn-type impurity diffusion layer and short-circuit does not occur. Therefore, it is possible to form the dummy region 13b at the well boundary in this way.
[0095]
Thereafter, the unreacted cobalt film is selectively removed to obtain the state shown in FIG.
[0096]
As described above, the present invention has been described with reference to the preferred embodiments. However, the present invention is not limited to the above-described specific embodiments, and various modifications and changes can be made within the scope of the claims.
[0097]
For example, regarding the first to fifth embodiments described above, the method for forming the cap layer is not limited to the above-described specific method. For example, with respect to the protective layer 21 described in the fifth embodiment, a film forming step of the protective layer 21 may be separately provided, or a deposition step for forming the protective layer as described in the fourth embodiment, It is also possible to provide a mask step. As an example of the insulating film used for the cap layer, a silicon oxide film (SiO₂) Was used, but other insulating films, such as SiN, SiON, SiCON, SiC, SiCO, and SiCO (H) films, can be used. In addition, a case where a CVD method (chemical vapor deposition) is used as a method for forming an insulating film is described, but the present invention is not limited to this. For example, a PVD method, a spin coating method, or the like is used. However, it is possible to obtain the same effect as that described in the above embodiment.
[0098]
(Supplementary Note 1) In a semiconductor device including an element region and an element isolation region formed on a semiconductor substrate,
The device region has a device region in which a device is formed, and a device dummy region provided for adjusting an area ratio between the device region and the device isolation region,
A semiconductor device, wherein a cap layer for preventing the device dummy region from being silicided is formed on the device dummy region.
[0099]
(Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the cap layer includes an insulating film.
[0100]
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the device dummy region includes a well boundary between a P well region and an N well region, and the cap layer is formed on the well boundary.
[0101]
(Supplementary Note 4) The semiconductor device according to Supplementary Note 3, wherein the cap layer prevents the P well region and the N well region from being electrically short-circuited.
[0102]
(Supplementary Note 5) The semiconductor device according to any one of Supplementary notes 1 to 4, wherein the cap layer is configured by a film formed in a step of forming the element.
[0103]
(Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 2 to 5, wherein the insulating film is formed on a surface of the semiconductor substrate.
[0104]
(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein a dielectric film is further formed on the insulating film.
[0105]
(Supplementary Note 8) The semiconductor device according to supplementary note 7, wherein the dielectric film is made of polysilicon.
[0106]
(Supplementary Note 9) The semiconductor device according to supplementary note 7 or 8, wherein another insulating film is further formed so as to cover the dielectric film.
[0107]
(Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the semiconductor substrate is a silicon substrate.
[0108]
(Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 2 to 10, wherein the insulating film is a silicon oxide film.
[0109]
(Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 9 to 11, wherein the another insulating film is a silicon oxide film.
[0110]
(Supplementary Note 13) An element region and an element isolation region are provided on a semiconductor substrate, and the element region is a device for adjusting an area ratio between the device region where the element is formed and the element region and the element isolation region. A method of manufacturing a semiconductor device comprising a dummy region,
Forming an element in the device region;
Forming a cap layer in the device dummy region;
Silicidizing the device region,
The method of manufacturing a semiconductor device, wherein the cap layer includes an insulating layer and prevents the device dummy region from being silicided.
[0111]
(Supplementary note 14) The method for manufacturing a semiconductor device according to Supplementary note 13, wherein the device dummy region includes a well boundary between a P well region and an N well region, and the cap layer is formed on the well boundary. .
[0112]
(Supplementary Note 15) The method according to Supplementary Note 14, wherein the cap layer prevents the P-well region and the N-well region from being electrically short-circuited.
[0113]
(Supplementary Note 16) The step of forming a cap layer in the device dummy region is performed together with the step of forming an element in the device region, wherein the element has a gate insulating film, and the insulating film and the gate insulating film are simultaneously formed. 16. The method for manufacturing a semiconductor device according to any one of supplementary notes 13 to 15, wherein the film is formed.
[0114]
(Supplementary Note 17) The device has a gate electrode film on the gate insulating film, and the cap layer has a dielectric film on the insulating film,
17. The method for manufacturing a semiconductor device according to claim 16, wherein the gate electrode film and the dielectric film are simultaneously formed.
[0115]
(Supplementary Note 18) The device has a sidewall film covering the gate electrode film, and the cap layer has another insulating film covering the dielectric film,
18. The method for manufacturing a semiconductor device according to claim 17, wherein the sidewall film and the another insulating film are simultaneously formed.
[0116]
(Supplementary Note 19) The element has a gate insulating film, a gate electrode film on the gate insulating film, and a sidewall film covering the gate electrode film, and the sidewall film and the insulating film are simultaneously formed. 16. The method of manufacturing a semiconductor device according to any one of supplementary notes 13 to 15, wherein:
[0117]
【The invention's effect】
According to the present invention, in manufacturing a semiconductor device using STI, it has become possible to maintain good flatness without causing dishing or erosion in a CMP process for forming an element isolation region. In the present invention, in the CMP step, a cap layer is provided on a dummy formed for preventing dishing and erosion, so that, for example, when a device dummy region is formed at a well boundary between a P well and an N well, the device The surface of the dummy region is prevented from being silicided. As a result, it is possible to prevent a current from flowing due to an electrical short between the P well and the N well, and to form a device dummy region in the well boundary layer. That is, the surface on which the device dummy region can be formed on the semiconductor substrate increases. As a result, the effect of suppressing the dishing and erosion is enhanced, and the flatness is improved. Further, since the device dummy area can be arranged at the well boundary, the restriction in designing the device dummy area is reduced, and the dummy area can be easily arranged by a conventional extension method. became.
[Brief description of the drawings]
FIGS. 1A, 1B, and 1C are diagrams illustrating a manufacturing process of a semiconductor device using conventional STI element isolation (part 1); FIGS.
FIGS. 2D and 2E are diagrams (part 2) illustrating a process for manufacturing a semiconductor device using conventional STI element isolation.
FIG. 3 is a plan view of the semiconductor device after a gate electrode is formed.
FIG. 4 is a plan view (part 1) of a semiconductor device in which a dummy region is formed.
FIG. 5 is a diagram (part 1) illustrating an example of a case where a dummy region is formed into a metal silicide;
FIG. 6 is a plan view (part 2) of the semiconductor device in which a dummy region is formed.
FIG. 7 is a diagram (part 2) illustrating an example of a case where a dummy region is metal silicidized;
FIG. 8 is a plan view (part 3) of the semiconductor device in which a dummy region is formed.
FIG. 9 is a plan view of a semiconductor device in which a dummy region is formed according to the first embodiment of the present invention.
FIG. 10 is a sectional view of a semiconductor device in which a dummy region is formed according to the first embodiment of the present invention.
FIG. 11 is a sectional view of a dummy region according to the first embodiment of the present invention.
FIGS. 12A to 12C are diagrams (part 1) illustrating the steps of manufacturing the semiconductor device according to the first embodiment of the present invention;
13 (D) to 13 (F) are views (No. 2) showing the steps of manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 14 is a plan view of a semiconductor device in which a dummy region is formed according to a second embodiment of the present invention.
FIG. 15 is a sectional view of a semiconductor device in which a dummy region is formed according to a second embodiment of the present invention.
FIG. 16 is a sectional view of a dummy region according to a second embodiment of the present invention.
FIGS. 17A to 17C are diagrams (part 1) illustrating the steps of manufacturing the semiconductor device according to the second embodiment of the present invention;
18 (D) to (F) are views (No. 2) showing the steps of manufacturing the semiconductor device according to the second embodiment of the present invention.
FIG. 19 is a plan view of a semiconductor device in which a dummy region is formed according to a third embodiment of the present invention.
FIG. 20 is a sectional view of a semiconductor device in which a dummy region is formed according to a third embodiment of the present invention.
FIG. 21 is a sectional view of a dummy region according to a third embodiment of the present invention.
FIGS. 22A to 22C are diagrams (part 1) illustrating the steps of manufacturing the semiconductor device according to the third embodiment of the present invention;
FIGS. 23 (D) to (F) are diagrams (part 2) illustrating a process for manufacturing the semiconductor device according to the third embodiment of the present invention; FIGS.
FIG. 24G is a view showing a manufacturing process (part 3) of a semiconductor device according to a third embodiment of the present invention;
FIG. 25 is a plan view of a semiconductor device in which a dummy region is formed according to a fourth embodiment of the present invention.
FIG. 26 is a sectional view of a semiconductor device in which a dummy region is formed according to a fourth embodiment of the present invention.
FIG. 27 is a sectional view of a dummy region according to a fourth embodiment of the present invention.
FIGS. 28A to 28C are diagrams (part 1) illustrating a process for manufacturing a semiconductor device according to a fourth embodiment of the present invention;
29 (D) to (F) are views (No. 2) showing the steps of manufacturing the semiconductor device according to the fourth embodiment of the present invention.
FIGS. 30 (G) to (I) are views (No. 3) showing the steps of manufacturing the semiconductor device according to the fourth embodiment of the present invention.
FIG. 31 is a plan view of a semiconductor device in which a dummy region is formed according to a fourth embodiment of the present invention.
FIG. 32 is a sectional view of a semiconductor device in which a dummy region is formed according to a fifth embodiment of the present invention.
FIG. 33 is a sectional view of a dummy region according to a fifth embodiment of the present invention.
FIGS. 34A to 34C are diagrams (part 1) illustrating the steps of manufacturing the semiconductor device according to the fifth embodiment of the present invention;
FIGS. 35 (D) to (F) are views (No. 2) showing the steps of manufacturing the semiconductor device according to the fifth embodiment of the present invention.
FIG. 36 (G) is a view (No. 3) showing a step of manufacturing the semiconductor device according to the fifth embodiment of the present invention;
[Explanation of symbols]
1 semiconductor substrate
2,4,9 ', 16' silicon oxide film
3 Silicon nitride film
5 P well
6 N-well
7 Gate oxide film
8 Gate electrode
9 Side wall
10 CoSi₂layer
13b Dummy area
14 polysilicon cover
15, 16, 21 protective layer
17 Device area
18,19,20 resist pattern
A1, A2, B1, B2 groove
A well boundary
W1, W2, W3, W3 'width
De device area
Du dummy area
101 semiconductor substrate
102,104 silicon oxide film
103 silicon nitride film
105 P well
106 N-well
107 Gate oxide film
108 Gate electrode
109 Sidewall
110 CoSi₂layer
111 dishing
112 erosion
113, 113a, 113b Dummy area
117 Device area

Claims (10)

In a semiconductor device including an element region and an element isolation region formed on a semiconductor substrate,
The device region has a device region in which a device is formed, and a device dummy region provided for adjusting an area ratio between the device region and the device isolation region,
A semiconductor device, wherein a cap layer for preventing the device dummy region from being silicided is formed on the device dummy region. The semiconductor device according to claim 1, wherein the cap layer includes an insulating film. 3. The semiconductor device according to claim 1, wherein the device dummy region includes a well boundary between a P well region and an N well region, and the cap layer is formed on the well boundary. 4. The semiconductor device according to claim 2, wherein said insulating film is formed on a surface of said semiconductor substrate. 5. The semiconductor device according to claim 4, wherein a dielectric film is further formed on said insulating film. 6. The semiconductor device according to claim 5, wherein another insulating film is further formed so as to cover said dielectric film. An element region and an element isolation region are provided on a semiconductor substrate. The element region includes a device region in which an element is formed, and a device dummy region for adjusting an area ratio between the element region and the element isolation region. A method for manufacturing a semiconductor device comprising:
Forming an element in the device region;
Forming a cap layer in the device dummy region;
Silicidizing the device region,
The method of manufacturing a semiconductor device, wherein the cap layer includes an insulating layer and prevents the device dummy region from being silicided. Performing the step of forming a cap layer in the device dummy region together with the step of forming an element in the device region, wherein the element has a gate insulating film, and the insulating film and the gate insulating film are simultaneously formed. The method for manufacturing a semiconductor device according to claim 7, wherein: The device has a gate electrode film on the gate insulating film, and the cap layer has a dielectric film on the insulating film,
9. The method according to claim 8, wherein the gate electrode film and the dielectric film are simultaneously formed. The device has a gate insulating film, a gate electrode film over the gate insulating film, and a sidewall film covering the gate electrode film, wherein the sidewall film and the insulating film are simultaneously formed. The method of manufacturing a semiconductor device according to claim 7.

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