KR100432788B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention relates to a method for fabricating a semiconductor device, wherein a source / drain region is formed on a silicon on insulator (SOI) substrate smaller than the width of a contact hole in which a subsequent metal plug is buried, and the trench sidewalls are exposed when the contact hole is formed. By forming a metal salicide layer on the sidewalls of the trench, the semiconductor can minimize the increase of junction leakage current in the source / drain regions, increase the degree of integration of the semiconductor device, and reduce the contact resistance to improve the reliability of the semiconductor device. A method of manufacturing a device is disclosed.

Description

Method for manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the semiconductor device can be manufactured to improve the reliability of the semiconductor device by increasing the integration of the semiconductor device by preventing an increase in the junction leakage current due to the reduction of the source / drain region. It is about a method.

In recent years, as semiconductor devices have been highly integrated, the length of the gate electrode and the depth of the source / drain regions have decreased. However, in addition to the high integration of semiconductor devices, the contact area should be reduced. However, current lithography techniques have limitations, which pose a great problem for the integration of semiconductor devices. Therefore, in order to solve the problem of increase of the junction leakage current according to the decrease of the source / drain region, and to secure the contact region and the contact resistance, a new method of manufacturing a semiconductor device using a silicon on insulator (SOI) wafer should be proposed. It is true.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, and prevents an increase in the junction leakage current due to the reduction of the source / drain regions, thereby increasing the integration of the semiconductor device and improving the reliability of the semiconductor device. The purpose is to.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

102: SOI substrate

104: device isolation film

106: gate oxide film

108: polysilicon layer

110a: NMOS gate electrode

110b: PMOS gate electrode

112: spacer

114a: N-type low concentration junction region

114b: P type low concentration junction region

116a: N-type high concentration junction region

116b: P-type high concentration junction region

118a: NMOS source / drain region

118b: PMOS source / drain area

120: first metal salicide layer

122: interlayer insulating film

124: contact hole

126: barrier metal layer

128: second metal salicide layer

130: metal plug

132: metal wiring

In the present invention, forming a trench in an SOI substrate, forming a device isolation layer by filling the trench, forming a gate electrode on the active region, and forming a source / drain region in the active region And depositing a metal material over the entire structure, and then performing a heat treatment process to form a first metal salicide layer, forming an interlayer insulating film over the entire structure, and forming the interlayer insulating film on the source / drain region. Performing an etching process to expose the first metal salicide layer and sidewalls of the trench to etch the interlayer insulating layer and the device isolation layer to form a contact hole, and a lower layer on the entire structure of the metal material Forming a barrier metal layer, and performing a heat treatment process on the upper part of the entire structure, so that a second sidewall of the trench is exposed. A method of manufacturing a semiconductor device includes forming a metal salicide layer, forming a metal plug to fill the contact hole, and forming a metal wiring on the entire structure.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. In the drawings, the same reference numerals refer to the same elements, and descriptions of overlapping elements will be omitted.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention, and are cross-sectional views of a complementary metal-oxide-semiconductor (CMOS) device.

Referring to FIG. 1, defining an SOI substrate 102 as an NMOS region and a PMOS region, which is made of an SOI substrate 102, for example, silicon 102a / silicon oxide film SiO ₂ 102b / silicon 102c. In order to form the device isolation film 104. In this case, the device isolation layer 104 may be formed using any one of a LOCOS (Poly Oxidation of Silicon) method, a poly-buffered LOCOS (PBL) method, and a shallow trench isolation (STI) method. It is preferable to form by STI method in consideration of the following process convenience.

Meanwhile, the STI method sequentially deposits a pad oxide film and a pad nitride film, which are not shown on the SOI substrate 102, and then sequentially performs a photolithography process and an etching process to perform a trench. Form. Then, a high-density plasma (HDP) oxide film (not shown) having excellent gap fill characteristics is buried in the trenches using chemical vapor deposition (hereinafter, referred to as 'CVD'). By deposition. Then, the high-density plasma oxide film is polished to fill the trench through chemical mechanical polishing (hereinafter, referred to as 'CMP') to form the device isolation film 104.

Then, NMOS region 'p ^-' impurity boron (Boron) injection to P- well (P-Well; not shown), ^a-implanting phosphorus (Phosphorous), the impurity is formed, and the N, PMOS area 'n' Form a well (N-Well) (not shown).

Referring to FIG. 2, the gate oxide film 106 is formed on the entire structure, and then the polysilicon layer 108 for the gate electrode is formed thereon. Then, an etching process using a mask for a gate electrode pattern is performed to sequentially pattern the polysilicon layer 108 and the gate oxide film 106 to form an NMOS gate electrode 110a in the NMOS region, and a PMOS gate in the PMOS region. The electrode 110b is formed.

Subsequently, an CVD process is performed on the entire structure to deposit an insulating film (not shown), and then an entire surface etching process such as etching back is performed to LDD on sidewalls of the NMOS gate electrode 110a and the PMOS gate electrode 110b. (Lightly Doped Drain) A spacer 112 for a high temperature low pressure dielectric (HLD) is formed.

Then, after the NMOS region, a photoresist pattern (not shown) to open (Open) formed only in the PMOS region, a photoresist agent for using pattern 'n ^-' of the exemplary ion implantation process (Ion implant) NMOS regions P An N-type low concentration junction 114a, which is a shallow junction, is formed in the well. Then, after a photoresist pattern (not shown), the PMOS region are open only NMOS forming region, a photoresist pattern using a bit 'p ^-' shallow junction regions in the N- well of the PMOS region by conducting an ion implantation process A P-type low concentration junction region 114b is formed.

Subsequently, a photoresist pattern (not shown) is formed only in the PMOS region to open the NMOS region, and then a 'n ⁺ ' ion implantation process using the photoresist pattern is performed to deeply bond to the P-well of the NMOS region. N-type high concentration junction region 116a, which is a depth junction), is formed. Then, a photoresist pattern (not shown) is formed only in the NMOS region so that the PMOS region is opened, and then a 'p ⁺ ' ion implantation process using the photoresist pattern is performed to deeply bond to the N-well of the PMOS region. P-type high concentration junction region 116b is formed.

By performing a plurality of ion implantation processes described above, an NMOS source / drain region 118a of an LDD structure including an N-type low concentration junction region 114a and an N-type high concentration junction region 116a is formed in the P-well of the NMOS region. In the N-well of the PMOS region, an LDD structure PMOS source / drain region 118b including a P-type low concentration junction region 114b and a P-type high concentration junction region 116b is formed. Meanwhile, the NMOS source / drain region 118a and the PMOS source / drain region 118b may be formed smaller than the width of a subsequent contact hole (see '124' in FIG. 5). Thereby, it is possible to raise the integration degree of a semiconductor element.

Referring to FIG. 3, a metal layer (not shown) is deposited with nickel or cobalt metal to form a first metal salicide layer 120 on the entire structure. In addition, in order to protect the metal layer, the capping layer is preferably formed of cobalt, nickel, titanium (Ti) or titanium nitride (TiN) on the metal layer.

Subsequently, the first metal salicide layer 120 is formed by performing a heat treatment process on the entire structure by a rapid temperature process (RTP) method. In this case, the first metal salicide layer 120 is formed on the source / drain regions 118a and 118b of the NMOS region and the PMOS region and the gate electrodes 110a and 110b.

On the other hand, the process for forming the first metal salicide layer 120 according to the metal material of the metal layer shows a slight difference in the characteristics of the metal material. For example, when nickel metal is used as the metal material of the metal layer, the first metal salicide layer 120 is formed by removing the unreacted nickel metal by performing a heat treatment process using a single RTP method and then performing a wet etching process. It is preferable. On the other hand, in the case of using cobalt metal as the metal material of the metal layer, the heat treatment process is performed by the primary RTP method, the wet etching process is performed to remove the unreacted cobalt metal, and then the heat treatment process is performed by the secondary RTP method. It is preferable to form a metal salicide layer 120.

Referring to FIG. 4, a spin on glass (SOG), un-doped silicate glass (USG), boron-phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), or plasma enhanced tetra ethyl ortho silicate (PETOS) is formed on an entire structure. Glass is formed using an CVD method to form an interlayer dielectric (ILD 122).

Next, the planarization process using the CVD method is performed on the interlayer insulating film 122 to planarize the entire structure. On the other hand, when the interlayer insulating film 128 is formed by spin coating, it is preferable to perform a flat etching process by performing a dry etch back process instead of the CMP method.

Referring to FIG. 5, after the photoresist is coated on the entire structure, an exposure process and a development process using a photo mask are performed to have a profile of the contact hole 124. A photoresist pattern (not shown) is formed.

Subsequently, an etch process using the photoresist pattern as an etching mask is performed to etch the interlayer insulating layer 122 to expose the NMOS source / drain region 118a of the NMOS region and the PMOS source / drain region 118b of the PMOS region. . In this case, it is preferable to etch a portion of the upper portion of the isolation layer 104 so that the sidewall of the trench (ie, the SOI substrate) is exposed by adjusting the etching process.

Referring to FIG. 6, the SOI substrate 102 and the subsequent metal plug (see '130' of FIG. 8) formed to bury the contact hole 124 on the inner surface of the contact hole 124 and the interlayer insulating film 122. Titanium and titanium nitride films are sequentially deposited to form a barrier mat layer 126 of a stacked structure in order to prevent junction sparking from occurring at the junction surface by reaction between the layers). In this case, cobalt or nickel may be used instead of titanium as the lower layer of the barrier metal layer 126, and may be formed by an ion metal plasma (IMP) sputtering method. In particular, titanium may be formed by a plasma enhanced CVD (PECVD) method, and TiCl ₄ and H ₂ gas may be used as the deposition gas.

Referring to FIG. 7, the second metal salicide layer 128 is formed on the sidewalls of the trench as shown in the 'A' region by performing a heat treatment process on the entire structure by the RTP method. At this time, the heat treatment step is carried out in the temperature range of 600 to 700 ℃, if the lower layer of the barrier metal layer 126 is formed of titanium, in the temperature range of 550 to 700 ℃, cobalt, In that case, it is preferable to carry out at 400-600 degreeC.

Referring to FIG. 8, after depositing tungsten (W), aluminum (Al), or copper (Cu) metal on the entire structure, an etching process is performed such that the barrier metal layer 126 on the interlayer insulating layer 122 is exposed by an etch back method. The metal plug 130 is formed to fill the contact hole 124.

Subsequently, tungsten (W), aluminum (Al) or copper (Cu) metal is deposited on the entire structure to form a metal wiring 132. Since the process is the same as the prior art, it will be omitted here for the convenience of description.

Although the technical spirit of the present invention described above has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the present invention, an increase in junction leakage current in the source / drain regions is formed by forming a source / drain region smaller than the width of a contact hole in which a subsequent metal plug is buried on a silicon on insulator (SOI) substrate. Minimize and increase the integration degree of the semiconductor device.

In addition, in the present invention, the trench sidewalls are exposed when the contact hole is formed, and then a metal salicide layer is formed on the portion, whereby the contact resistance can be reduced to improve the reliability of the semiconductor device.

Claims (8)

(a) forming a trench in the SOI substrate; (b) filling the trench to form an isolation layer; (c) forming a gate electrode on the active region; (d) forming a source / drain region in the active region; (e) depositing a metal material on the entire structure, and then performing a heat treatment process to form a first metal salicide layer; (f) forming an interlayer insulating film over the entire structure; (g) etching the interlayer insulating layer and the device isolation layer to form a contact hole by performing an etching process to expose the first metal salicide layer on the source / drain region and sidewalls of the trench; (h) forming a barrier metal layer formed of a metal material on a lower layer over the entire structure; (i) performing a heat treatment process on the entire structure to form a second metal salicide layer on sidewalls of the trench exposed in step (g); (j) forming a metal plug to fill the contact hole; And (k) forming a metal wiring on the entire structure. The method of claim 1, The source / drain area may be formed to be smaller than the width of the contact hole. The method of claim 1, The metal material is a method of manufacturing a semiconductor device, characterized in that the titanium, cobalt or nickel metal. The method of claim 1, The lower layer is a method of manufacturing a semiconductor device, characterized in that titanium, cobalt or nickel metal. The method of claim 1, The lower layer is a semiconductor device manufacturing method, characterized in that formed by IMP sputtering method or PECVD method. The method of claim 1, When the lower layer is formed of titanium, a method of manufacturing a semiconductor device, characterized in that formed by PECVD method using TiCl ₄ and H ₂ gas. The method of claim 1, The barrier layer is a semiconductor device manufacturing method, characterized in that the upper layer is a titanium nitride film. The method of claim 1, wherein the heat treatment step, When the lower layer is titanium, it is carried out at a temperature of 600 to 700 ℃, When the lower layer is cobalt, it is carried out at a temperature of 550 to 700 ℃, When the lower layer is nickel, the manufacturing method of the semiconductor device, characterized in that carried out at a temperature of 400 to 600 ℃.