KR100674645B1 - Method of manufacturing semiconductor devices - Google Patents
Method of manufacturing semiconductor devices Download PDFInfo
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- KR100674645B1 KR100674645B1 KR1020020009913A KR20020009913A KR100674645B1 KR 100674645 B1 KR100674645 B1 KR 100674645B1 KR 1020020009913 A KR1020020009913 A KR 1020020009913A KR 20020009913 A KR20020009913 A KR 20020009913A KR 100674645 B1 KR100674645 B1 KR 100674645B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 150000004767 nitrides Chemical class 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- Ceramic Engineering (AREA)
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Abstract
본 발명은 SOI 반도체 기판을 이용한 반도체 소자 제조 방법에 관한 것이다. 본 발명의 반도체 제조 방법은 SOI(Silicon On Isolation) 반도체 기판에 게이트 산화막과 폴리 실리콘 및 살리사이드 방지막을 증착하고, 패터닝하여 게이트 전극을 형성한다. LDD 확산층을 형성하기 위해 이온 주입하고, 질화막을 증착하여 스페이서 절연막을 형성한다. 스페이서가 형성된 반도체 기판 위에 확산층 형성을 위한 이온 주입하고, 이를 열처리 공정을 실시한다. 트랜지스터 절연을 위한 트랜치 절연막을 형성하고, 샐리사이드를 형성한다. 이어서 절연막을 증착, 평탄화하고, 금속 배선을 형성한다. 따라서 본 발명에 의하면, SOI 웨이퍼를 이용하여 확산층과 트랜치 측벽에 살리사이드 형성이 가능하고, 이를 통해 확산층 저항을 낮출 수 있어 확산층 배선이 가능하므로 고집적 소자 제조가 가능하다.The present invention relates to a semiconductor device manufacturing method using an SOI semiconductor substrate. In the semiconductor manufacturing method of the present invention, a gate oxide layer, a polysilicon layer, and a salicide barrier layer are deposited on a silicon on isolation (SOI) semiconductor substrate and patterned to form a gate electrode. Ion implantation is performed to form an LDD diffusion layer, and a nitride film is deposited to form a spacer insulating film. Ion implantation for forming a diffusion layer is formed on the semiconductor substrate on which the spacer is formed, and a heat treatment process is performed. A trench insulating film for transistor insulation is formed, and salicide is formed. Subsequently, an insulating film is deposited and planarized to form a metal wiring. Therefore, according to the present invention, salicide may be formed on the diffusion layer and the trench sidewalls using the SOI wafer, and thus the diffusion layer resistance may be lowered, thereby enabling the diffusion layer wiring to be manufactured.
SOI 반도체 기판, 살리사이드, 확산층 저항, 확산층 배선SOI semiconductor substrate, salicide, diffusion layer resistor, diffusion layer wiring
Description
도 1 내지 도 5는 본 발명에 따른 트랜지스터 제조 공정 수순을 나타내는 단면도들이다.1 to 5 are cross-sectional views showing a transistor manufacturing process procedure according to the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
2 : SOI 기판 4 : 활성층2: SOI substrate 4: active layer
6 : 게이트 산화막 8 : 스페이서 절연막6
10 : 게이트 전극 12 : 금속층10
14 : 샐리사이드막 16 : 절연막14
본 발명은 반도체 제조 방법에 관한 것으로, 좀 더 구체적으로는 SOI 웨이퍼를 이용한 고집적 반도체 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor, and more particularly, to a method for manufacturing a highly integrated semiconductor transistor using an SOI wafer.
고집적화라는 관점에서 반도체 소자의 집적도를 높이기 위해서는 개별 소자의 크기를 축소하는 것이 절대적으로 필요하지만, 동시에 소자와 소자 사이에 존재하는 절연(isolation) 영역의 폭을 전기적으로 허용하는 범위 내에서 축소하는 것도 필요하다. 칩 사이즈를 결정하는 중요한 기술로서 절연 공정 개발에 많은 노력 을 기울이는 이유가 여기에 있다.In order to increase the integration of semiconductor devices from the viewpoint of high integration, it is absolutely necessary to reduce the size of individual devices, but at the same time, it is also possible to reduce the width of the isolation region existing between the devices and the devices within an electrically acceptable range. need. This is the reason why a lot of effort is put into the development of the isolation process as an important technique for determining chip size.
반도체 소자가 고집적화되어 게이트 길이가 0.15 ㎛ 이하로 줄어들게 됨에 따라 소자의 채널 저항이 줄어들게 되었다. 따라서 상대적으로 기생 저항 성분의 기여도가 켜져 그 중요도가 커짐에 따라, 고속도를 요하는 로직 소자에서는 게이트와 확산층의 저항과 접촉 저항을 낮추기 위한 살리사이드 기술이 필수적이다.As the semiconductor devices are highly integrated and the gate length is reduced to 0.15 μm or less, the channel resistance of the devices is reduced. Therefore, as the contribution of parasitic resistance components becomes relatively important, the salicide technique for lowering the resistance and contact resistance of the gate and the diffusion layer is essential in logic devices requiring high speed.
또한 소자 집적화가 증가될수록 확산층을 이용한 배선이 늘고 있어 게이트 뿐만 아니라, 확산층의 저항 감소가 크게 대두되고 있는 실정이다. 그러나 게이트 길이의 감소로 인하여 확산층은 점점 얕아지고 그에 따라 살리사이드의 두께도 점점 감소하여 확산층이 점점 더 켜지는 문제점이 발생된다.In addition, as the integration of devices increases, wiring using the diffusion layer is increasing, so that the resistance of the diffusion layer as well as the gate is increasing. However, due to the decrease in the gate length, the diffusion layer becomes shallower, and the thickness of the salicide decreases gradually, resulting in a problem that the diffusion layer is turned on more and more.
본 발명의 목적은 상술한 문제점을 해결하기 위한 것으로, SOI 웨이퍼를 이용한 고집적 반도체 트랜지스터 제조 방법을 구현하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to implement a method for manufacturing a highly integrated semiconductor transistor using an SOI wafer.
이를 위해 SOI 웨이퍼의 특징을 최대한 활용하도록 트랜지스터 절연을 위한 트렌치 절연막 형성을 소오스/드레인 접합층 형성 후, 트랜치 측벽에 살리사이드를 형성하므로서 접합층의 저항을 감소시킨다. 이는 트랜치 하부가 산화물로 구비되기 때문에 그 부분에서는 샐리사이드가 형성되지 않고, 측벽에만 샐리사이드가 형성된다.To this end, in order to make the most of the characteristics of the SOI wafer, the trench insulating layer for transistor isolation is formed after the source / drain junction layer is formed, thereby forming salicide on the trench sidewalls, thereby reducing the resistance of the junction layer. Since the bottom portion of the trench is formed of an oxide, salicide is not formed at the portion thereof, and salicide is formed only at the sidewall.
상술한 목적을 달성하기 위한 본 발명에 의한 반도체 제조 방법은
SOI(Silicon On Isolation) 기판의 활성층에 게이트 산화막과 폴리 실리콘을 증착하고, 패터닝하여 게이트 전극을 형성하는 단계와; 상기 게이트 전극이 형성된 활성층에 LDD 확산층을 형성하기 위해 이온 주입하는 단계와; 상기 게이트 전극의 측면에 스페이서 절연막을 형성하는 단계와; 상기 스페이서 절연막이 형성된 활성층에 확산층 형성을 위한 이온을 주입하고, 이를 열처리하는 단계와;
상기 열처리된 활성층을 식각 및 분리하여 트랜지스터 절연을 위한 트랜치를 형성하는 단계와; 상기 트랜치가 형성된 활성층에 샐리사이드막을 형성하는 단계와; 상기 샐리사이드막이 형성된 활성층에 절연막을 증착하고, 이를 평탄화하는 단계 및; 상기 평탄화된 활성층에 금속 배선을 증착하는 단계를 포함한다.The semiconductor manufacturing method according to the present invention for achieving the above object is
Depositing and patterning a gate oxide film and polysilicon on an active layer of a silicon on isolation (SOI) substrate to form a gate electrode; Ion implantation to form an LDD diffusion layer in the active layer on which the gate electrode is formed; Forming a spacer insulating film on a side of the gate electrode; Implanting ions for forming a diffusion layer into an active layer on which the spacer insulating film is formed and heat-treating them;
Etching and separating the heat treated active layer to form a trench for transistor isolation; Forming a salicide layer on the trench in which the trench is formed; Depositing an insulating film on the active layer on which the salicide film is formed and planarizing the insulating film; Depositing a metal line on the planarized active layer.
또한, 상기한 샐리사이드막은 질화막 또는 산화막으로 형성한다.The salicide film is formed of a nitride film or an oxide film.
그리고 상기 샐리사이드를 형성하는 단계는 상기 트랜치가 형성된 활성층에 샐리사이드 형성을 위한 금속층을 증착하는 단계와, 상기 금속층이 증착된 활성층을 열처리하는 단계 및, 상기 열처리된 활성층에 상기 금속층의 미반응 금속 물질을 제거하기 위한 선택적으로 습식각하는 단계를 포함한다.
이 때, 상기 금속층은 코발트, 티타늄 또는 니켈을 100 ~ 500 Å 두께로 형성하고, 상기 상기 선택적으로 습식각하는 단계는 H2SO4와 H2O2의 혼합비가 4 : 1 인 혼합액으로 상기 미반응 금속 물질을 선택적으로 제거한다.The forming of the salicide may include depositing a metal layer for forming salicide on the trench formed active layer, heat treating the active layer on which the metal layer is deposited, and unreacted metal of the metal layer on the heat treated active layer. Optionally wet etching to remove the material.
At this time, the metal layer is formed of cobalt, titanium or nickel in a thickness of 100 ~ 500 Å, and the step of selectively wet etching is a mixture of H 2 SO 4 and H 2 O 2 is a mixture of 4: 1 The reactive metal material is selectively removed.
또한 상기 샐리사이드막이 형성된 활성층에 증착하는 절연막은 고밀도 플라즈마 산화막으로 형성한다.The insulating film deposited on the active layer on which the salicide film is formed is formed of a high density plasma oxide film.
따라서 본 발명에 의하면, SOI 웨이퍼를 이용하여 확산층과 트랜치 측벽에 샐리사이드막 형성이 가능하고, 이를 통해 확산층 저항을 낮출 수 있어 확산층 배선이 가능하므로 고집적 소자 제조가 가능하다.Therefore, according to the present invention, a salicide layer may be formed on the diffusion layer and the trench sidewalls using the SOI wafer, and the diffusion layer resistance may be lowered through the diffusion layer wiring, thereby enabling the fabrication of highly integrated devices.
이하 본 발명의 실시예를 첨부된 도면에 의거하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 반도체 소자 제조 공정을 나타내는 단면도들이다. 이 제조 공정은 SOI 반도체 기판을 이용하여 고집적도의 트랜지스터를 제조한다.1 to 5 are cross-sectional views illustrating a semiconductor device manufacturing process according to the present invention. This manufacturing process uses a SOI semiconductor substrate to produce a high density transistor.
도 1 내지 도 5를 참조하면, SOI(Silicon On Insulator)는 실리콘 웨이퍼 내부에 산화막(도시 생략됨)을 형성시킨 후, 산화막 상의 실리콘에 트랜지스터를 형성하는 기술을 의미한다. SOI 공정 기술은 집적도와 동작 특성이 우수하여 차세대 칩 제조 기술로 유망한 기술이다. 또한 낮은 유전체와 구리 배선 기술을 사용하여 소비 전력이 작고 성능이 뛰어난 칩을 만들 수 있다.1 to 5, a silicon on insulator (SOI) refers to a technique of forming an oxide film (not shown) inside a silicon wafer and then forming a transistor in silicon on the oxide film. SOI process technology is promising as next-generation chip manufacturing technology because of its high density and operation characteristics. Low dielectric and copper wiring techniques can also be used to create low power and high performance chips.
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SOI(Silicon On Isolation) 기판(2)상의 활성층(4) 및 게이트 산화막(6)과 폴리 실리콘을 증착하고, 패터닝하여 게이트 전극(10)을 형성한다. 이어서 상기 게이트 전극이 형성된 활성층(4)에 LDD 확산층을 형성하기 위해 이온 주입한다.A
상기 이온 주입된 SOI 기판(2)에 질화막을 증착하고 에치백하여 게이트 전극(10)측면에 스페이서 절연막(8)을 형성한다.
그리고 상기 스페이서 절연막(8)이 형성된 활성층(4)에 확산층 형성을 위한 이온을 주입하고, 이를 열처리하고, 상기 열처리된 SOI 기판(2)에 트랜지스터 절연을 위한 활성층(4)을 선택적으로 식각하여 트랜치를 형성한다.A nitride film is deposited on the ion implanted
In addition, a trench is implanted by implanting ions for forming a diffusion layer into the
상기 트랜치가 형성된 SOI 기판(2)에 샐리사이드막(14)을 형성하기 위한 금속층(12)을 증착하고, 이를 열처리하며 상기 열 처리된 SOI 기판(2)에 상기 금속층(12)의 미반응 금속 물질을 제거하기 위한 선택적으로 습식각하여 샐리사이드막(14)을 형성한다. 이 때, 상기 금속층(12)은 코발트, 티타늄 또는 니켈을 100 ~ 500 Å 두께로 형성한다.
그리고 상기 상기 선택적으로 습식각하는 단계는 H2SO4와 H2O2의 혼합비가 4 : 1 인 혼합액으로 상기 미반응 금속 물질을 선택적으로 제거한다.
이어서 상기 샐리사이드막(14)이 형성된 SOI 기판(2)에 절연막(16)을 증착하여, 이를 평탄화하고, 금속배선(도시 생략됨)을 증착한다.
상기 샐리사이드막(14) 형성 후의 절연막(16)은 갭필 능력이 우수한 고밀도 플라즈마 산화막으로 형성하는 것이 적합하다.The
In the selective wet etching, the unreacted metal material is selectively removed by a mixture of H 2 SO 4 and H 2 O 2 in a ratio of 4: 1.
Subsequently, an
It is preferable to form the
삭제delete
그러므로 상술한 바와 같이, 본 발명의 반도체 소자 제조 방법은 SOI 웨이퍼를 이용하여 고집적도의 반도체 소자를 형성한다. Therefore, as described above, the semiconductor device manufacturing method of the present invention forms a highly integrated semiconductor device using an SOI wafer.
삭제delete
상술한 바와 같이, 본 발명은 반도체 소자 제조에 있어서, SOI 웨이퍼를 이용하여 확산층과 트랜치 측벽에 살리사이드 형성이 가능하고, 이를 통해 확산층 저항을 낮출 수 있어 확산층 배선이 가능하므로 고집적 소자 제조가 가능하다. 또한 SOI 웨이퍼에 의한 집적 소자 제조에 살리사이드 공정을 효과적으로 활용할 수 있으므로 경제성이 향상된다.
As described above, in the semiconductor device fabrication, salicide may be formed in the diffusion layer and the trench sidewalls using the SOI wafer, and the diffusion layer resistance may be lowered through the diffusion layer wiring, thereby enabling the fabrication of highly integrated devices. . In addition, the salicide process can be effectively utilized for fabricating integrated devices using SOI wafers, thereby improving economic efficiency.
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|---|---|---|---|---|
| KR19980085205A (en) * | 1997-05-28 | 1998-12-05 | 문정환 | Salicide manufacturing method of semiconductor device |
| KR19980083005A (en) * | 1997-05-10 | 1998-12-05 | 윤종용 | Morse transistor using salicide process and manufacturing method thereof |
| KR19990001016A (en) * | 1997-06-11 | 1999-01-15 | 윤종용 | Method of manufacturing transistor of semiconductor device |
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| KR20040003901A (en) * | 2002-07-04 | 2004-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR20040003900A (en) * | 2002-07-04 | 2004-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
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| KR19980083005A (en) * | 1997-05-10 | 1998-12-05 | 윤종용 | Morse transistor using salicide process and manufacturing method thereof |
| KR19980085205A (en) * | 1997-05-28 | 1998-12-05 | 문정환 | Salicide manufacturing method of semiconductor device |
| KR19990001016A (en) * | 1997-06-11 | 1999-01-15 | 윤종용 | Method of manufacturing transistor of semiconductor device |
| KR20010032840A (en) * | 1997-12-09 | 2001-04-25 | 밀러 럿셀 비 | Receiver with sigma-delta analog-to-digital converter |
| KR20040003901A (en) * | 2002-07-04 | 2004-01-13 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
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