KR20010065747A - Structure For Preventing The Short Of Semiconductor Device And Manufacturing Method Thereof - Google Patents
Structure For Preventing The Short Of Semiconductor Device And Manufacturing Method Thereof Download PDFInfo
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- KR20010065747A KR20010065747A KR1019990065685A KR19990065685A KR20010065747A KR 20010065747 A KR20010065747 A KR 20010065747A KR 1019990065685 A KR1019990065685 A KR 1019990065685A KR 19990065685 A KR19990065685 A KR 19990065685A KR 20010065747 A KR20010065747 A KR 20010065747A
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- layer
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- device isolation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 230000000873 masking effect Effects 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 22
- 230000002265 prevention Effects 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 2
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은, 게이트전극의 소오스/드레인과 메탈플러그를 연결하는 구조를 제조하는 방법에 관한 것으로서, 특히, 트랜지스터의 소오스/드레인영역의 양측 끝단부를 라운드 지게 형성하고, 살리사이드공정으로 소오스/드레인영역 상에 살리사이드층을 형성한 후, 후속공정에서 메탈플러그를 소오스/드레인영역에 연결하므로 메탈플러그와 웰영역과의 쇼트를 방지하여 소자의 특성을 향상하도록 하는 반도체소자의 쇼트 방지구조 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a structure for connecting a source / drain and a metal plug of a gate electrode. In particular, a source / drain region of both sides of a source / drain region of a transistor is formed to be rounded and a salicide process is performed. After the salicide layer is formed on the semiconductor device, the short prevention structure of the semiconductor device which prevents the short between the metal plug and the well region and improves the characteristics of the device because the metal plug is connected to the source / drain regions in a subsequent process and fabrication thereof It is about a method.
일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 된다.In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. Will form.
최근에 반도체기판에 소자분리영역을 형성하기 위하여 반도체기판에 일정한 깊이를 갖는 트렌치(Trench)를 형성하고서 이 트렌치에 산화막을 증착키고서 화학기계적연마(Chemical Mechanical Polishing)공정으로 이 산화막의 불필요한 부분을 식각하므로 소자분리영역을 반도체기판에 형성시키는 STI(Shallow Trench Isolation)공정이 최근에 많이 이용되고 있다.Recently, in order to form a device isolation region in a semiconductor substrate, a trench having a constant depth is formed in the semiconductor substrate, and an oxide film is deposited on the trench, and a chemical mechanical polishing process is used to remove unnecessary portions of the oxide film. Since etching, a shallow trench isolation (STI) process for forming an isolation region on a semiconductor substrate has been widely used in recent years.
도 1은 종래의 반도체소자의 게이트와 메탈플러그를 연결하는 구조를 보인 도면으로서, 제조방법을 살펴 보도록 한다.1 is a view illustrating a structure in which a gate and a metal plug of a conventional semiconductor device are connected, and a manufacturing method thereof will be described.
도 1에 도시된 바와 같이, 반도체기판(1)에 STI(shallow trench isolation)소자분리공정으로 소자분리막(2)을 형성한 후, 소자분리막(2) 사이의 활성영역에 게이트산화막(3) 및 게이트전극층(4)을 순차적으로 적층하도록 한다.As shown in FIG. 1, after the device isolation film 2 is formed on the semiconductor substrate 1 by a shallow trench isolation (STI) device isolation process, the gate oxide film 3 and the active region between the device isolation films 2 are formed. The gate electrode layers 4 are sequentially stacked.
그리고, 상기 게이트산화막(3)과 게이트전극층(4)을 마스킹식각으로 게이트 (A)를 형성한 후, 이온을 주입하여 LDD이온주입영역(5)을 형성하고 게이트(B)의 양측면에 스페이서(6)를 형성하고, 재차 활성영역에 이온을 주입하여 소오스/드레인영역(7)을 형성하도록 한다.After the gate A is formed by masking etching the gate oxide layer 3 and the gate electrode layer 4, ions are implanted to form the LDD ion implantation region 5, and spacers are formed on both sides of the gate B. 6) and implanting ions into the active region again to form the source / drain regions 7.
그런 후에 상기 결과물 상에 층간절연막(8)을 적층한 후, 마스킹식각으로 소오스/드레인영역(7)으로 연결되는 콘택홀을 형성하고, 그 콘택홀 내에 금속층을 매립하여 식각하므로 메탈플러그(9)를 형성하도록 한다.Thereafter, after the interlayer insulating film 8 is laminated on the resultant, a contact hole connected to the source / drain region 7 is formed by masking etching, and a metal layer is embedded in the contact hole to be etched, thereby forming the metal plug 9. To form.
그러나, 도 1에서 도시된 바와같이, 반도체기판(1)에 형성된 소오스/드레인영역(7)의 졍션깊이가 일정하여 보덜리스 콘택(borderless contact)을 형성할 때, 공정상 포토 마스크 작업에서 약간의 미스얼라인(misalign)이 발생하는 경우, 졍션영역에서 누설전류가 발생되어 소자의 전기적인 특성이 나빠지는 문제점을 지닌다.However, as shown in FIG. 1, when the junction depth of the source / drain regions 7 formed in the semiconductor substrate 1 is constant to form borderless contact, there is a slight process photomask operation. In case of misalignment, leakage current is generated in the junction area, which causes a problem of deteriorating electrical characteristics of the device.
또한, 상기한 현상이 심한 경우에는, 도 1에서 "A" 로 표시된 바와 같이, 드레인영역(7)과 웰영역에 서로 쇼트(short)가 발생하여 소자의 작동 불량을 유발하는 심각한 문제를 초래하는 단점을 지닌다.In addition, in the case where the above phenomenon is severe, a short occurs between the drain region 7 and the well region, as indicated by " A " in FIG. 1, which causes a serious problem that causes malfunction of the device. Has disadvantages
본 발명은 이러한 점을 감안하여 안출한 것으로서, 소자분리막을 일정한 단차를 갖도록 식각한 후, 게이트의 양측면부에 이온을 주입하여 소오스/드레인영역의 양측 끝단부를 라운드지게 형성하고, 어닐링하고 살리사이드공정으로 소오스 /드레인영역 상에 살리사이드층을 형성한 후, 후속공정에서 메탈프러그를 소오스/드레인영역에 연결하므로 메탈플러그와 웰영역과의 쇼트를 방지하여 소자의 특성을 향상하는 것이 목적이다.The present invention has been made in view of this point, and the device isolation film is etched to have a constant step, and then ions are injected into both sides of the gate to form round ends of both ends of the source / drain regions, and annealing and salicide processes are performed. By forming a salicide layer on the source / drain region, a metal plug is connected to the source / drain region in a subsequent process, and thus, an object of the device may be improved by preventing a short between the metal plug and the well region.
도 1은 종래의 반도체소자의 게이트와 메탈플러그가 서로 연결되어진 구조를 보인 도면이고,1 is a view illustrating a structure in which a gate and a metal plug of a conventional semiconductor device are connected to each other.
도 2 내지 도 6은 본 발명의 반도체소자의 쇼트 방지구조를 순차적으로 형성하는 방법을 보인 도면이다.2 to 6 are views showing a method of sequentially forming a short prevention structure of a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 소자분리막10: semiconductor substrate 15: device isolation film
20 : 게이트산화막 25 : 게이트전극층20 gate oxide film 25 gate electrode layer
30 : LDD이온주입영역 35 : 스페이서30: LDD ion implantation area 35: spacer
40 : 라운드부 45 : 소오스/드레인영역40: round part 45: source / drain area
55 : 실리사이드층 60 : 층간절연막55 silicide layer 60 interlayer insulating film
70 : 메탈플러그70: metal plug
이러한 목적은 반도체기판에 STI공정으로 소자분리막을 형성하고 활성영역에 게이트산화막과 게이트전극층을 적층한 후, 패터닝하여 게이트를 형성하는 반도체소자 구조에 있어서, 상기 소자분리막을 일정 깊이의 단차를 갖도록 식각하여 반도체기판의 모서리 라운드부를 노출하고, 그 라운부에 까지 이온을 주입하여 양측단부가 절곡된 소오스/드레인영역을 형성하는 반도체소자의 쇼트 방지구조를 제공함으로써 달성된다.The purpose of the present invention is to form a device isolation film on a semiconductor substrate by an STI process, stack a gate oxide layer and a gate electrode layer on an active region, and then pattern the gate to form a gate. The semiconductor device is achieved by providing a short prevention structure of a semiconductor device in which a corner round portion of a semiconductor substrate is exposed and ions are implanted to the round portion to form a source / drain region having both ends bent.
그리고, 본 발명의 목적은, 반도체기판에 STI공정으로 소자분리막을 형성하고 활성영역에 게이트산화막과 게이트전극층을 적층한 후, 패터닝하여 게이트를 형성하는 단계와; 상기 단계 후에 상기 소자분리막을 식각하여 일정 깊이의 단차를 형성하는 단계와; 상기 단계 후에 상기 게이트의 양측면에 이온을 주입하여 상기 소자분리막의 모서리 라운드부까지 절곡되도록 소오스/드레인영역을 형성하는 단계와; 상기 단계 후에 상기 게이트전극층의 상부면과 상기 소오스/드레인영역의 상부면에 박막의 살리사이드층을 형성하는 단계와; 상기 단계 후에 상기 결과물 상에 층간절연막을 적층한 후, 마스킹 식각으로 콘택홀을 형성하여 상기 콘택홀 내에 금속층을 매립한 후 식각하여 메탈플러그를 형성하는 단계를 포함하여 이루어진 반도체소자의 쇼트 방지 구조 제조방법을 제공함으로써 달성된다.In addition, an object of the present invention is to form a device isolation film on a semiconductor substrate by an STI process, and to deposit a gate oxide film and a gate electrode layer in an active region, and then patterning the gate; Etching the device isolation layer after the step to form a step of a predetermined depth; Implanting ions into both sides of the gate after the step to form source / drain regions to be bent to the round corners of the device isolation layer; Forming a salicide layer of a thin film on an upper surface of the gate electrode layer and an upper surface of the source / drain region after the step; After forming the interlayer insulating layer on the resultant after the step, forming a contact hole by masking etching to fill a metal layer in the contact hole, and then etching to form a metal plug to manufacture a short-proof structure of a semiconductor device. By providing a method.
그리고, 상기 게이트의 스페이서로 질화막을 형성하는 것이 바람직 하다.In addition, it is preferable to form a nitride film with a spacer of the gate.
상기 소자분리막을 습식식각 혹은 건식식각으로 500 ∼ 1000Å의 두께로 식각하도록 한다.The device isolation film is etched by wet etching or dry etching to a thickness of 500 to 1000 Å.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2 내지 도 6은 본 발명의 반도체소자의 쇼트 방지구조를 순차적으로 형성하는 방법을 보인 도면이다.2 to 6 are views showing a method of sequentially forming a short prevention structure of a semiconductor device of the present invention.
우선 본 발명의 쇼트방지구조를 살펴 보면, 반도체기판(10)에 STI공정으로 소자분리막(15)을 형성하고 활성영역에 게이트산화막(20)과 게이트전극층(25)을 적층한 후 패터닝하여 게이트(B)를 형성하는 반도체소자 구조에 있어서, 상기 소자분리막(15)을 일정 깊이의 단차를 갖도록 식각하여 반도체기판의 모서리 라운드부 (40)를 노출하고, 그 라운부 부위까지 이온을 주입하여 양측단부가 절곡된 소오스/드레인영역(45)을 형성하도록 한다.First, in the short prevention structure of the present invention, the device isolation film 15 is formed on the semiconductor substrate 10 by the STI process, and the gate oxide layer 20 and the gate electrode layer 25 are stacked in the active region, and then patterned to form a gate ( In the semiconductor device structure forming B), the device isolation layer 15 is etched to have a predetermined depth to expose corner round portions 40 of the semiconductor substrate, and ions are injected to the round portions, thereby forming both side ends. Forms a bent source / drain region 45.
그리고, 본 발명의 반도체소자의 쇼트 방지 구조 제조방법을 살펴 보면, 도 2에 도시된 바와 같이, 반도체기판(10)에 STI공정으로 소자분리막(15)을 형성하고, 반도체기판(10)의 활성영역에 게이트산화막(20)과 게이트전극층(25)을 적층한 후, 마스킹식각으로 패터닝하여 게이트(B)를 형성하도록 한다.In addition, referring to FIG. 2, a method of manufacturing a short prevention structure of a semiconductor device according to an embodiment of the present invention forms an element isolation film 15 on the semiconductor substrate 10 by an STI process, and activates the semiconductor substrate 10. After the gate oxide layer 20 and the gate electrode layer 25 are stacked in the region, the gate B is formed by masking etching.
그리고, 상기 게이트(B)에 이온을 주입하여 LDD이온주입영역(30)을 형성한후, 게이트(B)의 양측면에 스페이서(35)를 형성하도록 한다.After the ion is implanted into the gate B to form the LDD ion implantation region 30, the spacers 35 are formed on both sides of the gate B. FIG.
도 3에 도시된 바와 같이, 상기 단계 후에 상기 소자분리막(15)을 식각하여 일정 깊이의 단차(a)를 형성하도록 한다.As shown in FIG. 3, after the step, the device isolation layer 15 is etched to form a step a of a predetermined depth.
그리고, 도 4에 도시된 바와 같이, 상기 단계 후에 상기 게이트(B)의 양측면에 이온을 주입하여 상기 소자분리막(15)의 모서리 라운드부(40)까지 절곡되도록 소오스/드레인영역(45)을 형성하도록 한다.As shown in FIG. 4, after the step, the source / drain region 45 is formed to be bent to the corner round portion 40 of the device isolation layer 15 by implanting ions into both sides of the gate B. Do it.
도 5에 도시된 바와 같이, 상기 단계 후에 상기 게이트전극층(25)의 상부면과 상기 소오스/드레인영역(45)의 상부면에 박막의 살리사이드층(55)을 형성한다,As shown in FIG. 5, after the step, a salicide layer 55 of a thin film is formed on an upper surface of the gate electrode layer 25 and an upper surface of the source / drain region 45.
이 때, 상기 살리사이드층(55)을 형성하기 전에 어닐링공정을 더 진행하는 것이 바람직 하다. 연속하여 상기 결과물상에 층간절연막(60)을 적층하도록 한다.At this time, it is preferable to further proceed the annealing process before forming the salicide layer (55). Successively, an interlayer insulating film 60 is laminated on the resultant product.
그리고, 도 6에 도시된 바와 같이, 상기 층간절연막(60)을 적층한 후, 마스킹 식각으로 콘택홀을 형성하여 상기 콘택홀의 내에 금속층을 매립하여 식각하여 메탈플러그(70)를 형성하도록 한다.As shown in FIG. 6, after the interlayer insulating layer 60 is stacked, a contact hole is formed by masking etching to embed and etch a metal layer in the contact hole to form a metal plug 70.
이 때, 상기한 도 6에 도시된 바와 같이, 메탈플러그(70)를 형성하면서 약간 우측으로 미스얼라인(misalign)이 발생하더라도 소오스/드레인영역(45)의 양측 끝단부위가 약간 절곡되어져 형성되므로 메탈플러그(70)가 웰영역과 접속되어서 발생하는 쇼트가 발생되어지지 않게 된다.In this case, as shown in FIG. 6, even when misalignment occurs slightly to the right while forming the metal plug 70, both end portions of the source / drain region 45 are slightly bent. The short generated by the metal plug 70 being connected to the well region is not generated.
상기한 바와 같이, 본 발명에 따른 반도체소자의 쇼트 방지구조 및 그 제조방법을 이용하게 되면, 반도체기판에 STI공정으로 소자분리막을 형성하고 활성영역에 게이트전극층을 적층하여 마스킹식각으로 게이트를 형성한 후, 소자분리막을 일정한 단차를 갖도록 식각한 후, 게이트의 양측 면부에 이온을 주입하여 소오스/드레인영역의 양측 끝단부를 라운드지게 형성하고, 살리사이드공정으로 소오스/드레인영역 상에 살리사이드층을 형성한 후, 후속공정에서 메탈플러그를 소오스/드레인영역에 연결하므로 메탈플러그와 웰영역과의 쇼트를 방지하여 소자의 특성을 향상하도록 하는 매우 유용하고 효과적인 발명이다.As described above, when the short prevention structure of the semiconductor device and the method of manufacturing the same according to the present invention are used, a device isolation film is formed on the semiconductor substrate by an STI process, and a gate electrode layer is laminated on the active region to form a gate by masking etching. After etching the device isolation layer to have a constant step, ions are implanted in both side surfaces of the gate to form round ends of the source / drain regions, and a salicide layer is formed on the source / drain regions by a salicide process. After that, the metal plug is connected to the source / drain regions in a subsequent process, thereby preventing the short between the metal plug and the well region, thereby improving the characteristics of the device.
Claims (5)
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6730971B2 (en) | 2001-12-18 | 2004-05-04 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| KR100432788B1 (en) * | 2002-07-04 | 2004-05-24 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR100466207B1 (en) * | 2002-07-04 | 2005-01-13 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
| KR100660327B1 (en) * | 2005-11-18 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Transistor of semiconductor device and method for forming the same |
| KR100720510B1 (en) * | 2005-11-18 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Transistor of semiconductor device and method for forming the same |
-
1999
- 1999-12-30 KR KR1019990065685A patent/KR20010065747A/en not_active Application Discontinuation
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6730971B2 (en) | 2001-12-18 | 2004-05-04 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| KR100454125B1 (en) * | 2001-12-18 | 2004-10-26 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| US7074683B2 (en) | 2001-12-18 | 2006-07-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of fabricating the same |
| KR100432788B1 (en) * | 2002-07-04 | 2004-05-24 | 주식회사 하이닉스반도체 | Method for manufacturing a semiconductor device |
| KR100466207B1 (en) * | 2002-07-04 | 2005-01-13 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
| KR100660327B1 (en) * | 2005-11-18 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Transistor of semiconductor device and method for forming the same |
| KR100720510B1 (en) * | 2005-11-18 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Transistor of semiconductor device and method for forming the same |
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