JP2003077936A - Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form in a self-aligned manner a connection hole connecting to a source and a drain of MISFET relative to a gate electrode regardless of the material of an insulation film covering the top and side wall of the gate electrode. SOLUTION: After a groove portion 15 encircling the periphery of a gate electrode 14 is formed on an interlayer dielectric 11, and the groove portion 15 is embedded by an etching stopper film 16 which is capable of obtaining a high dry etching selection ratio relative to the interlayer dielectric, the interlayer dielectric 11 is selectively and anisotoropically etched with a photoresist film 17 as a mask, thus the connection hole is formed that reaches a n-type semiconductor region 8 (source, drain) and a p-type semiconductor region 9 (source, drain).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device, and in particular,
MISFET (Metal Insulator Semiconductor Field)
The present invention relates to a technique effectively applied to a process of forming a connection hole connecting to a source and a drain of an effect transistor) in a self-aligned manner with respect to a gate electrode.

[0002]

2. Description of the Related Art In order to form contact holes for connecting to the source and drain of a MISFET in a self-aligned manner with respect to a gate electrode, there is, for example, the following Self-Aligned Contact (SAC) technique. After covering the upper portion and the side wall of the gate electrode with a silicon nitride film, a silicon oxide film to be an interlayer insulating film is formed on the semiconductor substrate. Next, the connection hole is formed by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film.

Regarding the above-mentioned SAC technique, for example, JP-A-11-26757 and JP-A-10-7949.
It is described in Japanese Patent No. 2 publication.

Japanese Unexamined Patent Publication No. 11-26757 discloses that a gate electrode is made of a metal material and a silicon nitride film is formed on the upper and side walls of the gate electrode. A technique for forming in self-alignment is disclosed.

Further, in Japanese Unexamined Patent Publication No. 10-79492, a silicon nitride film is formed on the upper and side walls of a gate electrode formed by laminating a tungsten film on a polycrystalline silicon film via a barrier metal film made of titanium nitride or tungsten nitride. And forming a contact hole for connecting to the source and drain in a self-aligned manner with respect to the gate electrode.

[0006]

However, the present inventors have found that the above self-aligned contact (SAC) technique has the following problems.

That is, when the connection hole is formed by the SAC technique, the connection hole is formed by etching the interlayer insulating film using the photoresist film patterned by the photolithography technique as a mask. Therefore, a margin for aligning the mask with the gate electrode is required. However, when the distance between the adjacent gate electrodes is narrowed for the purpose of high integration of the LSI, it becomes difficult to provide the alignment margin. That is, there is a problem that the miniaturization of the element is hindered.

Even when the above-mentioned alignment margin satisfies the conditions for forming a device of a desired standard, a relative error may occur in the alignment position of the mask between a plurality of semiconductor wafers. That is, there is a problem in that the distance between the gate electrode and the connection hole is different between the plurality of semiconductor wafers, so that the characteristics are varied among the plurality of LSIs.

Further, in the SAC technique described above, the connection hole is formed by utilizing the difference in etching rate between the insulating film covering the upper portion and the side wall of the gate electrode and the interlayer insulating film.
Therefore, the material of the insulating film that covers the upper portion and the side wall of the gate electrode is limited. Since there is a correlation between the characteristic of the MISFET and the characteristic peculiar to the insulating film, the dielectric constant may increase depending on the material of the insulating film. Further, according to the experiments conducted by the present inventors, in the p-channel type MISFET in particular, the drain current may decrease due to the stress acting on the source and drain regions depending on the characteristics peculiar to the insulating film. .
That is, the driving ability of the MISFET is reduced depending on the material of the insulating film that covers the upper portion and the side wall of the gate electrode, so that there is a problem that a MISFET having desired characteristics cannot be obtained in the process using the SAC technique.

An object of the present invention is to provide a technique for forming a connection hole connected to a source and a drain of a MISFET at a fixed position in a self-aligning manner with respect to a gate electrode regardless of the alignment margin of a mask for forming the connection hole. To provide.

Another object of the present invention is to provide a MIS regardless of the material of the insulating film covering the upper portion and the side wall of the gate electrode.
It is an object of the present invention to provide a technique of forming a connection hole connected to a source and a drain of an FET in a self-aligned manner with a gate electrode.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the present invention provides a first semiconductor device on a semiconductor substrate.
Forming an insulating film, forming a first groove in the first insulating film, and forming a first conductive film having a surface lower than that of the first insulating film in the first groove. A step of selectively and isotropically etching a part of the first insulating film to form a second groove portion adjacent to a side surface of the first conductive film; The step of forming a second insulating film having a large etching selection ratio in the second groove, and the first insulating film under the condition that the etching rate of the first insulating film is relatively larger than that of the second insulating film. And the step of forming the first hole portion in a self-aligned manner with respect to the second insulating film.

Further, according to the present invention, a step of forming a semiconductor region on the main surface of the semiconductor substrate, and a step of forming a first insulating film on the semiconductor substrate after the formation of the semiconductor region,
Forming a first groove in the first insulating film;
Embedding a first conductive film in the groove, and lowering the surface of the first conductive film in the first groove below the surface of the first insulating film, and then selecting a part of the first insulating film And isotropically etching to form a second groove portion adjacent to a side surface of the first conductive film, and a second insulating film having a large etching selection ratio with respect to the first insulating film is formed on the second insulating film. In the step of forming in the groove, and under the condition that the etching rate of the first insulating film is relatively higher than that of the second insulating film,
A step of forming a first hole reaching the semiconductor region in the first insulating film in a self-aligned manner with respect to the second insulating film.

Further, according to the present invention, a step of forming a semiconductor region on the main surface of the semiconductor substrate, a step of forming a dummy gate electrode on the main surface of the semiconductor substrate, and a step of forming a dummy gate electrode on the main surface of the semiconductor substrate. A step of forming a semiconductor region on the main surface of the semiconductor substrate, and a step of forming a second insulating film on the semiconductor substrate and on a sidewall of the dummy gate electrode after forming the dummy gate electrode and the semiconductor region. A step of forming a first insulating film on the second insulating film, and a step of chemically and mechanically polishing the first insulating film and the second insulating film to the height of the surface of the dummy gate electrode. Removing the dummy gate electrode and forming a first groove in the first insulating film, and filling the first groove with the first conductive film, and then removing the surface of the first conductive film from the first conductive film. First Self-alignment of the first insulating film with the second insulating film under the step of lowering the surface of the edge film and the condition that the etching rate of the first insulating film is relatively higher than that of the second insulating film. And a step of forming a first hole portion reaching the semiconductor region.

Further, the present invention comprises the steps of forming a semiconductor region on the main surface of the semiconductor substrate, forming a first conductive film on the semiconductor substrate, and then patterning the first conductive film. After forming the first conductive film on the semiconductor substrate,
Patterning the first conductive film, forming a semiconductor region on the main surface of the semiconductor substrate, and forming the semiconductor region on the semiconductor substrate after patterning the first conductive film and after forming the semiconductor region. Forming a first insulating film having a surface having the same height as the surface of the first conductive film; removing a part of the first conductive film, and making the surface lower than the surface of the first insulating film. After that, a step of selectively and isotropically etching a part of the first insulating film to form a second groove portion adjacent to a side surface of the first conductive film, and with respect to the first insulating film The step of forming a second insulating film having a large etching selection ratio in the second groove, and the first insulating film under the condition that the etching rate of the first insulating film is relatively larger than that of the second insulating film. The self-alignment with the second insulating film, It is intended to include a step of forming a first hole reaching the conductive region.

Further, according to the present invention, (a) a first insulating film formed on a semiconductor substrate, and (b) a first conductive film formed in the first insulating film and patterned into a predetermined shape. And (c) a second insulating film which is formed so as to surround the periphery of the first conductive film, is in contact with the side surface of the first conductive film, and has a large etching selection ratio with respect to the first insulating film,
(D) a first hole formed in the first insulating film in a self-aligned manner with the second insulating film; and (e) a plug formed in the first hole and in contact with the second insulating film. And have.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. In addition, hatching may be used even in a plan view for the sake of explanation.

(First Embodiment) A method for manufacturing a semiconductor integrated circuit device according to the first embodiment will be described below with reference to FIGS.

First, as shown in FIG. 1, the specific resistance is 10Ω.
The semiconductor substrate 1 made of single crystal silicon having a size of about
Heat treatment is performed at about 0 ° C. to form a thin silicon oxide film (pad oxide film) with a film thickness of about 10 nm on the main surface. Then, a silicon nitride film having a thickness of about 120 nm is deposited on the silicon oxide film by a CVD (Chemical Vapor Deposition) method, and then the silicon nitride film and the silicon oxide film in the element isolation region are dry-etched using the photoresist film as a mask. And are removed. The silicon oxide film is formed for the purpose of relieving stress applied to the substrate when the silicon oxide film embedded in the element isolation trench is densified (baked up) in a later step. In addition, since the silicon nitride film has a property of being hard to be oxidized, it is used as a mask for preventing the oxidation of the substrate surface below it (active region).

Then, the semiconductor substrate 1 in the element isolation region is formed to a depth of 3 by dry etching using a silicon nitride film as a mask.
After forming the groove of about 50 nm, in order to remove the damage layer generated on the inner wall of the groove by etching, the semiconductor substrate 1 is heat-treated at about 1000 ° C. to form a thin silicon oxide film of about 10 nm on the inner wall of the groove. Form.

Subsequently, after depositing the silicon oxide film 2 on the semiconductor substrate 1 by the CVD method, in order to improve the film quality of the silicon oxide film 2, the semiconductor substrate 1 is heat-treated to densify the silicon oxide film 2. (Bake down). After that, the silicon oxide film 2 is polished by a chemical mechanical polishing (CMP) method using a silicon nitride film as a stopper and left inside the groove, so that the element isolation groove 3 having a flat surface is formed. To form.

Next, after removing the silicon nitride film remaining on the active region of the semiconductor substrate 1 by wet etching using hot phosphoric acid, the n-channel MISF of the semiconductor substrate 1 is removed.
Impurity ions (for example, B (boron)) having a p-type conductivity type are ion-implanted into a region where ET is formed to form a p-type well 4. Then, impurity ions having an n-type conductivity (for example, P (phosphorus)) are ion-implanted into a region of the semiconductor substrate 1 where the p-channel type MISFET is to be formed, and n
A mold well 5 is formed.

Next, as shown in FIG. 2, the semiconductor substrate 1 is heat-treated to form a clean dummy gate oxide film 6 on the surfaces of the p-type well 4 and the n-type well 5.

Subsequently, a film thickness of 150 to 2 is formed on the semiconductor substrate 1.
A polycrystalline silicon film of about 00 nm is deposited by the CVD method. Then, using the photoresist film patterned by the photolithography technique as a mask, the polycrystalline silicon film is dry-etched. As a result, the dummy gate electrode 7 is formed on the dummy gate oxide film 6 on the p-type well 4 and on the dummy gate oxide film 6 on the n-type well 5.

Subsequently, P or As (arsenic) is ion-implanted into the p-type well 4 to form an n-type semiconductor region (source, drain) 8, and B is ion-implanted into the n-type well 5. A type semiconductor region (source, drain) 9 is formed.

Next, as shown in FIGS. 3 to 5, an interlayer insulating film (first insulating film) 11 is formed by depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, for example. 4 corresponds to the cross section taken along the line AA in FIG. 3, and FIG. 5 corresponds to the cross section taken along the line BB in FIG.
Further, in FIG. 3, an n-type semiconductor region (source, drain) 8 and a p-type semiconductor region (source, drain)
The area indicated by 9 is hatched. Subsequently, the interlayer insulating film 11 is polished by the CMP method until the surface of the dummy gate electrode 7 appears.

Next, as shown in FIGS. 6 to 8, the dummy gate electrode 7 is selectively removed by dry etching, for example. Next, the opening (first groove) 12 is formed by selectively removing the dummy gate oxide film 6 by dry etching, for example.

Next, as shown in FIGS. 9 to 11, the semiconductor substrate 1 is heat-treated to form a gate oxide film 13 at the bottom of the opening 12. Subsequently, as shown in FIGS. 12 and 13, a barrier conductor film 14A made of, for example, TiN (titanium nitride) is deposited on the semiconductor substrate 1 including the inside of the opening 12, and then, on the barrier conductor film 14. , W (tungsten) is deposited on the opening 12 by depositing a conductive film (first conductive film) 14B. Here, the TiN film which is the barrier conductor film 14A can be exemplified to be deposited by the sputtering method.
The W film of 4B can be exemplified to be deposited by the CVD method.

Next, as shown in FIGS. 14 to 16, the barrier conductor film 14 on the interlayer insulating film 11 is formed by, for example, the CMP method.
A and the conductive film 14B are removed, and the barrier conductor film 1 is removed.
4A and the conductive film 14B are left only in the opening 12.
Then, as shown in FIG. 17 and FIG.
By anisotropically etching the barrier conductor film 14A and the conductive film 14B in the inside, the height of the surface thereof is made lower than the height of the surface of the interlayer insulating film 11, and the gate electrode 1
4 is formed. At this time, the difference between the surface of the interlayer insulating film 11 and the surface of the gate electrode 14 is made equal to the distance between the gate electrode 14 and the source / drain connection hole formed in a later step. In the first embodiment, 1
An example of the thickness is about 00 nm. Through the steps up to this point, the n-channel type MISFET Qn and the p-channel type MISFET Qp can be formed.

Next, as shown in FIGS. 19 to 21, the interlayer insulating film 11 is selectively and isotropically etched by, for example, a wet etching method using a dilute hydrofluoric acid solution, and the surface of the interlayer insulating film 11 is etched. Is lowered to the height of the surface of the gate electrode 14. At this time, a groove portion (second groove portion) 15 is formed so as to surround the periphery of the gate electrode 14. Since the groove 15 is formed by isotropic etching,
The width and depth are determined by the height of the surface of the interlayer insulating film 11 and the gate electrode 14 after the previous step (see FIGS. 14 to 16).
Equal to the height of the surface of.

Next, as shown in FIGS. 22 and 23,
For example, an etching stopper film (second etching film) that can obtain a high dry etching selectivity with respect to the interlayer insulating film 11 is formed.
An insulating film 16 is deposited on the semiconductor substrate 1, and the groove 15 is filled with this etching stopper film 16. In the first embodiment, a silicon nitride film can be exemplified as the etching stopper film 16.

Next, as shown in FIGS. 24 to 26, the interlayer insulating film 11 and the gate electrode 1 are polished by polishing the etching stopper film 16 by CMP, for example.
The etching stopper film 16 on 4 is removed, and the etching stopper film 16 is left in the groove 15. Although the case where the etching stopper film 16 on the interlayer insulating film 11 and the gate electrode 14 is removed by the CMP method has been described in the first embodiment, the etchback method may be used.

Next, as shown in FIGS. 27 to 30, a photoresist film 17 patterned by photolithography is formed on the interlayer insulating film 11. This photoresist film 17 has an n-type semiconductor region 8 in a later step.
(Source, drain) and p-type semiconductor region (source,
Opening 1 for forming a connection hole reaching drain 9
Have eight. The planar shape of the opening 18 may be a slit type as shown in FIG. 27 or a rectangular shape as shown in FIG. 28, corresponding to the planar shape of the connection hole.

Next, as shown in FIGS. 31 to 34, the interlayer insulating film 11 is formed by using the photoresist film 17 as a mask.
Is selectively and anisotropically dry-etched to form a connection hole (first hole portion) 20 reaching the n-type semiconductor region 8 (source, drain) and the p-type semiconductor region (source, drain) 9. At this time, since the etching stopper film 16 embedded in the groove 15 has a high etching selection ratio with respect to the interlayer insulating film 11, the connection hole 2
It is possible to form 0 at a fixed position apart from the gate electrode 14 by the width of the groove portion 15. This eliminates the need to cover the gate electrode 14 with the photoresist film 17, so that the gate electrode 1 of the mask (photoresist film 17) is removed.
It is possible to omit the provision of the alignment margin for No. 4. That is, since the elements included in the semiconductor integrated circuit device according to the first embodiment can be miniaturized, the elements can be highly integrated.

Further, the connection hole 20 is formed in the gate electrode 14
Since the holes can be opened at a constant position separated by the width of the groove portion 15 from each other, the distance between the gate electrode 14 and the connection hole 20 can be constant even between the plurality of semiconductor substrates 1. As a result, it is possible to prevent variations in characteristics among the plurality of semiconductor integrated circuit devices of the first embodiment.

By the way, when the connection holes reaching the source and drain regions are formed by the SAC technique, an insulating film covering the upper and side walls of the gate electrode and an interlayer insulating film made of a material different from the insulating film are etched. The connecting hole is drilled by utilizing the rate difference. Therefore, the upper portion and the side wall of the gate electrode remain covered with the insulating film. On the other hand, in the first embodiment, the gate electrode 14
Is not covered with an insulating film made of a material different from that of the interlayer insulating film 11. Therefore, it is possible to prevent the driving ability of the n-channel type MISFET Qn and the p-channel type MISFET Qp from being lowered due to the characteristics of the insulating film. That is, according to the manufacturing process of the semiconductor integrated circuit device of the first embodiment, the n-channel MISF having desired characteristics is obtained.
It is possible to obtain ETQn and p-channel type MISFETQp.

Next, as shown in FIGS. 35 and 36,
For example, after depositing a barrier conductor film 21 made of titanium nitride on the semiconductor substrate 1 including the inside of the connection hole 20, a conductive film (second conductive film) 22 made of W is deposited on the barrier conductor film 21. , The connection hole 20 is embedded. The barrier conductor film 21 can be exemplified to be deposited by a sputtering method, and the conductive film 22 can be exemplified to be deposited by a CVD method.

Next, as shown in FIGS. 37 to 40, the barrier conductor film 21 and the conductive film 22 on the interlayer insulating film 11, the gate electrode 14 and the etching stopper film 16 are removed by CMP, for example, and the The plug 23 is formed by leaving the barrier conductor film 21 and the conductive film 22 inside the connection hole 20. 37 is a plan view of relevant parts corresponding to the case where the opening 18 of the photoresist film 17 has a slit shape in plan view (see FIG. 27), and FIG. 38 is a plan view of the photoresist film 17. FIG. 29 is a main-portion plan view corresponding to a case where the opening 18 has a rectangular planar shape (see FIG. 28).

Next, as shown in FIGS. 41 to 43, after an etching stopper film 25 made of, for example, a silicon nitride film is deposited on the semiconductor substrate 1, an interlayer made of a silicon oxide film is formed on the etching stopper film 25. Insulating film 26
Deposit. Then, a photoresist film (not shown) patterned by the photolithography technique is formed on the interlayer insulating film 26. Then, by using the photoresist film as a mask, the etching stopper film 25 and the interlayer insulating film 26 are dry-etched to form a connection hole 27 reaching the plug 23 and a connection hole 28 reaching the gate electrode.

Subsequently, for example, titanium nitride is deposited on the semiconductor substrate 1 including the insides of the connection holes 27 and 28 by the sputtering method, and then a W film is deposited on the titanium nitride film by the CVD method to form the connection holes. 27 and 28 are embedded. Then, the titanium nitride film and the W film on the interlayer insulating film 26 are removed by, for example, the CMP method, and the titanium nitride film and the W film are left inside the connection holes 27 and 28, whereby the plugs 30 and 3 are formed.
1 are formed respectively.

Next, as shown in FIGS. 44 and 45,
On the semiconductor substrate 1, for example, a titanium nitride film, an Al (aluminum) film and a titanium nitride film are sequentially deposited from the lower layer to form a laminated film. These titanium nitride film and Al
The film can be exemplified to be deposited by a sputtering method, for example. Subsequently, the first layer wiring 32 is formed by dry etching the laminated film using the photoresist film patterned by the photolithography technique as a mask.

Then, on the semiconductor substrate 1, for example, CV
After depositing the interlayer insulating film 33 made of a silicon oxide film by the D method, the second layer wiring 34 is formed by the same step as the step of forming the wiring 32, and the semiconductor integrated circuit device according to the first embodiment is obtained. To manufacture. Although the case where two wiring layers are formed has been described in the first embodiment,
The number of wiring layers is not limited to two and may be formed in multiple layers.

By the way, referring to FIGS. 44 and 45,
The case of forming the wiring (the first layer wiring 32 and the second layer wiring 34) using the Al film as the main conductive layer has been described.
A case of forming a wiring using u (copper) as a main conductive layer will be described with reference to FIGS. 46 and 47.

Plugs 30 and 31 (see FIGS. 41 to 43)
After the formation of the etching stopper film 33A made of, for example, a silicon nitride film, the insulating film 3 made of a silicon oxide film is formed on the etching stopper film 33A.
Deposit 3B. Subsequently, the insulating film 33B and the etching stopper film 33A are dry-etched using the photoresist film patterned by the photolithography technique as a mask to form the wiring groove 32A.

Next, after depositing a titanium nitride film on the semiconductor substrate 1 including the inside of the wiring groove 32A by, for example, a sputtering method, a Cu film is deposited on the titanium nitride film by a plating method and the Cu film is formed. The wiring groove 33A is filled with. Then, the excess titanium nitride film and the Cu film on the insulating film 33B are removed by polishing by, for example, the CMP method, and the titanium nitride film and the Cu film are left in the wiring groove 33A to form the first layer embedded wiring 32B. To do.

Next, on the semiconductor substrate 1, for example, an etching stopper film 33C made of a silicon nitride film, an insulating film 33D made of a silicon oxide film, an etching stopper film 33E made of a silicon nitride film, and an insulating film 33F made of a silicon oxide film. Are sequentially deposited from the lower layer. continue,
Using the photoresist film patterned by the photolithography technique as a mask, the insulating film 33F and the etching stopper film 33E are dry-etched to form the wiring groove 34A. Then, the second layer embedded wiring 34B is formed by the same step as the step of forming the first layer embedded wiring 32B, and the semiconductor integrated circuit device of the first embodiment is manufactured. In the first embodiment, the case where two layers of embedded wirings are formed has been described, but the number of embedded wirings is not limited to two layers, and more layers may be formed.

(Embodiment 2) In Embodiment 1, the gate electrode 14 (see FIGS. 14 to 16) is formed of TiN.
Barrier conductor film 14A made of W and conductive film 14 made of W
However, in the second embodiment, the gate electrode is formed by stacking the W film on the polycrystalline silicon film via the TiN film. A method of manufacturing the semiconductor integrated circuit device according to the second embodiment will be described in the order of steps with reference to FIGS. 48 to 83.

The method of manufacturing the semiconductor integrated circuit device according to the second embodiment is the same up to the step described with reference to FIG. 1 in the first embodiment.

Thereafter, as shown in FIG. 48, semiconductor substrate 1 is heat-treated to form a clean gate oxide film 6A on the surfaces of p type well 4 and n type well 5.

Subsequently, a film thickness of 150 to 2 is formed on the semiconductor substrate 1.
A polycrystalline silicon film 7A having a thickness of about 00 nm is deposited by the CVD method. Then, the polycrystalline silicon film 7A is patterned by dry etching using the photoresist film patterned by the photolithography technique as a mask.

Subsequently, P or As (arsenic) is ion-implanted into the p-type well 4 to form an n-type semiconductor region (source, drain) 8, and B is ion-implanted into the n-type well 5. A type semiconductor region (source, drain) 9 is formed.

Next, as shown in FIGS. 49 to 51, an interlayer insulating film 11 is formed by depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, for example. In addition,
50 corresponds to the cross section taken along the line AA in FIG. 49, and FIG. 51 corresponds to the cross section taken along the line BB in FIG. Further, in FIG. 49, an n-type semiconductor region (source, drain) 8 and a p-type semiconductor region (source, drain)
The area indicated by 9 is hatched. Then, the interlayer insulating film 11 is polished by the CMP method until the surface of the polycrystalline silicon film 7A appears.

Next, as shown in FIGS. 52 and 53,
The surface height of the polycrystalline silicon film 7A is made lower than that of the interlayer insulating film 11 by etching back the polycrystalline silicon film 7A. At this time, the difference between the surface of the interlayer insulating film 11 and the surface of the polycrystalline silicon film 7A is the same as the distance between the polycrystalline silicon film 7A and the source / drain connection hole formed in a later step. Thus, in the first embodiment, it can be exemplified that the thickness is about 100 nm.

Next, as shown in FIGS. 54 to 56, the interlayer insulating film 11 is selectively and isotropically etched by, for example, a wet etching method using a dilute hydrofluoric acid solution, and the surface of the interlayer insulating film 11 is etched. Is lowered to the height of the surface of the polycrystalline silicon film 7A. At this time, the trench 15 is formed so as to surround the polycrystalline silicon film 7A. Since the groove 15 is formed by isotropic etching,
The width and depth are equal to the difference between the height of the surface of interlayer insulating film 11 and the height of the surface of polycrystalline silicon film 7A after the previous step (see FIGS. 52 and 53).

Next, the etching stopper film 16 is deposited by the steps similar to those described with reference to FIGS. 22 and 23 in the first embodiment (FIGS. 57 and 58).
reference). 24 to 26 in the first embodiment.
The etching stopper film 16 on the interlayer insulating film 11 and the polycrystalline silicon film 7A is removed and the etching stopper film 16 is left in the groove portion 15 by the same process as that described with reference to FIGS. 59 to 61. .

Next, as shown in FIGS. 62 and 63,
By selectively etching back the polycrystalline silicon film 7A, the height of the surface thereof is lowered by about 50 nm to form an opening (third groove) 16A.

Then, a photoresist film 17 is formed by the same steps as those described with reference to FIGS. 27 to 30 in the first embodiment (see FIGS. 64 to 67). Also in the second embodiment, as in the case of the first embodiment, the planar shape of the opening 18 can be a slit type (see FIG. 64) or a rectangle (see FIG. 65).

Next, referring to FIG.
~ By the process similar to the process described using FIG. 34, n
A connection hole 20 reaching the type semiconductor region 8 (source, drain) and the p-type semiconductor region (source, drain) 9 is formed (see FIGS. 68 to 71). Also in the second embodiment, the etching stopper film 16 embedded in the groove 15 is formed.
Has a high etching selection ratio with respect to the interlayer insulating film 11, so that the connection hole 20 is formed from the gate electrode 14 to the groove portion 1.
It is possible to open holes at fixed positions separated by a width of 5.
This eliminates the need to cover the polycrystalline silicon film 7A with the photoresist film 17, so that it is possible to omit the provision of the alignment margin for the mask (photoresist film 17) with respect to the polycrystalline silicon film 7A. That is, since the elements included in the semiconductor integrated circuit device according to the second embodiment can be miniaturized, the elements can be highly integrated.

Also in the second embodiment, since the connection hole 20 can be opened at a fixed position apart from the polycrystalline silicon film 7A by the width of the groove portion 15, the polycrystalline silicon film can be formed between the plurality of semiconductor substrates 1. The distance between the membrane 7A and the connection hole 20 can be constant. As a result, it is possible to prevent variations in characteristics among a plurality of semiconductor integrated circuit devices according to the second embodiment.

Next, by the same steps as the steps described with reference to FIGS. 35 and 36 in the first embodiment,
A barrier conductor film 21 and a conductive film 22 are deposited to fill the opening 16A and the connection hole 20 (FIGS. 72 and 7).
3).

Subsequently, FIG. 37 in the first embodiment is described.
˜Barrier conductor film 21 and conductive film 22 on interlayer insulating film 11 and etching stopper film 16 are removed by a process similar to the process described with reference to FIGS. Thus, the barrier conductor film 21 and the conductive film 22 are left inside the connection hole 20, so that the plug 23 can be formed. Further, by leaving the barrier conductor film 21 and the conductive film 22 inside the opening 16A, the polycrystalline silicon film 7A, the barrier conductor film 21 and the conductive film 22 are formed.
It is possible to form the gate electrode 24 composed of (FIG. 7).
4 to FIG. 77). As described above, according to the second embodiment, the plug 23 and the gate electrode 24 made of the laminated film of the polycrystalline silicon film 7A, the barrier conductor film 21, and the conductive film 22 can be formed in the same step, so that the plug 23 and the The number of steps can be reduced as compared with the case where the gate electrode 24 is formed in individual steps. Through the steps so far, the n-channel type MISFET Qn and p
The channel type MISFET Qp can be formed.

Next, by the same steps as those described with reference to FIGS. 42 and 43 in the first embodiment,
After the etching stopper film 25 and the interlayer insulating film 26 are sequentially deposited, a connection hole 27 reaching the plug 23 and a connection hole 28 reaching the gate electrode are formed in the etching stopper film 25 and the interlayer insulating film 26. Then, the connection hole 2
After titanium nitride is deposited on the semiconductor substrate 1 including the insides of 7 and 28 by the sputtering method, a W film is deposited on the titanium nitride film by the CVD method to fill the connection holes 27 and 28. Next, the titanium nitride film and the W film on the interlayer insulating film 26 are removed by the CMP method, and the titanium nitride film and the W film are left inside the connection holes 27 and 28, whereby the plug 3
0 and 31 are formed respectively (see FIGS. 78 and 79).

Next, by the same steps as those described with reference to FIGS. 44 and 45 in the first embodiment,
The first layer wiring 32 and the second layer wiring 34 are formed, and the semiconductor integrated circuit device according to the second embodiment is manufactured (see FIGS. 80 and 81). In the second embodiment as well, 2
Although the case of forming the wiring layers of layers has been described, the number of wiring layers is not limited to two, and more layers may be formed.

Also in the second embodiment, the wiring may be formed using Cu as the main conductive layer. For example, after the plugs 30 and 31 (see FIGS. 78 and 79) are formed, the first layer embedded wiring 32B and the second layer embedded are formed by the process described with reference to FIGS. 46 and 47 in the first embodiment. The wiring 34B can be formed (see FIGS. 82 and 83). In the second embodiment as well, the case where two layers of embedded wirings are formed has been described, but the number of embedded wirings is not limited to two and may be formed in multiple layers.

(Third Embodiment) In the third embodiment, the silicon oxide film 2 in the element isolation trench 3 is formed by etching (see FIG. 33) when forming the connection hole 20 described in the first embodiment. In order to prevent the damage of the n-type semiconductor region 8 and the p-type semiconductor region 9 (see FIG. 2), a thin film having a high etching selection ratio with respect to the silicon oxide film 2 is deposited on the semiconductor substrate 1. It is a thing. A method of manufacturing the semiconductor integrated circuit device according to the third embodiment will be described in the order of steps with reference to FIGS. 84 to 121.

The method of manufacturing the semiconductor integrated circuit device according to the third embodiment is the same up to the step described with reference to FIG. 2 in the first embodiment.

After that, as shown in FIGS. 84 to 86, for example, a silicon nitride film having a high etching selection ratio with respect to the silicon oxide film 2 is deposited on the semiconductor substrate 1 by the CVD method to form an etching stopper film. (Second insulating film) 11A is formed. This etching stopper film 11
A can be exemplified to have a film thickness of about 100 nm.

Subsequently, in FIG. 3 to FIG.
After the interlayer insulating film 11 is formed by the process similar to the process described with reference to FIG. 5, the dummy gate electrode 7 is formed by the CMP method.
The interlayer insulating film 11 and the etching stopper film 11A are polished until the surface of (1) appears.

Next, the dummy gate electrode 7 and the dummy gate oxide film 6 are selectively removed by a process similar to the process described with reference to FIGS. 12 (FIGS. 87 to 8)
9).

Next, the gate oxide film 13 is formed on the bottom of the opening 12 by the same steps as those described with reference to FIGS. 9 to 13 in the first embodiment (FIGS. 90 to 92).
(See), the barrier conductor film 14A and the conductive film 14
B is sequentially deposited from the lower layer (see FIGS. 93 and 94).

Next, FIG. 14 to FIG.
By the process similar to the process described with reference to FIG. 16, the barrier conductor film 14A and the conductive film 14 on the interlayer insulating film 11 are formed.
B is removed, and the barrier conductor film 14A and the conductive film 1 are removed.
4B is left only in the opening 12 (see FIGS. 95 to 97). Then, the barrier conductor film 14 in the opening 12
By anisotropically etching A and the conductive film 14B, the height of the surface thereof is made lower than the height of the surface of the interlayer insulating film 11 to form the gate electrode 14 (see FIGS. 98 and 99). At this time, the difference between the surface of the interlayer insulating film 11 and the surface of the gate electrode 14 is due to the etching stopper film 11A.
It is possible to exemplify that the thickness is set to be equal to or larger than the film thickness, and in the third embodiment, it is set to about 100 nm. As a result, in a subsequent step, the n-type semiconductor region (source, drain) 8 and the p-type semiconductor region (source, drain) 9 are formed.
It is possible to keep the side wall of the gate electrode 14 covered with the etching stopper film 11A when the connection hole reaching the height is formed. The process will be described in detail later. Through the steps up to this point, the n-channel type MISFET Qn and the p-channel type MISFET Qp can be formed.

Next, FIG. 27 to FIG.
The photoresist film 17 is formed by the same steps as the steps described with reference to FIG. 30 (see FIGS. 100 to 103). Also in the third embodiment, as in the case of the first embodiment, the planar shape of the opening 18 can be a slit type (see FIG. 100) or a rectangle (see FIG. 101).

Next, referring to FIG. 31 to FIG.
By a process similar to the process described with reference to FIG. 34, the connection hole 20 reaching the n-type semiconductor region 8 (source, drain) and the p-type semiconductor region (source, drain) 9 is formed (see FIGS. 104 to 107). ). At this time, the gate electrode 1
Since the etching stopper film 11A existing on the side wall of No. 4 has a high etching selection ratio with respect to the interlayer insulating film 11, the contact hole 20 is separated from the gate electrode 14 by the thickness of the etching stopper film 11A. Can be opened at the position. As a result, also in the third embodiment, it is not necessary to cover the gate electrode 14 with the photoresist film 17, so that the mask (photoresist film 17) is used.
It is possible to omit the provision of the alignment margin with respect to the gate electrode 14. That is, since the elements included in the semiconductor integrated circuit device according to the third embodiment can be miniaturized, the elements can be highly integrated.

Further, the connection hole 20 is formed in the gate electrode 14
Since the holes can be opened at a constant position separated by the film thickness of the etching stopper film 11A from the above, the distance between the gate electrode 14 and the connection hole 20 can be made constant even between the plurality of semiconductor substrates 1. Thereby, a plurality of the third embodiment
It is possible to prevent variations in characteristics among the semiconductor integrated circuit devices.

By the way, in the first and second embodiments, the groove portion 15 is formed and the groove portion 1 is formed.
The case where the connection hole 20 is formed at a position separated from the gate electrode 14 by a certain distance by embedding the etching stopper film 16A in the layer 5 has been described (FIGS. 31 to 31).
34 and 68 to 71). On the other hand, in the third embodiment, the contact hole 20 is formed at a position separated from the gate electrode 14 by a certain distance by the etch stopper film 11A formed before forming the interlayer insulating film 11. There is. That is, in the third embodiment, the step of forming the groove portion 15 performed in the first and second embodiments, the step of depositing the etching stopper film 16 on the semiconductor substrate 1, and the interlayer insulating film 11 are performed. Also, the step of removing the etching stopper film 16 on the gate electrode 14 can be omitted. Therefore, according to the method of manufacturing the semiconductor integrated circuit device of the third embodiment, the number of steps can be reduced as compared with the first and second embodiments.

In the step of forming the connection hole 20, the etching stopper film 11A is formed on the bottom of the connection hole 20.
When there is no such a layer, since the interlayer insulating film 11 is formed of silicon oxide, an etching reaction also occurs in the silicon oxide film 2 existing in the element isolation trench 3 at the time of etching for forming the connection hole 20 and the oxidation occurs. There is a risk of damaging the silicon film 2. Therefore, in the third embodiment, the etching stopper film 11A is formed,
At the time of forming the connection hole 20, only the interlayer insulating film 11 is selectively etched. Therefore, it is possible to prevent the silicon oxide film 2 from being damaged.

Next, as shown in FIGS. 108 and 109, the etching stopper film 11A is selectively and anisotropically etched to remove the etching stopper film 11A at the bottom of the connection hole 20. At this time, the upper surface of the etching stopper film 11A existing on the side wall of the gate electrode 14 is also etched by the film thickness. Third Embodiment
Then, before the etching step, the upper surface of the etching stopper film 11A is present at a position higher than the upper surface position of the gate electrode 14 by the film thickness of the etching stopper film 11A or more. That is, even after the etching process, the gate electrode 1 is removed by the etching stopper film 11A.
The side wall of 4 can be kept covered. as a result,
It is possible to prevent a short circuit between the gate electrode 14 and the plug formed in the connection hole 20 in a later step.

Next, by the same steps as those described in the first embodiment with reference to FIGS. 35 and 36,
A barrier conductor film 21 and a conductive film 22 are deposited, and the connection hole 20 is buried (see FIGS. 110 and 111).

Next, as shown in FIGS. 112 to 115,
The interlayer insulating film 11, the etching stopper film 11A, the barrier conductor film 21, and the conductive film 22 are polished by the CMP method using the upper surface of the gate electrode 14 as the polishing end point. As a result, the barrier conductor film 21 and the conductive film 22 are connected to the connection hole 2
The plug 23 can be formed by leaving the inside of 0.
Note that FIG. 112 shows a case where the planar shape of the opening 18 of the photoresist film 17 is a slit type (FIG. 100).
FIG. 113 is a plan view of relevant parts corresponding to the case where the opening 18 of the photoresist film 17 has a rectangular plan shape (see FIG. 101).

Next, by the same steps as the steps described with reference to FIGS. 42 and 43 in the first embodiment,
After the etching stopper film 25 and the interlayer insulating film 26 are sequentially deposited, a connection hole 27 reaching the plug 23 and a connection hole 28 reaching the gate electrode are formed in the etching stopper film 25 and the interlayer insulating film 26. Then, the connection hole 2
After titanium nitride is deposited on the semiconductor substrate 1 including the insides of 7 and 28 by the sputtering method, a W film is deposited on the titanium nitride film by the CVD method to fill the connection holes 27 and 28. Next, the titanium nitride film and the W film on the interlayer insulating film 26 are removed by the CMP method, and the titanium nitride film and the W film are left inside the connection holes 27 and 28, whereby the plug 3
0 and 31 are formed respectively (see FIGS. 116 and 117).
reference).

Next, by the same steps as the steps described with reference to FIGS. 44 and 45 in the first embodiment,
The first layer wiring 32 and the second layer wiring 34 are formed, and the semiconductor integrated circuit device of the third embodiment is manufactured (see FIGS. 118 and 119). In the third embodiment, the case where two wiring layers are formed has been described.
The number of wiring layers is not limited to two and may be formed in multiple layers.

Also in the third embodiment, the wiring may be formed using Cu as the main conductive layer. For example, after the plugs 30 and 31 (see FIGS. 116 and 117) are formed, FIGS. 46 and 47 in the first embodiment.
By the process described with reference to FIG.
B and the second layer embedded wiring 34B can be formed (see FIGS. 120 and 121). In the third embodiment, the case of forming the two-layer embedded wiring has been described, but the number of embedded wirings is not limited to two layers and may be formed in multiple layers.

Although the invention made by the present inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it can be changed.

For example, in the above-mentioned embodiment, the case where the etching stopper film on the gate electrode is removed by the CMP method has been described, but the etchback method may be used.

[0087]

The effects obtained by the typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) An interlayer insulating film (first insulating film) whose surface is higher than that of the gate electrode is isotropically and selectively etched to form a groove portion (second groove portion) surrounding the gate electrode, After filling an etching stopper film (second insulating film) capable of obtaining a high dry etching selection ratio with respect to the interlayer insulating film in the groove portion, a connection hole reaching the source / drain (semiconductor region) in the interlayer insulating film ( Since the first hole portion) is formed in a self-aligning manner, the connection hole can be opened at a fixed position apart from the gate electrode by the width of the groove portion. (2) A contact hole (first hole portion) reaching the source / drain (semiconductor region) can be formed in a position separated from the gate electrode by a certain distance in a self-aligned manner, and a mask used for opening the contact hole can be formed. Since it is possible to omit providing the alignment margin with respect to the gate electrode, it is possible to highly integrate the elements of the semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 3 is a plan view of a principal part during a manufacturing step of the semiconductor integrated circuit device which is one embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 2;

FIG. 5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

6 is a main-portion plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3; FIG.

FIG. 7 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 4;

FIG. 8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 5;

9 is a main-portion plan view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6; FIG.

10 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;

FIG. 14 is a plan view of a main portion during a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

16 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 13; FIG.

FIG. 17 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 15;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;

FIG. 19 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device of the embodiment of the present invention.

FIG. 20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 17;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18;

22 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 20; FIG.

FIG. 23 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, which is subsequent to FIG. 21;

FIG. 24 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is the embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;

FIG. 26 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 23;

FIG. 27 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 24;

FIG. 28 is a plan view of the essential part during the manufacturing process of the semiconductor integrated circuit device, following FIG. 24;

29 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 25. FIG.

FIG. 30 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 26.

FIG. 31 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 27;

FIG. 32 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 28;

FIG. 33 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, which is subsequent to FIG. 29;

34 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 30. FIG.

FIG. 35 is an essential part cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 33;

FIG. 36 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 34.

FIG. 37 is a main-portion plan view of the semiconductor integrated circuit device in the manufacturing process according to the embodiment of the present invention;

FIG. 38 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is the embodiment of the present invention;

FIG. 39 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 35;

40 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 36.

41 is a plan view of essential parts in the manufacturing process of the semiconductor integrated circuit device, which is subsequent to FIG. 37 or FIG. 38;

42 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 39.

FIG. 43 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, which is subsequent to FIG. 40;

44 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 42.

45 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 43.

FIG. 46 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 42;

FIG. 47 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 43;

FIG. 48 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 49 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 50 is an essential part cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 48;

FIG. 51 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 52 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 50;

53 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 51.

FIG. 54 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 55 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 52;

FIG. 56 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 53;

57 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device continued from FIG. 55; FIG.

FIG. 58 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 56.

FIG. 59 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 60 is an essential part cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 57;

FIG. 61 is an essential part cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 58;

62 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 60.

FIG. 63 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 61;

FIG. 64 is a fragmentary plan view during the manufacturing process of the semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 65 is a plan view of a main portion during a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 66 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 62;

67 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 63.

FIG. 68 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 64;

69 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 65; FIG.

FIG. 70 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 66;

71 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 67; FIG.

72 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 70. FIG.

FIG. 73 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 71;

FIG. 74 is a plan view of a main portion during a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 75 is a plan view of a main portion during a manufacturing step of a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 76 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 72.

77 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 73. FIG.

78 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 76;

79 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 77. FIG.

FIG. 80 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 78;

81 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 79.

82 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 78; FIG.

83 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 79.

FIG. 84 is a main-portion plan view showing the manufacturing method of the semiconductor integrated circuit device, which is still another embodiment of the present invention.

FIG. 85 is a main-portion cross-sectional view showing the manufacturing method of the semiconductor integrated circuit device which is still another embodiment of the present invention.

FIG. 86 is a fragmentary cross-sectional view showing the manufacturing method of the semiconductor integrated circuit device which is still another embodiment of the present invention.

87 is a main-portion plan view of the semiconductor integrated circuit device in a manufacturing process, following FIG. 84; FIG.

88 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 85.

89 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 86.

90 is a fragmentary plan view in the manufacturing process of the semiconductor integrated circuit device, following FIG. 87; FIG.

91 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 88. FIG.

92 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 89. FIG.

93 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 91; FIG.

94 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 92.

FIG. 95 is a plan view of a main portion during a manufacturing process of a semiconductor integrated circuit device which is still another embodiment of the present invention.

96 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 93.

97 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 94.

98 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 96; FIG.

99 is a fragmentary sectional view in the manufacturing process of the semiconductor integrated circuit device, following FIG. 97; FIG.

FIG. 100 is a plan view of a substantial part during a manufacturing process of a semiconductor integrated circuit device which is still another embodiment of the present invention.

FIG. 101 is a plan view of a substantial part during a manufacturing process of a semiconductor integrated circuit device which is still another embodiment of the present invention.

102 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 98; FIG.

103 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 99; FIG.

104 is a main-portion plan view of the semiconductor integrated circuit device in a manufacturing process, following FIG. 100; FIG.

FIG. 105 is a main-portion plan view of the semiconductor integrated circuit device in the manufacturing process, following FIG. 101;

FIG. 106 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 102;

FIG. 107 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 103;

108 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 106;

FIG. 109 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, which is subsequent to FIG. 107;

110 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 108; FIG.

111 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 109. FIG.

FIG. 112 is a plan view of a main portion during a manufacturing process of a semiconductor integrated circuit device which is still another embodiment of the present invention.

FIG. 113 is a plan view of a main portion during a manufacturing step of a semiconductor integrated circuit device which is still another embodiment of the present invention.

114 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 110; FIG.

115 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 111. FIG.

116 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 114; FIG.

117 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 115;

118 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 116.

119 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 117. FIG.

120 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 116;

121 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG. 117.

[Explanation of symbols]

1 Semiconductor substrate 2 Silicon oxide film 3 element isolation grooves 4 p-type well 5 n-type well 6 Dummy gate oxide film 6A gate oxide film 7 Dummy gate electrode 7A Polycrystalline silicon film 8 n-type semiconductor region (source, drain) 9 p-type semiconductor region (source, drain) 11 Interlayer insulation film (first insulation film) 11A Etching stopper film (second insulating film) 12 Opening (first groove) 13 Gate oxide film 14 Gate electrode 14A Barrier conductor film 14B conductive film (first conductive film) 15 Groove (second groove) 16 Etching stopper film (second insulating film) 16A opening (third groove) 17 Photoresist film 18 openings 20 Connection hole (first hole) 21 Barrier conductor film 22 Conductive film (second conductive film) 23 plugs 24 gate electrode 25 Etching stopper film 26 Interlayer insulation film 27 Connection hole 28 Connection hole 30 plug 31 plug 32 First Layer Wiring 32A wiring groove 32B First layer embedded wiring 33 Interlayer insulation film 33A Etching stopper film 33B insulation film 33C Etching stopper film 33D insulation film 33E Etching stopper film 33F insulation film 34 Second Layer Wiring 34A wiring groove 34B Second layer embedded wiring Qn n-channel type MISFET Qp p channel MISFET

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 29/43 H01L 29/78 301P 29/78 27/08 321F (72) Inventor Katsuhiko Ichinose Ome City, Tokyo 3-16, Shinmachi, Hitachi Ltd. Device Development Center (72) Inventor Yohei Yanagida 3-16, Shinmachi, Ome, Tokyo 3rd F-Term, Hitachi, Ltd. Device Development Center (Reference) 4M104 AA01 BB01 BB04 BB30 BB40 CC01 CC05 DD02 DD04 DD07 DD16 DD17 DD37 DD43 DD52 DD53 DD66 DD75 EE09 EE17 FF18 FF22 GG09 GG10 GG14 HH14 5F033 HH08 HH11 HH33 JJ19 PP07Q37 Q37 Q07 NNQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQHQQQHQHQHQHQHQHQHQQHQHQHQHQHQHQHQHQHQHQHQHQHQHQHQJQPPQQQQQFF QQ11 QQ16 QQ18 QQ19 QQ25 QQ37 QQ48 QQ58 QQ65 RR04 RR06 SS11 TT02 TT07 VV00 XX03 XX15 XX24 XX33 5F048 AA01 AA07 AC03 BA01 BB01 BB05 BE03 BF01 BF07 BF12 BF15 BF16 BG12 5F140 AA39 AA40 AB03 BA01 BF03 BF04 BF10 BF11 BF15 BF20 BF21 BF27 BG04 CB08 CC08 CB08 CB08 CB08 CA08 CB05 CB05 BB05 BB28 BB05 BB28 BB03 CE07 CF00

Claims (20)

[Claims] 1. A step of forming a first insulating film on a semiconductor substrate, a step of forming a first groove in the first insulating film, and a surface of the first groove in the first groove. Forming a first conductive film lower than the surface of the first insulating film, (d) selectively and isotropically etching a part of the first insulating film, and a side surface of the first conductive film. Second adjacent to
A step of forming a groove portion, (e) a step of forming a second insulating film having a large etching selection ratio with respect to the first insulating film in the second groove portion, and (f) relatively relative to the second insulating film. Forming a first hole portion in the first insulating film in a self-aligned manner with the second insulating film under a condition that the etching rate of the first insulating film is large. Method of manufacturing circuit device. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film contains silicon oxide as a main component, and the second insulating film contains silicon nitride as a main component. Manufacturing method of semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the etching in the step (d) uses hydrofluoric acid. 4. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a source, a drain and a gate, which includes the steps of: (a) forming a semiconductor region to be the source / drain on a main surface of a semiconductor substrate. (B) After the step (a),
Forming a first insulating film on the semiconductor substrate, (c)
Forming a first groove in the first insulating film, (d) depositing a first conductive film forming the gate on the semiconductor substrate, and filling the first groove with the first conductive film And (e) a second adjoining side surface of the first conductive film by selectively and isotropically etching a part of the first insulating film.
A step of forming a groove portion, (f) a step of forming a second insulating film in the second groove portion, and (g) under a condition that the etching rate of the first insulating film is relatively larger than that of the second insulating film. Forming a first hole in the first insulating film reaching the semiconductor region in a self-aligned manner with respect to the second insulating film. 5. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a source, a drain and a gate, including the steps of: (a) forming a dummy gate electrode on a main surface of a semiconductor substrate; After the step (a), the step of forming a semiconductor region to be the source / drain on the main surface of the semiconductor substrate, (c) after the step (b), the first semiconductor layer is formed on the semiconductor substrate.
Forming an insulating film, (d) polishing the first insulating film to the height of the upper surface of the dummy gate electrode, (e)
The dummy gate electrode is removed and a first insulating film is formed on the first insulating film.
Forming a groove, (f) depositing a first conductive film forming the gate on the semiconductor substrate, and filling the first groove with the first conductive film, (g) the first Polishing and removing the first conductive film outside the groove,
(H) a step of removing a part of the first conductive film in the first groove part to make the surface thereof lower than the surface of the first insulating film, (i) the step of (h), and then the first step. A step of selectively and isotropically etching a part of the insulating film to form a second groove portion adjacent to the side surface of the first conductive film; (j) forming a second insulating film in the second groove portion And (k) the second step
Under the condition that the etching rate of the first insulating film is relatively higher than that of the insulating film, a first hole portion that reaches the semiconductor region in a self-aligned manner with the second insulating film is formed in the first insulating film. Forming process. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein after the step (k), a second conductive film is formed in the first hole portion. Production method. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein the first conductive film contains tungsten as a main component. 8. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a source, a drain and a gate, including the steps of: (a) forming a dummy gate electrode on a main surface of a semiconductor substrate; After the step (a), a step of forming a semiconductor region to be the source / drain on the main surface of the semiconductor substrate, (c) After the step (b), a second layer is formed on the semiconductor substrate and on the sidewall of the dummy gate electrode. Forming an insulating film; (d) forming a first insulating film on the second insulating film; (e) forming the first insulating film and the second insulating film up to the height of the surface of the dummy gate electrode. Polishing process,
(F) removing the dummy gate electrode and forming a first groove in the first insulating film, (g) depositing a first conductive film on the semiconductor substrate, and forming the first groove in the first groove. Filling with a conductive film, (h) etching back the first conductive film to remove the first conductive film outside the first groove, and to remove the first conductive film in the first groove. Lowering the surface of the conductive film below the surface of the first insulating film, (i)
A first hole reaching the semiconductor region in a self-aligning manner with the first insulating film under the condition that the etching rate of the first insulating film is relatively higher than that of the second insulating film. Forming a portion, (j) depositing a second conductive film on the semiconductor substrate and filling the first hole with the second conductive film, (k) a surface of the first conductive film The second conductive film, the first insulating film, and the second insulating film to the height of the second conductive film, and the second conductive film is left in the first hole portion, so that the semiconductor is formed in the first hole portion. Forming a plug that electrically connects to the region. 9. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a source, a drain, and a gate, including the steps of: (a) after forming a first conductive film to be the gate on a semiconductor substrate. Patterning the first conductive film, (b) forming a semiconductor region to be the source / drain on the main surface of the semiconductor substrate, (c) the (a)
After the step and the step (b), a first layer is formed on the semiconductor substrate.
Forming an insulating film, (d) removing a part of the first conductive film and lowering the surface of the insulating film below the surface of the first insulating film, (e) after the (d) step, the A step of selectively and isotropically etching a part of the first insulating film to form a second groove portion adjacent to the side surface of the first conductive film; (f) placing the second insulating film in the second groove portion Forming step (g) the first insulating film is self-aligned with the second insulating film under the condition that the etching rate of the first insulating film is relatively higher than that of the second insulating film. A step of forming a first hole reaching the semiconductor region. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein in the step (c), (c1) the first insulating film is deposited on the semiconductor substrate and the first conductive film. And (c2) polishing the first insulating film so that its surface is at the same height as the surface of the first conductive film, a method of manufacturing a semiconductor integrated circuit device. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the first conductive film contains silicon as a main component. 12. A method of manufacturing a semiconductor integrated circuit device having a MISFET including a source, a drain and a gate, which comprises the steps of: (a) after forming a first conductive film to be the gate on a semiconductor substrate. Patterning the first conductive film, (b) forming a semiconductor region to be the source / drain on the main surface of the semiconductor substrate, (c) the (a)
A step of forming a first insulating film on the semiconductor substrate and on the first conductive film after the step and the step (b),
(D) a step of polishing the first insulating film so that its surface has the same height as the surface of the first conductive film, (e) the step (d)
After the step, a step of removing a part of the first conductive film and lowering the surface of the first conductive film below the surface of the first insulating film; (f) After the step (e), a part of the first insulating film is removed. A step of selectively and isotropically etching to form a second groove portion adjacent to a side surface of the first conductive film; (g) forming a second insulating film in the second
Forming in the groove, (h) after step (g), removing a part of the first conductive film to form a third groove,
(I) Under the condition that the etching rate of the first insulating film is relatively higher than that of the second insulating film, the first insulating film reaches the semiconductor region in a self-aligned manner with respect to the second insulating film. Forming a first hole, (j) depositing a second conductive film on the semiconductor substrate, and filling the third groove and the first hole with the second conductive film;
(K) By polishing the second conductive film to a height of the surface of the first conductive film and leaving the second conductive film in the third groove and the first hole, the first conductive film is formed. Forming a gate electrode composed of a conductive film and the second conductive film on the first conductive film, and forming a plug electrically connected to the semiconductor region in the first hole. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12, wherein the first conductive film contains silicon as a main component, and the second conductive film contains tungsten as a main component. Manufacturing method of semiconductor integrated circuit device. 14. A first insulating film formed on a semiconductor substrate, a first conductive film formed in the first insulating film and patterned into a predetermined shape, and a periphery of the first conductive film. A second insulating film formed so as to surround the first conductive film and having a large etching selection ratio with respect to the first insulating film, and a second insulating film in the first insulating film with respect to the second insulating film. And a plug formed in the first hole and in contact with the second insulating film. 15. The semiconductor integrated circuit device according to claim 14, wherein the first insulating film contains silicon oxide as a main component, and the second insulating film contains silicon nitride as a main component. apparatus. 16. A semiconductor region of a source / drain portion formed on a main surface of a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a gate electrode formed in the first insulating film. A second insulating film formed so as to surround the periphery of the gate electrode, contacting at least a part of a side surface of the gate electrode, and having a large etching selection ratio with respect to the first insulating film; A first hole formed in self-alignment with the second insulating film;
A semiconductor integrated circuit device having a MISFET, characterized in that it has a plug formed in a hole, in contact with the second insulating film, and electrically connected to the semiconductor region. 17. The semiconductor integrated circuit device according to claim 16, wherein the first insulating film contains silicon oxide as a main component, and the second insulating film contains silicon nitride as a main component. apparatus. 18. The semiconductor integrated circuit device according to claim 16, wherein the gate electrode contains tungsten as a main component. 19. The semiconductor integrated circuit device according to claim 16, wherein the gate electrode is made of a thin film in which a polycrystalline silicon film and a tungsten film are laminated. 20. A semiconductor region of a source / drain portion formed on a main surface of a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and a gate electrode formed in the first insulating film. , In a plane parallel to the semiconductor substrate,
A second insulating film formed so as to surround the periphery of the gate electrode, contacting a side surface of the gate electrode, and having a large etching selection ratio with respect to the first insulating film; and the second insulating film in the first insulating film. A first hole formed in a self-alignment manner with respect to the first hole, and a plug formed in the first hole, in contact with the second insulating film, and electrically connected to the semiconductor region. A semiconductor integrated circuit device having a MISFET.