KR20040008711A - Method for fabricating gate electrode in semiconductor device - Google Patents
Method for fabricating gate electrode in semiconductor device Download PDFInfo
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- KR20040008711A KR20040008711A KR1020020042382A KR20020042382A KR20040008711A KR 20040008711 A KR20040008711 A KR 20040008711A KR 1020020042382 A KR1020020042382 A KR 1020020042382A KR 20020042382 A KR20020042382 A KR 20020042382A KR 20040008711 A KR20040008711 A KR 20040008711A
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- Prior art keywords
- gate
- film
- forming
- substrate
- hole
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 229920005591 polysilicon Polymers 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 241000723353 Chrysanthemum Species 0.000 description 1
- 235000005633 Chrysanthemum balsamita Nutrition 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 게이트 전극형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to a method of forming a gate electrode.
반도체 소자가 집적화되면서 게이트 전극의 선폭 및 게이트 절연층의 두께도 따라서 감소한다.As the semiconductor device is integrated, the line width of the gate electrode and the thickness of the gate insulating layer are also reduced.
게이트 전극의 선폭은 감소하지만 반도체 소자에서 요구하는 전도도를 유지해야 되기 때문에 게이트용 전도막을 폴리 실리콘막에서 폴리실리콘 및 텅스텐등의 금속을 사용하여 이중막으로 게이트 전극을 형성한다.Since the line width of the gate electrode is reduced, but the conductivity required by the semiconductor device must be maintained, the gate electrode is formed from a polysilicon film using a metal such as polysilicon and tungsten in a double film.
따라서 게이트 패턴 형성시에 금속을 사용하게 되어 게이트용 전도막을 패터닝할 때에 기판 표면에 데미지를 주고, 데이지를 받은 기판표면에 형성된 활성영역과 콘택플러그간의 전기적 특성저하등의 문제점이 생기고 있다.Therefore, a metal is used to form the gate pattern, thereby damaging the surface of the substrate when patterning the gate conductive film, and deteriorating the electrical characteristics between the active region formed on the surface of the substrate subjected to the daisy and the contact plug.
도1a 및 도1b는 종래기술에 의한 반도체 장치의 게이트 제조방법을 나타내는 공정단면도이다.1A and 1B are cross-sectional views showing a method of manufacturing a gate of a semiconductor device according to the prior art.
도1a를 참조하여 살펴보면, 반도체 기판(10)에 피모스트랜지스와 앤모스트랜지스터가 형성될 영역에 각각 N-Well과 P-Well(미도시)을 형성한다. 이어서 기판의 소자분리막이 형성될 영역을 식각하여 트렌치 홀을 형성하고, 트렌치 홀에 절연물을 매립하여 소자분리막을 형성한다.Referring to FIG. 1A, N-Well and P-Well (not shown) are formed in regions where a PMOS transistor and an MOS transistor are to be formed in the semiconductor substrate 10. Subsequently, a region in which the device isolation film is to be formed is etched to form a trench hole, and an insulation material is embedded in the trench hole to form a device isolation film.
이어서 기판 전면에 게이트 패턴용 절연막(12)를 형성하고, 그 상부에 게이트 패턴의 도전막으로 폴리실리콘막(13) 및 텅스텐막(14)을 형성한다. 이어서 그 상부에 후속공정에서 상부패턴과의 절연을 위한 절연막(15)을 형성한다.Next, a gate pattern insulating film 12 is formed over the entire substrate, and a polysilicon film 13 and a tungsten film 14 are formed thereon as a conductive film of the gate pattern. Subsequently, an insulating film 15 for insulating the upper pattern is formed on the upper part.
이어서 도1b를 참조하여 살펴보면, 게이트 패턴용 마스크를 이용하여 절연막(12),폴리실리콘막(13), 텅스텐막(14), 절연막(15)를 패터닝하여 게이트 패턴을 형성한다.Subsequently, referring to FIG. 1B, a gate pattern is formed by patterning the insulating film 12, the polysilicon film 13, the tungsten film 14, and the insulating film 15 using a gate pattern mask.
이 때 텅스텐막(14)을 패터닝하기 때문에 기판표면에 데미지를 받게 되는데 이때 받는 데미지로 기판표면이 손상된다. 이어서 게이트패턴 측면에 절연막으로 스페이서를 형성하는 공정을 진행하는데 손상된 기판표면으로 인해 스페이서가 제대로 형성되지 않고 이로 인해 핫 케리어(Hot carrier) 특성도 저하되는 문제점을 가지고 있다.At this time, since the tungsten film 14 is patterned, damage is caused to the surface of the substrate, at which time the surface of the substrate is damaged. Subsequently, in the process of forming a spacer with an insulating layer on the side of the gate pattern, a spacer is not formed properly due to a damaged substrate surface, and thus, a hot carrier characteristic is also deteriorated.
또한, 손상된 기판표면 하부에 활성영역이 형성되면, 활성영역과 콘택플러그간에 접촉특성이 저하되는 문제점을 가지고 있다.In addition, when the active region is formed below the damaged substrate surface, there is a problem that the contact characteristics between the active region and the contact plug is reduced.
본 발명에 의해 하부 기판상에 손상없이 형성할 수 있는 게이트 전극 제조방법을 제공함을 목적으로 한다.An object of the present invention is to provide a method for manufacturing a gate electrode that can be formed on the lower substrate without damage.
도1a 및 도1b는 종래기술에 의한 반도체 장치의 게이트 제조방법을 나타낸 공정단면도.1A and 1B are cross-sectional views showing a method for manufacturing a gate of a semiconductor device according to the prior art.
도2a 내지 도2h는 본 발명의 바람직한 실시예에 따른 게이트 제조방법을 나타낸 공정단면도.Figures 2a to 2h is a cross-sectional view showing a gate manufacturing method according to a preferred embodiment of the present invention.
* 도면의 주요 부호에 대한 설명* Description of the main symbols in the drawing
20 : 기판20: substrate
21 : 소자분리막21: device isolation film
22 : 게이트용 절연막22: gate insulating film
23 : 스페이서23: spacer
24 : 게이트용 절연막24: insulating film for gate
25 : 게이트용 폴리실리콘막25: polysilicon film for gate
26 : 게이트용 금속막26: gate metal film
27 : 층간절연막27: interlayer insulating film
상기의 목적을 달성하기 위한 본 발명은 기판 상에 게이트 형성용 절연막을형성하는 단계; 게이트가 형성될 영역의 상기 게이트 형성용 절연막을 선택적으로 제거하여 상기 기판이 노출되도록 패터닝하여 게이트홀을 형성하는 단계: 상기 게이트홀의 측벽에 게이트 스페이서를 형성하는 단계; 상기 게이트홀의 바닥에 게이트용 절연막을 형성하는 단계: 및 게이트용 전극막으로 상기 게이트용 홀을 매립하는 단계를 포함하는 반도체 장치의 게이트 전극형성방법을 제공한다.The present invention for achieving the above object comprises the steps of forming an insulating film for forming a gate on a substrate; Selectively removing the gate forming insulating layer in a region where a gate is to be formed and patterning the substrate to expose the substrate, thereby forming a gate hole; forming a gate spacer on a sidewall of the gate hole; Forming a gate insulating film on the bottom of the gate hole; and filling the gate hole with a gate electrode film.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도2a 내지 도2h는 본 발명의 바람직한 실시예에 따른 게이트 제조방법을 나타낸 공정단면도이다.2A through 2H are cross-sectional views illustrating a method of manufacturing a gate according to a preferred embodiment of the present invention.
도2a에 도시된 바와 같이, 반도체 기판(20)에 피모스트랜지스와 앤모스트랜지스터가 형성될 영역에 각각 N-Well과 P-Well(미도시)을 형성한다. 이어서 기판의 소자분리막이 형성될 영역을 식각하여 트렌치 홀을 형성하고, 트렌치 홀에 절연물을 매립하여 소자분리막(21)을 형성한다.As shown in FIG. 2A, N-Well and P-Well (not shown) are formed in regions where the PMOS transistor and the ANMOS transistor are to be formed in the semiconductor substrate 20. Subsequently, a region in which the device isolation film is to be formed is etched to form a trench hole, and an insulation material is embedded in the trench hole to form the device isolation film 21.
이어서 스페이서 형성을 위한 절연막(22)을 실리콘산화막 또는 실리콘질화막으로 증착하고 화학적기계적연마 공정을 이용하여 평탄화한다.Subsequently, an insulating film 22 for forming a spacer is deposited by a silicon oxide film or a silicon nitride film and planarized using a chemical mechanical polishing process.
이어서 도2b에 도시된 바와 같이, 게이트 패턴 형성 마스크를 이용하여 기판(20)이 노출되도록 절연막(22)을 선택적으로 제거하여 게이트홀을 형성하는 단계:Subsequently, as illustrated in FIG. 2B, a gate hole is formed by selectively removing the insulating layer 22 to expose the substrate 20 using the gate pattern forming mask:
이어서 도2c에 도시된 바와 같이, 스페이서용 절연막을 패터닝된 절연막(22)을 따라 형성한 다음, 에치백 공정을 이용하여 패터닝된 절연막(22)의 측벽-게이트용 홀의 측벽에 스페이서(23)를 형성한다.Subsequently, as shown in FIG. 2C, the spacer insulating film is formed along the patterned insulating film 22, and then the spacer 23 is formed on the sidewall of the sidewall-gate hole of the patterned insulating film 22 using an etch back process. Form.
이어서 도2d에 도시된 바와 같이, 게이트용 절연막(24) 및 게이트 전극용 폴리실리콘막(25)을 스페이서(23) 및 절연막(22) 패턴을 따라 차례로 형성한다.Subsequently, as shown in FIG. 2D, the gate insulating film 24 and the gate electrode polysilicon film 25 are sequentially formed along the spacer 23 and the insulating film 22 pattern.
이어서 도2e에 도시된 바와 같이, 피모스트랜지스터가 형성될 영역에 P형 불순물을 도핑한다.Then, as shown in Fig. 2E, the P-type impurity is doped in the region where the MOS transistor is to be formed.
이어서 도2f에 도시된 바와 같이, 앤모스트랜지스터가 형성될 영역에 N형 불순물을 도핑한다.Then, as shown in Fig. 2F, the N-type impurity is doped in the region where the an-mo transistor is to be formed.
이어서 도2g에 도시된 바와 같이, 게이트 전극용 금속막(26)을 증착하고, 화학적기계적 연마 공정을 이용하여 평탄화한다. 여기서 게이트 전극용 금속막은 W,Cu,Al등을 사용할 수 있다.Then, as shown in FIG. 2G, the metal film 26 for the gate electrode is deposited and planarized using a chemical mechanical polishing process. Here, the metal film for the gate electrode may be W, Cu, Al or the like.
이어서 도2h에 도시된 바와 같이, 게이트 패턴 상부에 층간절연막(27)을 형성한다.Subsequently, as shown in FIG. 2H, an interlayer insulating film 27 is formed on the gate pattern.
상기와 같이 스페이서를 먼저 형성하고 게이트 패턴을 형성하게 되면, 게이트 패턴형성공정에서 기판상에 데미지를 주어 손상을 입히지 않아 후속공정에서 활성영역이 안정적으로 형성되어 핫케리어 특성저하를 방지할 수 있다. 또한 활성영역과 콘택플러그와의 접촉특성저하도 방지할 수 있다.If the spacer is first formed and the gate pattern is formed as described above, damage is not caused by damage to the substrate in the gate pattern forming process, and thus active regions are stably formed in the subsequent process to prevent deterioration of hot carrier characteristics. In addition, it is possible to prevent the deterioration of contact characteristics between the active area and the contact plug.
이상에서 설명한 본 발명은, 전술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러가지 치환, 변형및 변경이 가능함이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the spirit and scope of the present invention. It will be apparent to those who have knowledge.
본 발명에 의해 하부기판상에 손상없이 게이트 패턴을 형성할 수 있어 반도체 장치의 제조공정상 신뢰성이 향상된다.According to the present invention, a gate pattern can be formed on the lower substrate without damage, thereby improving reliability in the manufacturing process of the semiconductor device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020042382A KR20040008711A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating gate electrode in semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020042382A KR20040008711A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating gate electrode in semiconductor device |
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| Publication Number | Publication Date |
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| KR20040008711A true KR20040008711A (en) | 2004-01-31 |
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| KR1020020042382A KR20040008711A (en) | 2002-07-19 | 2002-07-19 | Method for fabricating gate electrode in semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999763B2 (en) | 2006-01-13 | 2011-08-16 | Lg Electronics Inc. | Plasma display apparatus |
-
2002
- 2002-07-19 KR KR1020020042382A patent/KR20040008711A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999763B2 (en) | 2006-01-13 | 2011-08-16 | Lg Electronics Inc. | Plasma display apparatus |
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