KR20030000134A - Forming method for field oxide of semiconductor device - Google Patents

Forming method for field oxide of semiconductor device Download PDF

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KR20030000134A
KR20030000134A KR1020010035794A KR20010035794A KR20030000134A KR 20030000134 A KR20030000134 A KR 20030000134A KR 1020010035794 A KR1020010035794 A KR 1020010035794A KR 20010035794 A KR20010035794 A KR 20010035794A KR 20030000134 A KR20030000134 A KR 20030000134A
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trench
insulating film
gas
forming
device isolation
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KR1020010035794A
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Korean (ko)
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차한섭
류혁현
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주식회사 하이닉스반도체
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Publication of KR20030000134A publication Critical patent/KR20030000134A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for fabricating an isolation layer of a semiconductor device is provided to prevent a moat phenomenon in which the isolation layer becomes lower than an active region of a semiconductor substrate, by forming a selective epitaxial growth(SEG) silicon layer in a part of the lower portion of a trench so that the isolation layer is formed after the active region is increased. CONSTITUTION: The trench is formed in the semiconductor substrate(21) by a photolithography process using an isolation mask. A predetermined thickness of the SEG silicon layer(29) is formed on the surface of the trench to increase the active region of the semiconductor substrate. The trench is buried to form the isolation layer(32).

Description

반도체소자의 소자분리절연막 형성방법{Forming method for field oxide of semiconductor device}Forming method for field oxide of semiconductor device

본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 보다 상세하게 트렌치를 이용한 소자분리공정에서 상기 트렌치의 표면에 소정 두께의 선택적 에피택셜 성장(selective epitaxial growth, 이하 SEG 라 함) 실리콘층을 형성하여반도체기판의 활성영역을 증가시킨 다음, 소자분리절연막을 형성하여 상기 소자분리절연막의 가장자리에 모우트(moat)현상이 발생하는 것을 방지하는 반도체소자의 소자분리절연막 형성방법에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and more particularly, to form a selective epitaxial growth (SEG) silicon layer on a surface of the trench in a device isolation process using a trench. The present invention relates to a method for forming a device isolation insulating film of a semiconductor device by forming a device isolation insulating film to increase the active area of a semiconductor substrate and then forming a device isolation insulating film to prevent a moat phenomenon from occurring at the edge of the device isolation insulating film.

고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.

일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.

그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.

그리고, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process becomes difficult to bury the trench region as the design rule decreases as well as the complexity of the process, and when the design rule approaches 0.1 μm, it will be difficult to apply the trench isolation process.

이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.

먼저, 반도체기판(11) 상부에 패드산화막(도시안됨)과 질화막(도시안됨)을 형성한다.First, a pad oxide film (not shown) and a nitride film (not shown) are formed on the semiconductor substrate 11.

다음, 상기 질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the nitride film to expose a portion of the device isolation region.

그 다음, 상기 감광막패턴을 식각마스크로 상기 질화막과 패드산화막 및 소정 두께의 반도체기판(11)을 식각하여 질화막패턴과 패드산화막패턴을 형성하는 동시에 트렌치를 형성한다.Next, the nitride film, the pad oxide film, and the semiconductor substrate 11 having a predetermined thickness are etched using the photoresist pattern as an etch mask to form a nitride film pattern and a pad oxide film pattern and simultaneously form a trench.

다음, 상기 감광막패턴을 제거한다.Next, the photoresist pattern is removed.

그 다음, 상기 구조를 열산화시켜 상기 트렌치의 표면에 열산화막을 형성하고 다시 제거한다. 이때, 상기 열산화공정은 상기 트렌치를 형성하기 위한 식각공정 시 트렌치 표면에 발생된 결함(damage)을 제거하기 위해 실시된다.The structure is then thermally oxidized to form a thermal oxide film on the surface of the trench and removed again. In this case, the thermal oxidation process is performed to remove damage generated on the trench surface during the etching process for forming the trench.

그 다음, 전체표면 상부에 매립절연막(도시안됨)을 형성하여 상기 트렌치를 매립시킨 후 상기 매립절연막을 평탄화시켜 소자분리절연막(13)을 형성한다. 이때, 상기 평탄화공정은 상기 질화막패턴을 식각장벽으로 이용한 화학적 기계적 연마공정(chemical mechanical polishing, 이하 CMP 라 함)으로 실시된다.Next, a buried insulating film (not shown) is formed over the entire surface to fill the trench, and then the buried insulating film is planarized to form the device isolation insulating film 13. In this case, the planarization process is performed by chemical mechanical polishing (hereinafter referred to as CMP) using the nitride film pattern as an etching barrier.

그 다음, 상기 질화막패턴 및 패드산화막패턴을 제거한다. (도 1a 참조)Next, the nitride film pattern and the pad oxide film pattern are removed. (See Figure 1A)

그 후, 게이트전극을 형성하기 전에 세정공정을 실시한다. 이때, 상기 소자분리절연막(13)의 가장자리가 손실되어 ⓧ부분과 같이 소자분리절연막(13)이 반도체기판(11)보다 낮게 형성되는 모우트(moat) 현상이 발생된다. (도 1b 참조)Thereafter, the cleaning step is performed before the gate electrode is formed. At this time, the edge of the device isolation insulating film 13 is lost, so that a moat phenomenon occurs in which the device isolation insulating film 13 is formed lower than the semiconductor substrate 11 as shown in FIG. (See FIG. 1B)

상기와 같이 종래기술에 따른 반도체소자의 소자분리절연막 형성방법은, 소자분리절연막을 형성한 후 실시되는 습식식각공정 및 세정공정에 의해 상기 소자분리절연막의 가장자리가 손실되어 소자분리절연막이 반도체기판의 활성영역보다 낮아지는 모우트 현상이 발생하여 후속 게이트 절연막 형성공정시 상기 함몰 부분에서는 게이트 절연막이 얇게 형성되고, 그로 인하여 게이트 전극형성후 전기장이 크게 걸려 제너레이션(generation)된 핫캐리어(hot carrier)량이 증가하여 트랜지스터의 라이프타임(lifetime)을 감소시키는 문제점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the related art, an edge of the device isolation insulating film is lost by a wet etching process and a cleaning process performed after the device isolation insulating film is formed. In the subsequent gate insulating film forming process, the gate phenomenon is formed to be thinner than the active region, so that the gate insulating film is thinly formed in the recessed portion. Therefore, the amount of hot carriers generated due to the large electric field after the gate electrode is formed is generated. There is a problem of increasing the lifetime of the transistor.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 트렌치 표면에 소정 두께의 SEG 실리콘층을 형성하여 반도체기판의 활성영역을 증가시킨 다음, 소자분리절연막을 형성함으로써 상기 소자분리절연막이 손실되더라도 모우트현상이 발생하는 것을 방지하여 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems of the prior art, by forming a SEG silicon layer of a predetermined thickness on the trench surface to increase the active area of the semiconductor substrate, and then forming a device isolation insulating film, even if the device isolation insulating film is lost It is an object of the present invention to provide a method for forming a device isolation insulating film of a semiconductor device which prevents occurrence of a phenomenon and improves electrical characteristics and reliability of the device.

도 1a 및 도 1b 는 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1A and 1B are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.

도 2a 내지 도 2f 는 본 발명에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11, 21 : 반도체기판 13, 32 : 소자분리절연막11, 21: semiconductor substrate 13, 32: device isolation insulating film

23 : 패드산화막패턴 25 : 질화막패턴23: pad oxide film pattern 25: nitride film pattern

27 : 트렌치 29 : SEG 실리콘층27: trench 29: SEG silicon layer

31 : 매립절연막31: buried insulation film

이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,Method for forming a device isolation insulating film of a semiconductor device according to the present invention for achieving the above object,

반도체기판에 소자분리마스크를 이용한 사진식각공정으로 트렌치를 형성하는 공정과,Forming a trench in a semiconductor substrate by a photolithography process using an element isolation mask;

상기 트렌치 표면에 소정 두께의 SEG 실리콘층을 형성하여 반도체기판의 활성영역을 증가시키는 공정과,Forming an SEG silicon layer having a predetermined thickness on the trench surface to increase the active area of the semiconductor substrate;

상기 트렌치를 매립하여 소자분리절연막을 형성하는 공정을 포함하는 것을 특징으로 한다.And embedding the trench to form a device isolation insulating film.

이하, 첨부된 도면을 참고로 하여 본 발명에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the present invention.

도 2a 내지 도 2f 는 본 발명에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to the present invention.

먼저, 반도체기판(21) 상부에 패드산화막(도시안됨)과 질화막(도시안됨)을 형성한다.First, a pad oxide film (not shown) and a nitride film (not shown) are formed on the semiconductor substrate 21.

다음, 상기 질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴(도시안됨)을 형성한다.Next, a photoresist pattern (not shown) is formed on the nitride film to expose a portion of the device isolation region.

그 다음, 상기 감광막패턴을 식각마스크로 상기 질화막과 패드산화막 및 소정 두께의 반도체기판(21)을 식각하여 질화막패턴(25)과 패드산화막패턴(23)을 형성하는 동시에 트렌치(27)를 형성한다.Next, the nitride layer, the pad oxide layer, and the semiconductor substrate 21 having a predetermined thickness are etched using the photoresist pattern as an etch mask to form the nitride layer pattern 25 and the pad oxide layer pattern 23 and to form a trench 27. .

다음, 상기 감광막패턴을 제거한다. (도 2a 참조)Next, the photoresist pattern is removed. (See Figure 2A)

그 다음, 상기 구조를 열산화시켜 상기 트렌치(27)의 표면에 열산화막(도시안됨)을 형성하였다가 다시 제거하여 상기 트렌치(27)를 형성하기 위한 식각공정 시 트렌치(27) 표면에 발생된 결함(damage)을 제거하기 위해 실시된다.Next, the structure is thermally oxidized to form a thermal oxide film (not shown) on the surface of the trench 27 and then removed to form the trench 27 on the surface of the trench 27 during the etching process to form the trench 27. It is done to eliminate the damage.

다음, 상기 트렌치(27)의 표면에 소정 두께의 SEG 실리콘층(29)을 형성한다. 이때, 상기 SEG 실리콘층(29)은 SEG SiGe층으로 형성될 수도 있다. 상기 SEG 실리콘층(29)은 단지 모우트현상이 발생하는 것을 방지하는 역할을 하지만, 상기 SEG SiGe층에서 도펀트의 확산속도가 낮기 때문에 후속 어닐공정에 의해 웰이나 접합영역에 이온주입된 도펀트가 소자분리절연막으로 확산되어 빠져나가는 것을 방지한다. 특히, 보론이 소자분리절연막으로 빠져나가는 경우 누설전류가 증가하는 동시에 p 웰의 분리 특성도 저하된다.Next, the SEG silicon layer 29 having a predetermined thickness is formed on the surface of the trench 27. In this case, the SEG silicon layer 29 may be formed of a SEG SiGe layer. The SEG silicon layer 29 only serves to prevent the occurrence of the mote phenomenon, but since the dopant diffusion rate is low in the SEG SiGe layer, the dopant is ion-implanted into the well or the junction region by a subsequent annealing process. Diffusion to the isolation insulating film prevents the escape. In particular, when boron exits the device isolation layer, the leakage current increases and the isolation characteristic of the p well also decreases.

상기 SEG 실리콘층(29)은 700 ∼ 1000℃의 온도 및 10 ∼ 500Torr의 압력하에서 100 ∼ 500sccm의 DCS 가스와 50 ∼ 400sccm의 HCl가스를 이용하여 형성된다. 이때, 상기 DCS 가스대신 SiH4가스 또는 Si2H6가스를 사용할 수도 있다. 또한, 상기 SEG SiGe층은 상기와 같은 조건에서 10 ∼ 500sccm의 GeH4가스를 추가로 사용하여 형성된다. 그리고, 상기 SEG SiGe층에서 Ge의 농도비율은 5 ∼ 60%가 되도록 조절한다. (도 2b 참조)The SEG silicon layer 29 is formed using a DCS gas of 100 to 500 sccm and an HCl gas of 50 to 400 sccm at a temperature of 700 to 1000 ° C. and a pressure of 10 to 500 Torr. In this case, SiH 4 gas or Si 2 H 6 gas may be used instead of the DCS gas. In addition, the SEG SiGe layer is formed by using a GeH 4 gas of 10 to 500sccm under the above conditions. In addition, the concentration ratio of Ge in the SEG SiGe layer is adjusted to be 5 to 60%. (See Figure 2b)

다음, 전체표면 상부에 매립절연막(31)을 형성한다. 상기 매립절연막은 CVD 방법으로 형성되는 산화막이다. (도 2c 참조)Next, a buried insulating film 31 is formed over the entire surface. The buried insulating film is an oxide film formed by a CVD method. (See Figure 2c)

그 다음, 상기 매립절연막(31)을 CMP공정으로 평탄화시켜 상기 트렌치(27)을 매립시키는 소자분리절연막(32)을 형성한다. (도 2d 참조)Next, the buried insulating film 31 is planarized by a CMP process to form a device isolation insulating film 32 for filling the trench 27. (See FIG. 2D)

다음, 상기 질화막패턴(25) 및 패드산화막패턴(23)을 제거한다. (도 2e 참조)Next, the nitride film pattern 25 and the pad oxide film pattern 23 are removed. (See Figure 2E)

그 후, 후속공정으로 세정공정 및 식각공정이 실시되어도 소자분리절연막(32)의 가장자리에 모우트 현상이 발생하지 않는 것을 알 수 있다. (도 2 f 참조)Subsequently, even if the cleaning process and the etching process are performed in a subsequent process, it can be seen that no moat phenomenon occurs at the edge of the device isolation insulating film 32. (See Figure 2f)

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 반도체기판에 트렌치를 형성하고, 상기 트렌치 하부의 일부에 선택적 에피택셜 성장(selective epitaxial growth, 이하 SEG 라 함) 실리콘층을 형성하여반도체기판의 활성영역을 증가시킨 후 소자분리절연막을 형성함으로써 상기 소자분리절연막이 후속 식각공정 및 세정공정에 손실되는 것을 방지하여 소자분리절연막이 반도체기판의 활성영역보다 낮아지는 모우트(moat)현상이 발생하는 것을 방지하고, 그로 인하여 후속 게이트전극 형성 후 전기장이 크게 걸리는 것을 방지하여 트랜지스터의 라이프타임(lifetime)을 향상시키는 이점이 있다.As described above, in the method of forming a device isolation insulating film of a semiconductor device according to the present invention, a trench is formed in a semiconductor substrate, and a selective epitaxial growth (SEG) silicon layer is formed in a portion of the lower portion of the trench. Forming a device isolation insulating film after increasing the active area of the semiconductor substrate to prevent the device isolation insulating film from being lost in subsequent etching and cleaning processes so that the device isolation insulating film is lower than the active area of the semiconductor substrate. This phenomenon has the advantage of preventing the occurrence of the phenomenon, thereby preventing the electric field from being largely taken after the formation of the subsequent gate electrode, thereby improving the lifetime of the transistor.

Claims (7)

반도체기판에 소자분리마스크를 이용한 사진식각공정으로 트렌치를 형성하는 공정과,Forming a trench in a semiconductor substrate by a photolithography process using an element isolation mask; 상기 트렌치 표면에 소정 두께의 SEG 실리콘층을 형성하여 반도체기판의 활성영역을 증가시키는 공정과,Forming an SEG silicon layer having a predetermined thickness on the trench surface to increase the active area of the semiconductor substrate; 상기 트렌치를 매립하여 소자분리절연막을 형성하는 공정을 포함하는 반도체소자의 소자분리절연막 형성방법.Forming a device isolation insulating film by filling the trench. 제 1 항에 있어서,The method of claim 1, 상기 SEG 실리콘층 대신 SEG SiGe층을 형성하는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.And forming a SEG SiGe layer instead of the SEG silicon layer. 제 1 항에 있어서,The method of claim 1, 상기 SEG 실리콘층은 700 ∼ 1000℃의 온도 및 10 ∼ 500Torr의 압력하에서 100 ∼ 500sccm의 DCS 가스와 50 ∼ 400sccm의 HCl가스를 이용하여 형성되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The SEG silicon layer is formed using a DCS gas of 100 to 500 sccm and HCl gas of 50 to 400 sccm under a temperature of 700 to 1000 ℃ and a pressure of 10 to 500 Torr. 제 3 항에 있어서,The method of claim 3, wherein 상기 DCS 가스대신 SiH4가스 또는 Si2H6가스가 사용되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.SiH 4 gas or Si 2 H 6 gas is used in place of the DCS gas. 제 2 항에 있어서,The method of claim 2, 상기 SEG SiGe층은 700 ∼ 1000℃의 온도 및 10 ∼ 500Torr의 압력하에서 100 ∼ 500sccm의 DCS 가스와 50 ∼ 400sccm의 HCl가스 및 10 ∼ 500sccm의 GeH4가스를 이용하여 형성되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The SEG SiGe layer is formed using a DCS gas of 100 to 500 sccm, an HCl gas of 50 to 400 sccm and a GeH 4 gas of 10 to 500 sccm at a temperature of 700 to 1000 ° C. and a pressure of 10 to 500 Torr. Device isolation insulating film formation method. 제 5 항에 있어서,The method of claim 5, 상기 DCS 가스대신 SiH4가스 또는 Si2H6가스가 사용되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.SiH 4 gas or Si 2 H 6 gas is used in place of the DCS gas. 제 2 항에 있어서,The method of claim 2, 상기 SEG SiGe층에서 Ge의 농도비율은 5 ∼ 60%가 되도록 조절되는 것을 특징으로 하는 반도체소자의 소자분리절연막 형성방법.The method for forming a device isolation insulating film of a semiconductor device, characterized in that the concentration ratio of Ge in the SEG SiGe layer is adjusted to be 5 to 60%.
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