KR100390240B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR100390240B1 KR100390240B1 KR10-2001-0035791A KR20010035791A KR100390240B1 KR 100390240 B1 KR100390240 B1 KR 100390240B1 KR 20010035791 A KR20010035791 A KR 20010035791A KR 100390240 B1 KR100390240 B1 KR 100390240B1
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- insulating film
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- isolation insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 트렌치를 이용하여 소자분리절연막을 형성한 다음, 반도체기판의 NMOS영역 및 PMOS영역에 p웰 및 n웰을 형성한 후 상기 NMOS영역 내의 소자분리절연막을 소정 두께 제거하여 PMOS영역과 NMOS영역 내의 소자분리절연막 두께 차이를 제거함으로써 PMOS영역에서 기생 누설전류(parasitic leakage current)가 발생하는 것을 방지하고, 게이트 절연막 보전(gate oxide integrity, GOI) 특성을 향상시키는 동시에 인버스 내로우 위드쓰 효과(inverse narrow width effect) 및 서브쓰레셜드 험프(subthreshold hump)현상을 방지하며 NMOS영역에서 게이트전극 형성 후 식각잔류물이 발생하는 것을 방지하여 소자의 동작 특성 및 신뢰성을 향상시키는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a device isolation insulating film is formed using a trench, and then p wells and n wells are formed in an NMOS region and a PMOS region of a semiconductor substrate, and then the device isolation insulating layer in the NMOS region is formed. By removing a predetermined thickness, the parasitic leakage current is prevented from occurring in the PMOS region and the gate oxide integrity (GOI) characteristics are improved by eliminating the difference in the thickness of the isolation layer between the PMOS region and the NMOS region. At the same time, it prevents inverse narrow width effect and subthreshold hump phenomenon and prevents etching residues after forming gate electrode in NMOS region, improving device operation characteristics and reliability. It is a technique to let.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 보다 상세하게 PMOS영역과 NMOS영역 내에 형성되는 소자분리절연막의 두께 차이를 제거하는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for removing a difference in thickness between device isolation insulating films formed in a PMOS region and an NMOS region.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디멘젼(dimension)을 축소하는 것과, 소자간에 존재하는 분리영역의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈(memory cell size)를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of the separation region existing between devices, and the degree of reduction depends on the size of the cell. In this regard, device isolation technology may be used to determine memory cell size.
일반적으로 소자분리 기술에서 디자인 룰이 감소함에 따라 작은 버즈빅 길이와 큰 체적비를 요구하고 있다.In general, as the design rule decreases in device isolation technology, a small buzz length and a large volume ratio are required.
그러나, 종래의 로코스(LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함) 공정방법은 소자분리막이 얇아지는 문제와 버즈빅현상으로 기가(Giga DRAM)급 소자에서는 적용하는데 한계가 있다.However, the conventional LOCOS (LOCOS: LOCOS) process method has a limitation in that it is applied to a giga DRAM device due to a problem of thinning an isolation layer and a buzz big phenomenon.
그리고, 트렌치 소자분리 공정도 공정의 복잡성뿐만 아니라 디자인 룰이 감소할수록 트렌치 영역을 매립하는 것이 어려워지므로 실제로 디자인 룰이 0.1 ㎛ 에 접근하면 트렌치 소자분리 공정도 적용하기가 어려워 질 것이다.In addition, the trench isolation process becomes difficult to bury the trench region as the design rule decreases as well as the complexity of the process, and when the design rule approaches 0.1 μm, it will be difficult to apply the trench isolation process.
이하, 도시되어 있지는 않지만 종래기술에 대하여 설명한다.Hereinafter, although not shown, the prior art will be described.
먼저, 반도체기판 상부에 패드산화막과 질화막을 형성한다.First, a pad oxide film and a nitride film are formed on the semiconductor substrate.
다음, 상기 질화막 상부에 소자분리영역으로 예정되는 부분을 노출시키는 감광막패턴을 형성한다.Next, a photoresist pattern is formed on the nitride film to expose a portion of the device isolation region.
그 다음, 상기 감광막패턴을 식각마스크로 상기 질화막과 패드산화막 및 소정 두께의 반도체기판을 식각하여 질화막패턴과 패드산화막패턴을 형성하는 동시에 트렌치를 형성한다.Next, the nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness are etched using the photoresist pattern as an etch mask to form a nitride film pattern and a pad oxide film pattern and to form a trench.
다음, 상기 감광막패턴을 제거한다.Next, the photoresist pattern is removed.
그 다음, 상기 구조를 열산화시켜 상기 트렌치의 표면에 열산화막을 형성하고 다시 제거한다. 이때, 상기 열산화공정은 상기 트렌치를 형성하기 위한 식각공정 시 트렌치 표면에 발생된 결함(damage)을 제거하기 위해 실시된다.The structure is then thermally oxidized to form a thermal oxide film on the surface of the trench and removed again. In this case, the thermal oxidation process is performed to remove damage generated on the trench surface during the etching process for forming the trench.
다음, 상기 트렌치의 표면에 열산화막을 다시 형성한다.Next, a thermal oxide film is formed again on the trench.
그 다음, 전체표면 상부에 매립절연막을 형성하여 상기 트렌치를 매립시킨 후 상기 매립절연막을 평탄화시켜 소자분리절연막을 형성한다. 이때, 상기 평탄화공정은 상기 질화막패턴을 식각장벽으로 이용한 화학적 기계적 연마공정(chemical mechanical polishing, 이하 CMP 라 함)으로 실시된다.Next, a buried insulating film is formed over the entire surface to fill the trench, and then the buried insulating film is planarized to form a device isolation insulating film. In this case, the planarization process is performed by chemical mechanical polishing (hereinafter referred to as CMP) using the nitride film pattern as an etching barrier.
그 다음, 상기 질화막패턴 및 패드산화막패턴을 제거한다.Next, the nitride film pattern and the pad oxide film pattern are removed.
그 후, n 웰 및 p 웰을 형성하기 위한 이온주입공정을 실시하고, 세정공정을 실시한 후 게이트절연막을 형성한다.Thereafter, an ion implantation process for forming n wells and p wells is performed, and after the cleaning process, a gate insulating film is formed.
상기와 같이 종래기술에 따른 반도체소자의 제조방법은, 소자분리절연막을 형성한 후 게이트절연막이 형성되는 동안 수 차례의 식각공정 및 세정공정이 실시된다. 이는 반도체기판의 PMOS영역과 NMOS영역의 소자분리절연막의 두께 차이를 유발하고, 이로 한하여 소자분리절연막의 손실이 많은 PMOS영역에서는 기생 누설전류(parasitic leakage current)가 발생하고, 게이트 절연막 보전(gate oxide integrity, GOI) 특성을 열화시키는 동시에 인버스 내로우 위드쓰 효과(inverse narrow width effect) 및 서브쓰레셜드 험프(subthreshold hump)현상을 일으키며, NMOS영역에서는 게이트전극 형성 후 식각잔류물이 발생하여 소자간에 단락을 일으키는 등 소자의 신뢰성을 저하시키는 문제점이 있다.As described above, in the method of manufacturing a semiconductor device according to the prior art, after the device isolation insulating film is formed, several etching and cleaning processes are performed while the gate insulating film is formed. This causes a difference in the thickness of the device isolation insulating film between the PMOS region and the NMOS region of the semiconductor substrate. Thus, parasitic leakage current occurs in the PMOS region having a large loss of the device isolation insulating film, and gate oxide preservation is performed. Integrity (GOI) characteristics are degraded, while inverse narrow width effect and subthreshold hump phenomenon occur.In the NMOS region, etching residues occur after the formation of the gate electrode to short-circuit between devices. There is a problem of lowering the reliability of the device, such as causing.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 소자분리절연막을 형성하고, PMOS영역과 NMOS영역에 n 웰 및 p 웰을 형성하기 위한 이온주입공정을 실시한 후 소자분리절연막의 손실이 비교적 적은 NMOS영역의 소자분리절연막을 소정 두께 제거하여 PMOS영역과 NMOS영역 내의 소자분리절연막 두께 차이를 제거하는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, the device isolation insulating film is formed, and after the ion implantation process for forming n well and p well in the PMOS region and the NMOS region, the loss of the device isolation insulating film is relatively small. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which the thickness of the device isolation insulating film in the NMOS region is removed by removing the predetermined thickness of the device isolation insulating film in the NMOS region.
도 1 내지 도 11 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도.1 to 11 are cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
10 : 반도체기판 11 : p웰10 semiconductor substrate 11: p well
12 : n 웰 13 : 패드산화막12: n well 13: pad oxide film
14 : 패드산화막패턴 15 : 질화막14 pad oxide film pattern 15 nitride film
16 : 질화막패턴 17 : 제1감광막패턴16: nitride film pattern 17: first photosensitive film pattern
19 : 트렌치 21 : 열산화막19: trench 21: thermal oxide film
23 : 매립절연막 24 : 소자분리절연막23: buried insulating film 24: device isolation insulating film
25 : 제2감광막패턴 27 : 제3감광막패턴25: second photosensitive film pattern 27: third photosensitive film pattern
이상의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은,Method for manufacturing a semiconductor device according to the present invention for achieving the above object,
반도체기판 상부에 패드산화막과 질화막의 적층구조를 형성하고, 소자분리마스크를 식각마스크로 상기 적층구조와 소정 두께의 반도체기판을 식각하여 질화막패턴, 패드산화막패턴 및 트렌치를 형성하는 공정과,Forming a stacked structure of a pad oxide film and a nitride film on the semiconductor substrate, and etching the stacked structure and a semiconductor substrate having a predetermined thickness using an element isolation mask as an etch mask to form a nitride film pattern, a pad oxide film pattern, and a trench;
상기 트렌치의 표면에 소정 두께의 열산화막을 형성하는 공정과,Forming a thermal oxide film having a predetermined thickness on a surface of the trench;
전체표면 상부에 매립절연막을 형성하는 공정과,Forming a buried insulating film over the entire surface;
상기 매립절연막을 평탄화시켜 상기 트렌치에 매립되는 소자분리절연막을 형성하는 공정과,Forming a device isolation insulating film buried in the trench by planarizing the buried insulating film;
상기 질화막패턴을 제거하는 공정과,Removing the nitride film pattern;
상기 반도체기판에서 PMOS영역으로 예정되는 부분에 n형 불순물을 이온주입하여 n웰을 형성하는 공정과,Forming an n well by implanting an n-type impurity into a portion of the semiconductor substrate to be defined as a PMOS region;
상기 반도체기판에서 NMOS영역으로 예정되는 부분에 p형 불순물을 이온주입하여 p웰을 형성하는 공정과,Forming a p well by ion implanting p-type impurities into a portion of the semiconductor substrate to be defined as an NMOS region;
상기 NMOS영역 내에 형성되어 있는 패드산화막패턴과 소자분리절연막의 소정 두께를 제거하여 상기 PMOS영역 내에 형성되어 있는 소자분리절연막과의 두께 차이를 제거하는 공정을 포함하는 것을 특징으로 한다.And removing a predetermined thickness of the pad oxide film pattern formed in the NMOS region and the device isolation insulating film to remove a thickness difference between the device isolation insulating film formed in the PMOS region.
이하, 첨부된 도면을 참고로 하여 본 발명에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the present invention.
도 1 내지 도 11 은 본 발명에 따른 반도체소자의 제조방법을 도시한 단면도이다.1 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
먼저, 반도체기판(10) 상부에 패드산화막(13)과 질화막(15)을 형성한다. 이때, 상기 패드산화막(13)은 50 ∼ 200Å 두께로 형성되고, 상기 질화막(15)은 1200 ∼ 3000Å 두께로 형성된다. (도 1 참조)First, the pad oxide film 13 and the nitride film 15 are formed on the semiconductor substrate 10. In this case, the pad oxide film 13 is formed to a thickness of 50 ~ 200Å, the nitride film 15 is formed to a thickness of 1200 ~ 3000Å. (See Figure 1)
다음, 상기 질화막(15) 상부에 소자분리영역으로 예정되는 부분을 노출시키는 제1감광막패턴(17)을 형성한다.Next, a first photoresist layer pattern 17 is formed on the nitride layer 15 to expose a portion of the device isolation region.
그 다음, 상기 제1감광막패턴(17)을 식각마스크로 상기 질화막(15)을 식각하여 질화막패턴(16)을 형성한다. (도 2 참조)Next, the nitride film pattern 16 is formed by etching the nitride film 15 using the first photoresist film pattern 17 as an etch mask. (See Figure 2)
다음, 상기 제1감광막패턴(17)을 식각마스크로 상기 패드산화막(13) 및 소정 두께의 반도체기판(11)을 식각하여 패드산화막패턴(14)을 형성하는 동시에 트렌치(19)를 형성한다. 상기 트렌치(19)는 3000 ∼ 4000Å 깊이로 형성된다.Next, the pad oxide layer 13 and the semiconductor substrate 11 having a predetermined thickness are etched using the first photoresist layer pattern 17 as an etch mask to form a pad oxide layer pattern 14 and a trench 19. The trench 19 is formed to a depth of 3000 to 4000 mm 3.
그 다음, 상기 제1감광막패턴을 제거한다. (도 3 참조)Then, the first photoresist pattern is removed. (See Figure 3)
다음, 상기 구조를 세정한다. 상기 세정공정은 NH4OH, H2O2및 H2O가 1 : 5 : 50으로 혼합된 50℃의 SC-1용액을 이용하여 5 ∼ 15분간 세정공정을 실시한 다음,HF : H2O가 99 : 1로 혼합된 용액을 이용하여 150 ∼ 220초간 세정공정을 실시한다.Next, the structure is cleaned. The washing step is a washing process for 5 to 15 minutes using a SC-1 solution of 50 ℃ mixed with NH 4 OH, H 2 O 2 and H 2 O 1: 5: 50, and then HF: H 2 O Using a solution mixed with a value of 99: 1, the washing process is performed for 150 to 220 seconds.
그 다음, 상기 구조를 열산화시켜 상기 트렌치(19)의 표면에 열산화막(21)을 형성한다. 이때, 상기 열산화공정은 1050℃의 온도에서 실시되는 건식산화공정으로 50 ∼ 150Å 두께의 열산화막(21)이 형성되도록 실시된다. (도 4 참조)Then, the structure is thermally oxidized to form a thermal oxide film 21 on the surface of the trench 19. At this time, the thermal oxidation process is a dry oxidation process carried out at a temperature of 1050 ℃ to be carried out so that the thermal oxidation film 21 having a thickness of 50 ~ 150Å. (See Figure 4)
다음, 전체표면 상부에 매립절연막(23)을 형성한다. 상기 매립절연막(23)은 HDP CVD(high density plasma chemical vapor deposition)방법으로 형성되는 산화막으로 4000 ∼ 7000Å 두께로 형성된다.Next, a buried insulating film 23 is formed over the entire surface. The buried insulating film 23 is an oxide film formed by a high density plasma chemical vapor deposition (HDP CVD) method and has a thickness of 4000 to 7000 Å.
그 다음, 800 ∼ 1200℃의 질소분위기에서 20 ∼ 40분간 열처리하여 상기 매립절연막(23)을 치밀화시킨다. (도 5 참조)Then, the buried insulating film 23 is densified by heat treatment for 20 to 40 minutes in a nitrogen atmosphere at 800 to 1200 ° C. (See Figure 5)
다음, 상기 매립절연막(23)을 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP 라 함)공정으로 평탄화시켜 상기 트렌치(19)를 매립시키는 소자분리절연막(24)을 형성한다. 상기 CMP공정은 상기 질화막패턴(16)을 식각장벽으로 사용하여 실시되며, 상기 CMP공정 후 750 ∼ 2000Å의 상기 질화막패턴(16)이 잔류되도록 실시한다. 이로 인하여 상기 소자분리절연막(24)은 반도체기판(10)보다 750Å이상 높게 형성된다. (도 6 참조)Next, the buried insulating film 23 is planarized by a chemical mechanical polishing (hereinafter referred to as CMP) process to form a device isolation insulating film 24 that fills the trench 19. The CMP process is performed using the nitride film pattern 16 as an etch barrier, and the nitride film pattern 16 of 750 to 2000 mV remains after the CMP process. As a result, the device isolation insulating film 24 is formed to be 750 보다 or more higher than that of the semiconductor substrate 10. (See Figure 6)
다음, 상기 질화막패턴(16)을 제거한다. (도 7 참조)Next, the nitride film pattern 16 is removed. (See Figure 7)
그 다음, 전체표면 상부에 PMOS영역으로 예정되는 부분을 노출시키는 제2감광막패턴(25)을 형성한다.Next, a second photosensitive film pattern 25 is formed on the entire surface to expose a portion intended to be a PMOS region.
다음, 상기 제2감광막패턴(25)을 이온주입마스크로 사용하여 n형 불순물을이온주입하여 n웰(12)을 형성한다. 이때, 상기 n형 불순물은 포스포러스(phosphorus) 또는 아즈닉(arsenic)이 사용된다. (도 8 참조)Next, the n well 12 is formed by ion implanting n-type impurities using the second photoresist layer pattern 25 as an ion implantation mask. At this time, the n-type impurity is used (phosphorus) or arsenic (arsenic). (See Figure 8)
그 다음, 상기 제2감광막패턴(25)을 제거한다.Next, the second photoresist pattern 25 is removed.
다음, 전체표면 상부에 NMOS영역으로 예정되는 부분을 노출시키는 제3감광막패턴(27)을 형성한다.Next, a third photoresist pattern 27 is formed on the entire surface to expose a portion intended to be an NMOS region.
그 다음, 상기 제3감광막패턴(27)을 이온주입마스크로 사용하여 p형 불순물을 이온주입하여 p웰(11)을 형성한다. 이때, 상기 p형 불순물은 보론(boron)이 사용된다. (도 9 참조)Subsequently, p-type impurities are formed by implanting p-type impurities using the third photoresist pattern 27 as an ion implantation mask. In this case, boron is used as the p-type impurity. (See FIG. 9)
다음, 상기 제3감광막패턴(27)을 식각마스크로 사용하는 전면식각공정으로 상기 NMOS영역 내에 형성되어 있는 소자분리절연막(24)을 소정 두께 제거한다. 이때, 상기 패드산화막패턴(14)도 같이 제거된다. 상기 NMOS영역 내에 형성되어 있는 소자분리절연막(24)을 소정 두께 제거함으로써 후속 세정공정 및 식각공정에서 PMOS영역 내의 소자분리절연막(24)이 손실되더라도 PMOS영역과 NMOS영역 내의 소자분리절연막(24)의 두께 차이가 발생하는 것을 방지할 수 있다. (도 10 참조)Next, the device isolation insulating film 24 formed in the NMOS region is removed by a predetermined surface etching process using the third photoresist pattern 27 as an etching mask. At this time, the pad oxide layer pattern 14 is also removed. By removing a predetermined thickness of the device isolation insulating film 24 formed in the NMOS region, even if the device isolation insulating film 24 in the PMOS region is lost in a subsequent cleaning and etching process, the device isolation insulating film 24 in the PMOS region and the NMOS region is removed. The thickness difference can be prevented from occurring. (See FIG. 10)
그 다음, 상기 제3감광막패턴(27)을 제거한다. (도 11 참조)Next, the third photoresist pattern 27 is removed. (See Figure 11)
그 후, 후속공정으로 세정공정을 실시한 다음, 게이트절연막을 형성한다.Thereafter, the cleaning step is performed in a subsequent step, and then a gate insulating film is formed.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 제조방법은, 트렌치를 이용하여 소자분리절연막을 형성한 다음, 반도체기판의 NMOS영역 및 PMOS영역에 p웰 및 n웰을 형성한 후 상기 NMOS영역 내의 소자분리절연막을 소정 두께 제거하여 PMOS영역과 NMOS영역 내의 소자분리절연막 두께 차이를 제거함으로써 PMOS영역에서 기생 누설전류가 발생하는 것을 방지하고, 게이트 절연막 보전 특성을 향상시키는 동시에 인버스 내로우 위드쓰 효과 및 서브쓰레셜드 험프현상을 방지하며 NMOS영역에서 게이트전극 형성 후 식각잔류물이 발생하는 것을 방지하여 소자의 동작 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming a device isolation insulating film using a trench, and then forming p wells and n wells in the NMOS region and the PMOS region of the semiconductor substrate, By removing a predetermined thickness of the device isolation insulating film to eliminate the difference in the thickness of the device isolation insulating film in the PMOS region and the NMOS region to prevent parasitic leakage current in the PMOS region, improve the gate insulating film integrity characteristics while at the same time inverse narrow with It prevents the subthreshold hump phenomenon and prevents the etching residue after the gate electrode is formed in the NMOS region, thereby improving the operation characteristics and reliability of the device.
Claims (5)
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| KR19990061023A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing method of semiconductor device |
| US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
| US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
| US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR19990061023A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Manufacturing method of semiconductor device |
| US5960276A (en) * | 1998-09-28 | 1999-09-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process |
| US6150235A (en) * | 2000-01-24 | 2000-11-21 | Worldwide Semiconductor Manufacturing Corp. | Method of forming shallow trench isolation structures |
| US6228726B1 (en) * | 2000-03-06 | 2001-05-08 | Taiwan Semiconductor Manufacturing Company | Method to suppress CMOS device latchup and improve interwell isolation |
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