KR100268907B1 - Isolation film of semiconductor device and method for forming the same - Google Patents
Isolation film of semiconductor device and method for forming the same Download PDFInfo
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- KR100268907B1 KR100268907B1 KR1019980008519A KR19980008519A KR100268907B1 KR 100268907 B1 KR100268907 B1 KR 100268907B1 KR 1019980008519 A KR1019980008519 A KR 1019980008519A KR 19980008519 A KR19980008519 A KR 19980008519A KR 100268907 B1 KR100268907 B1 KR 100268907B1
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000002955 isolation Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- 238000005468 ion implantation Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000009919 sequestration Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자에 관한 것으로 특히, STI(Shallow Trench Isolation)방식의 소자격리막에 있어서, 리키지 커런트(leakage current) 및 액티브영역의 감소를 방지하고, 우수한 브랙다운(breakdown)특성을 갖도록 하는데 적당한 반도체소자의 격리막 및 이의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. In particular, in a device isolation film of a shallow trench isolation (STI) method, it is suitable to prevent leakage of leakage current and active area and to have excellent breakdown characteristics. An isolation film of a semiconductor device and a method of forming the same.
통상, 소자격리막 형성방법중 고집적소자에 적당한 소자격리막으로 많이 사용되는 방법이 STI(Shallow Trench Isolation)방법이다.In general, a method of forming a device isolation film that is suitable for a high integration device is a STI (Shallow Trench Isolation) method.
이 경우, 실리콘기판을 식각한 후 산화(oxidation)와 여러번의 클리닝(cleaning)을 실시하게 되는데 액티브영역의 크기가 감소하게 되어 소자의 특성을 열악하게 만드는 원인이 되기도 한다.In this case, the silicon substrate is etched and then oxidized and cleaned several times. The size of the active region is reduced, which may cause deterioration of device characteristics.
이하, 종래기술에 따른 반도체소자의 격리막 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a separator of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1f는 종래 반도체소자의 격리막 형성방법을 설명하기 위한 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a separator of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체기판(11)상에 제 1 절연막(12)으로써 산화막을 성장시킨 후, 제 1 절연막(12)상에 제 2 절연막(13)으로써 실리콘질화막을 증착한다.As shown in FIG. 1A, after the oxide film is grown on the semiconductor substrate 11 with the first insulating film 12, the silicon nitride film is deposited on the first insulating film 12 with the second insulating film 13.
제 2 절연막(13)상에 포토레지스트(14)를 도포한 후, 노광 및 현상공정을 이용한 패터닝공정으로 소자격리영역을 정의한다.After the photoresist 14 is coated on the second insulating film 13, the device isolation region is defined by a patterning process using an exposure and development process.
패터닝된 포토레지스트(14)를 마스크로 이용한 식각공정으로 제 2 절연막(13)과 제 1 절연막(12)을 차례로 제거하여 반도체기판(11)을 노출시킨다.In the etching process using the patterned photoresist 14 as a mask, the second insulating layer 13 and the first insulating layer 12 are sequentially removed to expose the semiconductor substrate 11.
도 1b에 도시한 바와 같이, 포토레지스트(14)를 제거하고 클리닝(cleaning)작업을 수행한 후, 제 2 절연막(13)을 마스크로 이용한 식각공정으로 기판(11)을 소정깊이로 식각하여 트랜치(15)를 형성한다.As shown in FIG. 1B, after the photoresist 14 is removed and the cleaning process is performed, the trench 11 is etched to a predetermined depth by an etching process using the second insulating layer 13 as a mask. (15) is formed.
이후, 도 1c에 도시한 바와 같이, 트랜치(15)내면에 3 절연막(16)을 성장시킨 후, 필드이온주입을 실시한다.Thereafter, as shown in FIG. 1C, after the three insulating films 16 are grown on the inner surface of the trench 15, field ion implantation is performed.
여기서, 필드이온 주입을 위해 소자격리영역만을 노출시키기 위한 포토공정이 필요하게 되며 필드이온을 주입하고 포토레지스트를 제거한 다음, 클리닝작업을 수행한다.In order to implant the field ions, a photo process for exposing only the device isolation region is required. The field ions are implanted, the photoresist is removed, and the cleaning operation is performed.
따라서, N-필드 이온주입과 P-필드 이온주입에 따라 두 번의 포토공정이 필요하며 두 번의 클리닝공정도 필요하게 된다.Therefore, two photo processes are required according to N-field ion implantation and P-field ion implantation, and two cleaning processes are required.
이와같이, 필드이온을 주입한 다음 클리닝작업을 수행한 후, 트랜치(15)내에 소자격리를 위한 절연막을 형성하게 되는데, 절연막 형성전에 기판(11)상의 불순물을 제거 및 절연특성 향상을 위해 다시 클리닝작업을 수행한다.As such, after the field ion is injected and the cleaning operation is performed, an insulating film for isolation of the device is formed in the trench 15. The cleaning operation is again performed to remove impurities on the substrate 11 and to improve insulation properties before forming the insulating film. Do this.
이후, 기판(11)전면에 SOG(Spin On Glass)(17)(또는 USG:Undoped Silicate Glass)를 증착하여 트랜치(15)를 매립시킨다.Thereafter, the trench 15 is buried by depositing a spin on glass (SOG) 17 (or undoped silica glass) on the entire surface of the substrate 11.
상기 절연막 증착후, 열처리공정을 수행하게 되는데, 열처리를 위해 퍼니스(furnace)에 들어가기 이전에 클리닝작업을 수행한다.After the insulating film is deposited, a heat treatment process is performed, and a cleaning operation is performed before entering the furnace for heat treatment.
이는 장비관리 측면에서 필수적으로 거쳐야 하는 클리닝공정이다.This is an essential cleaning process in terms of equipment management.
이어서, 도 1d에 도시한 바와 같이, 기판(11)전면에 실리콘질화막(18)을 증착한 후, 포토공정을 이용하여 소자격리막이 형성될 부위에만 선택적으로 형성한다.Subsequently, as illustrated in FIG. 1D, the silicon nitride film 18 is deposited on the entire surface of the substrate 11, and then selectively formed only on a portion where the device isolation film is to be formed using a photo process.
이는 소자격리막 형성을 위한 CMP(Chemical Mechanical Polishing)공정시 SOG, 또는 USG와 제 2 절연막(13)의 물질인 실리콘질화막과의 식각선택비가 서로 상이함으로 인하여 단차가 발생하게 되는 문제를 해결하기 위한 것이다.This is to solve the problem that a step occurs due to the difference in etching selectivity between SOG or USG and silicon nitride film, which is a material of the second insulating film 13, during the chemical mechanical polishing (CMP) process for forming the device isolation film. .
즉, 실리콘질화막에 비해 SOG(17)가 더 빨리 식각되기 때문에 CMP공정을 완료하게 되면 소자격리막으로 사용되는 SOGG가 실리콘질화막보다 더 많이 식각되어 소자격리막의 특성을 저하시킬 수가 있기 때문이다.That is, since the SOG 17 is etched faster than the silicon nitride film, when the CMP process is completed, the SOGG used as the device isolation film is etched more than the silicon nitride film, thereby deteriorating the characteristics of the device isolation film.
따라서, 이러한 식각선택비에 따른 단차발생을 미연에 방지하게 위해 소자격리막이 형성될 부위의 SOG(17)상에 실리콘질화막(18)을 선택적으로 형성하는 것이다.Therefore, in order to prevent the generation of the step difference due to the etching selectivity, the silicon nitride film 18 is selectively formed on the SOG 17 at the portion where the device isolation film is to be formed.
이때, 상기 실리콘질화막(18)형성하기 이전에 클리닝작업을 수행한다.At this time, the cleaning operation is performed before the silicon nitride film 18 is formed.
상기 포토공정에 따른 포토레지스트를 제거한 후, 다시 클리닝작업을 수행한 후, 도 1e에 도시한 바와 같이, 화학기계적단면연마(CMP)공정을 수행하여 소자격리막(17a)을 형성한다.After removing the photoresist according to the photo process, the cleaning process is performed again, and as shown in FIG. 1E, a chemical mechanical cross-sectional polishing (CMP) process is performed to form the device isolation layer 17a.
이어, 도 1f에 도시한 바와 같이, 제 2 절연막(13)을 제거하고 클리닝작업을 수행하면 종래기술에 따른 소자격리막(17a) 형성공정이 완료된다.Subsequently, as shown in FIG. 1F, when the second insulating film 13 is removed and the cleaning operation is performed, the process of forming the device isolation film 17a according to the related art is completed.
그러나 상기와 같은 종래 반도체소자의 격리막 형성방법은 다음과 같은 문제점이 있었다.However, the method of forming a separator of the conventional semiconductor device as described above has the following problems.
첫째, 소자격리막 형성에 따른 여러번의 클리닝작업으로 인하여 액티브영역이 줄어들게 된다.First, the active region is reduced by several cleaning operations due to the formation of the device isolation layer.
둘째, 소자격리막과 액티브영역의 기판과의 스트레스가 심하여 필드 리키지 커런트가 증가함에 따라 소자의 특성이 저하된다.Second, as the field isolation current is severely stressed between the device isolation layer and the substrate in the active region, the device characteristics deteriorate.
셋째, 소자격리막 형성시 고집적화에 따른 고단차구조에서 트랜치내에 보이드(void)가 형성되거나 소자격리막 주변의 실리콘질화막을 제거한 후, 클리닝작업을 수행할 경우, 소자격리막의 에지부분에서 클리닝으로 인한 소자격리막의 손상을 초래하여 격리특성이 저하된다.Third, when a cleaning operation is performed after voids are formed in a trench or a silicon nitride film around the device isolation layer is removed in a high step structure due to high integration when the device isolation layer is formed, the device isolation layer due to cleaning at the edge of the device isolation film is cleaned. This can cause damage to the sequestration properties.
본 발명은 상기한 문제점을 해결하기 위해 안출한 것으로써, 여러번의 클리닝작업으로 인하여 액티브영역이 감소하는 것을 방지하고, 표면이 균일한 소자격리막을 형성하여 격리특성 및 소자의 신뢰성을 향상시킬 수 있는 반도체소자의 격리막 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, it is possible to prevent the active area is reduced due to a number of cleaning operations, to form a device isolation film with a uniform surface can improve the isolation characteristics and the reliability of the device It is an object of the present invention to provide a method for forming a separator of a semiconductor device.
도 1a 내지 1f는 종래 반도체소자의 격리막 형성방법을 설명하기 위한 공정단면도1A to 1F are cross-sectional views illustrating a method of forming a separator of a conventional semiconductor device.
도 2는 본 발명에 따른 반도체소자의 격리막구조를 설명하기 위한 단면도2 is a cross-sectional view for explaining a separator structure of a semiconductor device according to the present invention.
도 3a 내지 3f는 본 발명에 따른 반도체소자의 격리막 형성방법을 설명하기 위한 공정단면도3A to 3F are cross-sectional views illustrating a method of forming an isolation layer of a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31 : 반도체기판 36 : 도전성측벽31 semiconductor substrate 36 conductive side wall
36a : 절연측벽 37a : 소자격리막36a: insulation side wall 37a: device isolation film
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 격리막은 트랜치가 형성된 반도체 기판과, 상기 트랜치내 양측면에 형성된 도전성 측벽과, 상기 도전성 측벽상에 형성된 절연측벽과, 상기 절연측벽상에 형성된 절연막을 포함하여 구성되고 본 발명의 반도체소자의 격리막 형성방법은 기판상에 절연패턴을 형성하는 공정과, 상기 절연패턴을 마스크로 상기 기판에 트랜치를 형성하는 공정과, 상기 기판의 스트레스 완화를 위해 상기 트랜치 양측면에 스트레스 버퍼층을 형성하는 공정과, 트랜치 하부의 기판에 필드이온을 주입하고 소자격리막 형성을 위한 절연막을 증착하는 공정과, 상기 소자격리막이 형성될 부위의 절연막상에 상기 절연막과의 식각선택비를 갖는 다른 절연막을 패터닝하는 공정과, 상기 절연패턴이 노출되도록 평탄화시킨 후, 상기 절연패턴을 제거하여 소자격리막을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The isolation film of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate having a trench formed therein, conductive sidewalls formed on both sides of the trench, an insulating side wall formed on the conductive sidewall, and an insulating film formed on the insulating side wall. The method for forming an isolation layer of a semiconductor device according to the present invention includes forming an insulating pattern on a substrate, forming a trench in the substrate using the insulating pattern as a mask, and reducing the trench to relieve stress of the substrate. Forming a stress buffer layer on both sides, injecting field ions into the substrate under the trench and depositing an insulating film for forming an isolation layer, and an etching selectivity with the insulating layer on the insulating layer in the region where the isolation layer is to be formed Patterning another insulating film having a planarization and planarizing the insulating pattern to expose the insulating pattern; And removing the insulating pattern to form a device isolation film.
이하, 본 발명의 반도체소자 격리막 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of forming a semiconductor device isolation film of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체소자의 격리막 구조를 설명하기 위한 단면도이다.2 is a cross-sectional view for explaining a separator structure of a semiconductor device according to the present invention.
도 2에 도시한 바와 같이, 트랜치를 갖는 기판(31)과, 트랜치내에 형성된 소자격리막(37a)과, 상기 트랜치의 양측면에 형성된 도전성측벽(36)과, 상기 도전성측벽(36)과 소자격리막(37a)사이에 형성된 절연측벽(36a)을 포함하여 구성된다.As shown in Fig. 2, the substrate 31 having the trench, the device isolation film 37a formed in the trench, the conductive side wall 36 formed on both sides of the trench, the conductive side wall 36 and the device isolation film ( And an insulating side wall 36a formed between 37a).
여기서, 상기 도전성측벽(36)은 폴리실리콘, 비정질실리콘, 인-시튜 도핑된 폴리실리콘, 인-시튜 도핑된 비정질실리콘 등을 포함한다.Here, the conductive side wall 36 includes polysilicon, amorphous silicon, in-situ doped polysilicon, in-situ doped amorphous silicon, and the like.
이와같이 구성된 본 발명의 반도체소자 격리막 형성방법을 설명하면 다음과 같다.Referring to the semiconductor device isolation film forming method of the present invention configured as described above are as follows.
도 3a 내지 3f는 본 발명의 반도체소자의 격리막 형성방법을 설명하기 위한 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of forming an isolation film of a semiconductor device of the present invention.
도 3a에 도시한 바와 같이, 반도체기판(31)상에 제 1 절연막(32)을 증착하고, 제 1 절연막(31)상에 제 2 절연막(33)으로써 실리콘질화막을 증착한다.As shown in FIG. 3A, a first insulating film 32 is deposited on the semiconductor substrate 31, and a silicon nitride film is deposited on the first insulating film 31 as the second insulating film 33.
제 2 절연막(33)상에 포토레지스트(34)를 도포한 후, 노광 및 현상공정으로 패터닝하여 소자격리영역을 정의한다.After the photoresist 34 is coated on the second insulating film 33, the device isolation region is defined by patterning the photoresist 34 by exposure and development processes.
패터닝된 포토레지스트(34)를 마스크로 이용한 식각공정으로 제 2 절연막(33)과 제 1 절연막(32)을 선택적으로 제거하여 기판(31)을 노출시킨다.The substrate 31 is exposed by selectively removing the second insulating film 33 and the first insulating film 32 by an etching process using the patterned photoresist 34 as a mask.
도 3b에 도시한 바와 같이, 상기 포토레지스트(34)를 제거한 후, 클리닝작업을 수행하고, 제 2 절연막(33)을 마스크로 이용한 식각공정으로 노출된 기판(31)을 소정깊이로 식각하여 트랜치(35)를 형성한다.As shown in FIG. 3B, after the photoresist 34 is removed, a cleaning operation is performed, and the substrate 31 exposed by the etching process using the second insulating layer 33 as a mask is etched to a predetermined depth to form a trench. (35) is formed.
이후, 트랜치(35)를 포함한 기판(31)전면에 도전층을 형성한 후 에치백하여 도전성측벽(36)을 형성한다.Thereafter, the conductive layer is formed on the entire surface of the substrate 31 including the trench 35 and then etched back to form the conductive side wall 36.
여기서, 상기 도전층의 물질은 폴리실리콘 또는 비정질실리콘 또는 인-시튜 도핑된 폴리실리콘 또는 인-시튜 도핑된 비정질실리콘중 어느하나를 사용한다.Here, the material of the conductive layer uses either polysilicon or amorphous silicon or in-situ doped polysilicon or in-situ doped amorphous silicon.
그리고 도전성측벽(36)형성을 위한 에치백시에 트랜치(35)하면이 소정깊이로 식각된다.In addition, the bottom surface of the trench 35 is etched to a predetermined depth during etching back to form the conductive side wall 36.
이와같이, 트랜치(35)양측면에 도전성측벽(36)을 형성한 후, 도 3c에 도시한 바와 같이, 산화공정을 진행하면, 상기 도전성측벽(36)상에 절연측벽(36a)이 형성된다.In this way, after the conductive side walls 36 are formed on both sides of the trench 35, as shown in FIG. 3C, the oxidation side walls 36a are formed on the conductive side walls 36 when the oxidation process is performed.
즉, 도전성측벽(36)은 실리콘을 함유하고 있으므로 O2가스를 주입하면 실리콘과 O2가스가 반응하여 실리콘산화막으로 이루어지는 절연측벽(36a)이 형성된다.That is, since the conductive side wall 36 contains silicon, when the O 2 gas is injected, the insulating side wall 36a made of a silicon oxide film is formed by the reaction between the silicon and the O 2 gas.
이때, 상기 트랜치(35)하면에도 산화공정에 의한 열산화막(36b)이 형성된다.At this time, a thermal oxide film 36b formed by an oxidation process is formed on the lower surface of the trench 35.
여기서, 상기 도전측벽(36) 및 절연측벽(36a)은 후에 형성되는 소자격리막에 의한 기판(31)의 스트레스를 최소화하기 위한 스트레스 버퍼층으로 사용한다.Here, the conductive side wall 36 and the insulating side wall 36a are used as a stress buffer layer for minimizing the stress of the substrate 31 by the device isolation film formed later.
한편, 상기 도전성측벽(36a)대신에 고온에서 화학기상증착법(CVD:Chemical Vapor Deposition)에 의한 절연막을 형성하는 공정이 적용가능하며 절연막을 형성하는 경우, 별도로 절연측벽(36a)을 형성하기 위한 공정이 필요치 않다.Meanwhile, a process of forming an insulating film by chemical vapor deposition (CVD) at a high temperature instead of the conductive side wall 36a is applicable. In the case of forming the insulating film, a step for forming the insulating side wall 36a separately This is not necessary.
이어, 도 3d에 도시한 바와 같이, N-필드 및 P-필드 이온주입을 실시한다.Next, as shown in FIG. 3D, N-field and P-field ion implantation are performed.
따라서, 각 필드이온주입에 따른 두 번의 포토공정이 필요하게 되어 이에 포토레지스트 제거후 두 번의 클리닝작업을 수행한다.Therefore, two photo processes are required for each field ion implantation, thereby performing two cleaning operations after removing the photoresist.
이어, 종래와 마찬가지로 소자격리막으로 사용될 절연막을 증착하기 이전에 클리닝작업을 수행한 다음, 상기 트랜치(35)를 포함한 기판(31)전면에 소자격리막으로 사용될 제 3 절연막(37)을 증착한다.Subsequently, a cleaning operation is performed prior to depositing an insulating film to be used as the device isolation film, and then a third insulating film 37 to be used as the device isolation film is deposited on the entire surface of the substrate 31 including the trench 35.
이때, 제 3 절연막(37)으로써는 SOG 또는 USG 등을 포함한다.At this time, the third insulating film 37 includes SOG or USG.
상기 제 3 절연막(37) 증착후, 열처리공정을 수행하게 되는데, 열처리를 위해 퍼니스(furnace)에 들어가기 이전에 클리닝작업을 수행한다.After the deposition of the third insulating layer 37, a heat treatment process is performed, and a cleaning operation is performed before entering the furnace for heat treatment.
이는 장비관리 측면에서 필수적으로 거쳐야 하는 클리닝공정이다.This is an essential cleaning process in terms of equipment management.
이어서, 기판(31)전면에 제 4 절연막(38)으로써 실리콘질화막을 증착한 후, 포토공정을 이용하여 소자격리막이 형성될 부위에만 선택적으로 형성한다.Subsequently, after the silicon nitride film is deposited on the entire surface of the substrate 31 with the fourth insulating film 38, the silicon nitride film is selectively formed only on the portion where the device isolation film is to be formed by using a photo process.
이는 소자격리막 형성을 위한 CMP(Chemical Mechanical Polishing)공정시 SOG, 또는 USG와 제 2 절연막(33)의 물질인 실리콘질화막과의 식각선택비가 서로 상이함으로 인하여 단차가 발생하게 되는 문제를 해결하기 위한 것이다.This is to solve the problem that a step occurs due to different etching selectivity between SOG or USG and silicon nitride film, which is a material of the second insulating film 33, during the chemical mechanical polishing (CMP) process for forming the device isolation film. .
즉, 제 2 절연막(33)인 실리콘질화막에 비해 제 3 절연막(37)인 SOG가 더 빨리 식각되기 때문에 CMP공정을 완료하게 되면 제 3 절연막(37)인 SOG가 제 2 절연막(33)보다 더 빨리 식각되어 결국, 소자격리막의 특성을 저하시킬 수가 있기 때문이다.That is, since the SOG, which is the third insulating film 37, is etched faster than the silicon nitride film, which is the second insulating film 33, when the CMP process is completed, the SOG, the third insulating film 37, is more than the second insulating film 33. This is because it can be quickly etched and eventually degrades the device isolation film.
따라서, 이러한 식각선택비에 따른 단차발생을 미연에 방지하게 위해 소자격리막이 형성될 부위의 제 3 절연막(37)상에 제 4 절연막(38)인 실리콘질화막을 선택적으로 형성하는 것이다.Accordingly, in order to prevent the generation of the step difference due to the etching selectivity, the silicon nitride film, which is the fourth insulating film 38, is selectively formed on the third insulating film 37 at the portion where the device isolation film is to be formed.
이때, 상기 제 4 절연막(38)형성하기 이전에 클리닝작업을 수행한다.In this case, a cleaning operation is performed before forming the fourth insulating layer 38.
상기 포토공정에 따른 포토레지스트를 제거한 후, 다시 클리닝작업을 수행한 후, 도 3e에 도시한 바와 같이, 화학기계적단면연마(CMP)공정을 수행하여 소자격리막(37a)을 형성한다.After removing the photoresist according to the photo process, the cleaning process is performed again, and as shown in FIG. 3E, a chemical mechanical cross-sectional polishing (CMP) process is performed to form the device isolation layer 37a.
이어, 도 3f에 도시한 바와 같이, 제 2 절연막(33)을 제거하면 본 발명에 따른 소자격리막(37a)형성공정이 완료된다.3F, when the second insulating film 33 is removed, the process of forming the device isolation film 37a according to the present invention is completed.
이상 상술한 바와 같이, 본 발명의 반도체소자의 격리막 및 이의 형성방법은 다음과 같은 효과가 있다.As described above, the isolation film and the method of forming the semiconductor device of the present invention has the following effects.
첫째, 기판을 식각하여 트랜치를 형성한 후, 곧바로 측벽을 형성하기 때문에 산화공정 및 여러번의 클리닝에도 불구하고 액티브영역이 감소되지 않아 액티브영역을 극대화시킬 수 있다.First, since the sidewalls are formed immediately after the trench is formed by etching the substrate, the active area is not reduced despite the oxidation process and several cleanings, thereby maximizing the active area.
둘째, 소자격리막 형성시 고집적화에 따른 고단차구조를 현저히 개선하여 보이드(void)가 없는 균일한 소자격리막을 얻을 수 있다.Second, when the device isolation layer is formed, a high step structure due to high integration is remarkably improved to obtain a uniform device isolation layer without voids.
셋째, 소자격리막으로 사용하는 SOG 또는 USG막과 액티브영역의 기판간에 측벽을 사용하여 스트레스 버퍼층을 형성함으로써 필드 리키지 커런트 감소 및 브랙다운 특성이 향상되어 소자의 특성을 개선시킬 수 있다.Third, a stress buffer layer is formed between the SOG or USG film used as the device isolation film and the substrate of the active region to form a stress buffer layer, thereby reducing field leakage current and improving breakdown characteristics, thereby improving device characteristics.
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| KR100835472B1 (en) * | 2002-06-29 | 2008-06-04 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
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| KR100451512B1 (en) * | 2002-03-26 | 2004-10-06 | 주식회사 하이닉스반도체 | method for forming isolation layer |
| KR100835472B1 (en) * | 2002-06-29 | 2008-06-04 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
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