KR20010019185A - Method for fabrication a trench isolation - Google Patents

Abstract

PURPOSE: A method for manufacturing a trench isolation is provided to increase a threshold voltage and current, to improve a refresh characteristic and to reduce dent of a nitride layer liner, by forming polymer in an inner wall of an opening to increase an active region. CONSTITUTION: The first insulating layer, the second insulating layer and the third insulating layer sequentially formed on a semiconductor substrate(100) are patterned to form an opening. An insulating material is formed on an inner wall of the opening to reduce the width of the opening. A trench is formed in the semiconductor substrate exposed to the opening. The insulating material, the third insulating layer and the second insulating layer are eliminated.

Description

Trench isolation manufacturing method {METHOD FOR FABRICATION A TRENCH ISOLATION}

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing trench isolation.

With the high integration of semiconductor devices, the manufacturing process is becoming more complicated. Also, in isolation between unit devices, development of isolation technology having excellent electrical characteristics in a small area is required. Therefore, as a way to solve the problems of LOCOS (LOCal Oxidation of Silicon) isolation technology, Shallow Trench Isolation (STI) technology is being researched and applied to the process. The STI is a trench isolation method in which a silicon substrate is etched to a depth necessary for isolation to form a trench, the trench is filled with a chemical vapor deposition (CVD) oxide film, and then planarized to realize device isolation.

However, in the conventional trench isolation method, stress is generated due to the difference in the coefficient of thermal expansion between the silicon filling the trench and the silicon. In addition, the trench inner wall is oxidized in a subsequent oxidation process, and stress is applied to the trench inner wall due to volume expansion of the oxide film. This generated stress results in a defect in the silicon lattice in the trench, which degrades the insulating properties of the trench isolation.

Therefore, in order to improve such a problem, in the current trench isolation process, a nitride film liner is formed in the trench before the trench isolation film is formed. The nitride film liner inhibits oxidation of the inner wall of the trench to prevent stress generated in the inner wall of the trench. However, in a subsequent phosphate strip process, the nitride film liner on the trench is etched together to generate dents.

1A to 1D are cross-sectional views sequentially showing processes of a trench isolation manufacturing method of a conventional semiconductor device.

Referring to FIG. 1A, in the trench isolation manufacturing method of the conventional semiconductor device, first, a pad oxide film, a pad nitride film, and an anti-reflective coating (ARC) are formed on a semiconductor substrate 1. A photoresist pattern 5 is formed on the antireflection film. The photoresist pattern 5 is used to dry etch the anti-reflection film, pad nitride film and pad oxide film. The dry etched anti-reflection film 4, the pad nitride film 3 and the pad oxide film 2 are used as a trench etching mask of a multi-layer structure for forming a trench in a semiconductor substrate.

Referring to FIG. 1B, the photoresist pattern 5 is removed. The trench etch mask is used to form a trench in the semiconductor substrate 1.

Referring to FIG. 1C, an oxide film 6 is formed on the bottom and the inner wall of the trench to remove silicon lattice defects in the trench generated when the trench is formed. The nitride film liner 7 is formed on the oxide film 6 and the semiconductor substrate 1 in the trench. A trench isolation film 8 is formed on the nitride film liner 7 of the semiconductor substrate 1 so as to completely fill the trench. The trench isolation layer 8 is planarized by using the pad nitride layer 3 as an etch stop layer.

Referring to FIG. 1D, when the pad nitride film 3 is removed by a phosphate strip process, trench isolation is completed. However, in the phosphate strip process for removing the pad nitride film 3, the nitride film liner 7 is etched together because it is the same material as the pad nitride film 3. In addition, since the over-etching is performed to completely remove the pad nitride film 3, the nitride film liner 7 is also etched to generate a recess. That is, the nitride film liner 7 in the trench upper edge portion of the semiconductor substrate 1 is etched to easily generate dents 9. These dents 9 reduce the refresh characteristics of the device, or in the subsequent gate oxide film formation and gate poly etching processes, respectively, such as gate oxide thinning and gate poly bridge, etc. It will cause a problem.

It is an object of the present invention to provide a trench isolation manufacturing method that prevents dents in nitride film liners.

1A and 1B are flowcharts sequentially showing processes of a trench isolation manufacturing method of a conventional semiconductor device. And

2A through 2E are flow charts that sequentially illustrate the processes of the trench isolation manufacturing method in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100 semiconductor substrate 102 pad oxide film

104: nitride film 106: antireflection film

108 photoresist film 200 polymer

204: oxide film 206: nitride film liner

208: separator

According to the present invention for achieving the above object, a first insulating film, a second insulating film, and a third insulating film are sequentially formed on a semiconductor substrate. The first insulating film, the second insulating film, and the third insulating film are patterned to form an opening. An insulating material is formed on the inner wall of the opening to reduce the width of the opening by twice the thickness of the insulating material. The semiconductor substrate exposed to the opening is etched to form a trench. After removing the third insulating layer and the insulating material, the second insulating layer is removed. Fill the trench with isolation material.

(Example)

2A to 2D, an embodiment of the present invention will be described in detail.

Referring to FIG. 2A, a pad oxide film is formed on the semiconductor substrate 100 to a thickness of about 110 GPa. A nitride film SiN is formed on the pad oxide film to a thickness of 1500 kPa. An anti-reflective coating (ARC) is formed on the nitride film to a thickness of 600 kPa. The anti-reflection film serves to ensure the uniformity of the pattern size in the photographic process.

Next, a photoresist pattern 108 is formed on the anti-reflection film through a conventional photolithography process. The photoresist pattern 108 is used to dry etch the pad oxide film, the nitride film and the anti-reflection film. The stacked structure of the photoresist pattern 108 and the pad oxide layer 102, the nitride layer 104, and the anti-reflection layer 106 etched by the dry etching may be used to form an opening for forming a trench on the semiconductor substrate 100. Form.

Referring to FIG. 2B, a polymer 200 is formed on the opening inner wall by etching the opening inner wall by an oxide etch recipe while the semiconductor substrate 100 is exposed. The formation of the polymer 200 serves to reduce the width of the opening inner wall by twice the thickness L of the polymer 200, and further, the edge 202 of the upper portion of the trench has a slope. It is effective to have. Therefore, the width of the opening is reduced, so that the isolation region of the trench is reduced, and the width of the active region is relatively increased by the thickness L of the polymer 200. As such, the increase of the active region increases the threshold voltage and the current of the cell transistor, thereby improving the characteristics of the cell transistor. In addition, the ion implantation amount is reduced on the active region, thereby improving the refresh characteristics of the transistor. In addition, an increase in the active area results in a decrease in the dent of the nitride film liner generated in a subsequent phosphate strip process. In addition, since the edge portion 202 of the upper portion of the trench has an inclination, it is possible to prevent a junction leak or the like that occurred in a conventional sharp corner.

Next, the semiconductor substrate 100 exposed to the opening is dry-etched while the photoresist pattern 108 is not removed. By the dry etching, trenches having a depth of 2500 Pa to 4000 Pa are formed.

Referring to FIG. 2C, after the photoresist pattern 108 and the polymer 200 are removed, the anti-reflection film 106 is continuously removed by dry etching.

In the chemical mechanical polishing (CMP) process, the anti-reflection film 106 has a significantly reduced etching rate compared to the nitride film 104. This is because densification of the anti-reflection film 106 occurs at the same time because an annealing process for densification of the trench isolation film is performed in a step before the chemical mechanical polishing process. Therefore, if the anti-reflective film 106 is not removed before the heat treatment process and the heat treatment process is to be removed in the CMP process, the excessive CMP process must be sufficiently performed. However, this excessive CMP process significantly worsens the uniformity of the trench upper oxide film. Therefore, it is advantageous that the anti-reflection film 106 is dry etched in the present process step, that is, after the photoresist pattern 108 and the polymer 200 are removed.

Referring to FIG. 2D, the dry etching for forming the trench is a dry etching using plasma. Since the plasma dry etching uses ions having high energy and high directionality, defects occur in the silicon lattice in the trench due to the impact of the ions. Accordingly, an oxide film 204 is formed in the bottom and inner walls of the trench in a thickness of 20 kV to 150 kV to remove silicon lattice defects in the trench generated when the trench is formed.

Next, stress is generated between the semiconductor substrate 100 in the trench and the trench isolation layer to be formed in a later process. Therefore, a nitride film liner 206 for preventing the stress is formed on the oxide film 204 and the nitride film 104 in a thickness of 20 kPa to 150 kPa.

Next, a trench isolation layer 208 is formed on the entire surface of the semiconductor substrate 100 to completely fill the trench. The trench isolation layer 208 is a USG film formed by plasma enhanced chemical vapor deposition (PECVD). At this time, the formation of the polymer 200 of the present invention forms the step of forming the nitride film 104 / semiconductor substrate 100 / trench. As a result, the aspect ratio is reduced. Therefore, no void is generated in the trench when the isolation layer 208 is formed in the trench.

Next, the trench isolation layer 208 on the semiconductor substrate 100 is planarized etched through a chemical mechanical polishing process. The nitride film 104 is used as an etch stop layer.

Referring to FIG. 2E, the trench is completed when the nitride film 104 is removed by a phosphate strip process. However, the dent 300 is also etched with the nitride film liner 206 which is the same material as the nitride film 104. However, as the active region increases by the thickness L of the polymer 200, the etching rate of phosphoric acid penetrating into the nitride liner during the phosphoric acid strip process decreases, so that the amount of the dent 300 of the nitride liner 206 is reduced.

According to the present invention, a polymer is formed in the opening inner wall for forming the trench on the semiconductor substrate, thereby increasing the active area. Increasing the active area has the effect of increasing the active area of the first cell transistor to increase the threshold voltage and current and to improve the refresh characteristics. Second, the increase of the active region reduces the etching rate of phosphoric acid penetrating into the nitride film liner in the phosphoric acid strip process, thereby reducing the dent of the nitride film liner. The nitride film / semiconductor substrate / trench is formed in a step shape before the third trench isolation film is filled, thereby preventing voids in the trench when the isolation film is filled into the trench.

Claims (3)

Patterning the first insulating film, the second insulating film, and the third insulating film sequentially formed on the semiconductor substrate to form an opening; Forming an insulating material on the inner wall of the opening to reduce the width of the opening; Forming a trench in the semiconductor substrate exposed to the opening; Removing the insulating material, the third insulating film and the second insulating film. The method of claim 1, And removing the insulating material, the third insulating film, and the second insulating film, and then filling the insulating material in the trench. The method of claim 1, And the third insulating film is a photoresist film and the insulating material is a polymer.