KR100420701B1 - Method of forming an isolation film in semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a device isolation layer of a semiconductor device, by forming a trench by a multi-step etching process and a high density plasma deposition (HDP) process to improve the insulating properties between the devices and through the continuous rounding oxidation through the upper corner of the trench The present invention provides a method of forming a device isolation layer of a semiconductor device capable of improving the rounding characteristic of the device and improving the electrical characteristics and the reliability of the device.

Description

Method of forming an isolation film in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film for shallow trench isolation (STI) during a manufacturing process of a highly integrated device of 0.13 μm tech or less.

1A to 1D are cross-sectional views illustrating a method of forming a device isolation film according to the related art.

Referring to FIG. 1A, a pad oxide film 2 and a nitride film 3 are sequentially deposited on a Si substrate 1. After the photoresist 4 is applied onto the silicon substrate 1 on which the pad oxide film 2 and the nitride film 3 are deposited, the trench 5 is formed through an exposure process using a photo mask. Define.

Referring to FIG. 1B, a trench 5 having a shallow trench isolation (STI) structure is sequentially formed by etching the nitride film 3, the pad oxide film 2, and the silicon substrate using the photoresist 4 as a barrier. After forming the photoresist 4 on the nitride film 3 is removed. In forming the trench 5, the silicon substrate 1 is etched to have a specific inclination of about 75 to 85 degrees.

Referring to FIG. 1C, in order to compensate for etch damage of the sidewalls of the trenches 5 of the STI structure, sidewall oxidation is performed in the trenches 5 of the STI structure to form a thermal oxide film 6. In order to fill the trench 5 of the STI structure in which the thermal oxide film 6 is formed, a high density plasma (HDP) oxide film 7 is deposited on the silicon substrate 1 and then a planarization process is performed.

Specifically, an STI CMP process for removing the HDP oxide layer 7 on the nitride layer 3 using the nitride layer 3 as an etch stop layer after depositing the HDP oxide layer 7 so as not to form an empty space in the trench 5. By flattening.

Referring to FIG. 1D, the floating gate region is defined by removing the nitride layer 3 and the pad oxide layer 2 and performing wet etching before forming the VT screen oxide layer (not shown). However, due to the wet etching, the HDP oxide layer 7 is recessed and at the same time, a moat in which the active region of the HDP oxide layer 7 is recessed is generated.

The formation of the HDP oxide film moat generates a leakage current, and an element defect is generated by the leakage current. In addition, the STI method, which has been used as a device isolation method until now, forms a trench by etching a field region, and then fills the trench with an HDP oxide film.

However, this technique performs the etching process with some inclination when etching the field region due to the buried trench in the HDP deposition process. The slope of the etching process formed at this time is a factor that has a decisive influence on the high integration of semiconductors in ultrafine devices.

Therefore, the ultra-fine circuit device is a limitation of the technology through such etching, and to overcome this, it must proceed without tilt during STI etching. Due to the trench forming process limit, there are many problems in the HDP deposition for sufficient device insulation depth and latch-up prevention.

Accordingly, an object of the present invention is to provide a device isolation film having a sufficient depth and a device depth by forming a trench without a slope through a multi-step etching process and HDP deposition in forming the trench to solve the above problems.

1A to 1D are cross-sectional views illustrating a method of forming a device isolation layer in accordance with the prior art.

2A to 2I are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 11: semiconductor substrate 2, 12: pad oxide film

3, 13: nitride film 4, 14: photoresist pattern

5, 15, 18, 21: trench 6: thermal oxide film

7, 24: HDP oxide film 16, 19, 22: rounding oxide film

17, 20, 23: trench sidewall spacer

Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate, forming a first trench by etching the nitride film, the pad oxide film, and the semiconductor substrate, and then forming a first rounding oxide film inside the first trench; Depositing a first HDP oxide layer on the structure and forming first sidewall spacers on the sidewalls of the first trenches; forming a second trench by etching the semiconductor substrate under the first trenches; Forming a second rounding oxide layer, depositing a second HDP oxide layer over the entire structure, and then forming a second sidewall spacer on the sidewalls of the second trench; etching a semiconductor substrate under the second trench; Forming a third rounding oxide layer inside the third trench after depositing the third HDP oxide layer on the entire structure Forming a third sidewall spacer on the third trench sidewalls, depositing a fourth HDP oxide film on the entire structure, performing a planarization process, and removing the nitride film. It provides a method for forming a device separator of the.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

2A to 2I are cross-sectional views illustrating a method of forming an isolation layer in a semiconductor device according to the present invention.

Referring to FIG. 2A, a pad oxide film 12 and a nitride film 13 are sequentially deposited on a Si substrate 11. After the photoresist is applied onto the silicon substrate 11 on which the pad oxide film 12 and the nitride film 13 are deposited, the photoresist pattern 14 is formed through an exposure process using a photo mask.

The pad oxide film 12 is formed to a thickness of 100 to 180 Å to be used as an etch stop layer for stress relaxation of the silicon substrate 11 and the nitride film 13 and for etching the nitride film 13. The nitride film 13 is formed to a thickness of 1000 to 1500 Å to serve as a barrier for the etch stationary layer and the spacer etch in a subsequent CMP process. The photoresist pattern 14 distinguishes the active region and the field region of the device.

Referring to FIG. 2B, the first trench 15 is formed in the field region by performing a first isolation etching process using the photoresist pattern 14 as an isolation (ISO) mask. The photoresist used for the photoresist pattern 14 is removed.

The pad oxide film 12, the nitride film 13, and the silicon substrate 11 in the field region are removed by the first isolation etching process. In this case, about one third of the depth of the device isolation layer to be formed is etched from the surface of the silicon substrate 11 defined as the field region by the first isolation etching process. If the depth of the device isolation layer to be formed is 3600Å, the silicon substrate 11 removed by the first isolation etching process is etched by a depth of about 1200Å from the surface of the silicon substrate 11.

Referring to FIG. 2C, after the pretreatment cleaning process, a first rounding oxide process is performed at a temperature of 1050 ° C. to form a first rounding oxide layer 16 having a thickness of 90 to 110 kPa.

The pretreatment washing step was performed at 50 ° C. for 10 minutes using SC-1 having a ratio of NH ₄ OH: H ₂ O ₂ : H ₂ O 1: 5: 50, and then the ratio of HF: H ₂ O was 99: Wash for 180 seconds using 1 phosphorus solution.

In addition, by forming a round oxide, the plasma damage of the subsequent HDP deposition process can be alleviated and the trench top corner can be rounded.

Referring to FIG. 2D, a first HDP oxide film is formed to a thickness of about 3000 kPa over the entire structure, and then annealed for 30 minutes under a temperature of about 1000 ° C. and an N ₂ gas atmosphere. As such, the annealing process is performed to densify the HDP oxide film so that the film quality of the HDP oxide film has an etching characteristic similar to that of the thermal oxide film.

The first trench spacers 17 may be formed by performing a maskless front etching process on the first HDP oxide layer.

Referring to FIG. 2E, the second trench 18 is formed by removing the exposed silicon substrate 11 in the field region by performing a second isolation etching process using the first trench spacer 17 as an etching barrier. After the pretreatment cleaning step, the second rounding oxidation step is performed at a temperature of 1050 ° C. to form a second rounding oxide film 19 having a thickness of about 100 kPa.

At this time, about one third of the depth of the device isolation layer to be formed is etched from the surface of the silicon substrate 11 exposed in the field region by the second isolation etching process. If the device isolation layer to be formed has a depth of 3600 μs, the silicon substrate 11 removed by the second isolation etching process is etched by a depth of about 1200 μs from the surface of the exposed silicon substrate 11 in the field region. Therefore, the silicon substrate 11 in the field region is etched by about two thirds of the depth of the device isolation layer to be formed by the first isolation and the second isolation etching processes.

After the second isolation etching step, the pretreatment washing step is performed at 50 ° C. for 10 minutes using SC-1 having a ratio of NH ₄ OH: H ₂ O ₂ : H ₂ O of 1: 5: 50.

Referring to FIG. 2F, a second HDP oxide film is formed on the entire structure to a thickness of about 3000 kPa, and then annealed for 30 minutes under a temperature of about 1000 ° C. and an N ₂ gas atmosphere. The second trench spacer 20 is formed by performing a mask-less front etching process on the second HDP oxide layer.

Referring to FIG. 2G, the third trench spacer 20 is removed by performing a third isolation etching process using the second trench spacer 20 as an etching barrier to remove the exposed silicon substrate 11 in the field region. After the pretreatment cleaning step, the third rounding oxidation step is performed at a temperature of 1050 ° C. to form a third rounding oxide film 22 having a thickness of about 100 kPa.

At this time, about one third of the device isolation film depth to be formed is etched from the surface of the exposed silicon substrate 11 in the field region by the third isolation etching process. If the device isolation film to be formed has a depth of 3600Å, the silicon substrate 11 removed by the third isolation etching process is etched by a depth of about 1200Å from the surface of the exposed silicon substrate 11 in the field region. Accordingly, the silicon substrate in the field region is etched by the depth of the device isolation layer to be formed by the first isolation, the second isolation, and the third isolation etching process.

After the third isolation etching step, the pretreatment cleaning step is performed at 50 ° C. for 10 minutes using SC-1 having a ratio of NH ₄ OH: H ₂ O ₂ : H ₂ O 1: 5: 50.

Referring to FIG. 2H, a third HDP oxide film is formed on the entire structure to a thickness of about 3000 kPa, and then annealed for 30 minutes under a temperature of about 1000 ° C. and an N ₂ gas atmosphere. The third trench spacer 23 may be formed by performing a maskless front etching process on the third HDP oxide layer.

Referring to FIG. 2I, after forming the fourth HDP oxide layer 24 to a thickness of about 6000 kPa over the entire structure, annealing is performed for 30 minutes under a temperature of about 1000 ° C. and an N ₂ gas atmosphere. A planarization process using CMP is performed to remove portions of the fourth HDP oxide film 24, the nitride film 13, and the first trench spacer 17 so that the thickness of the field region is about 750 mm higher than the thickness of the active region. The isolation film of the semiconductor element is formed by removing the nitride film 13 remaining after the above planarization process.

As described above, the present invention can increase the degree of integration of the device and improve the insulating property between devices by forming a device isolation layer without gradient and forming a device isolation layer having a sufficient depth through a multi-step etching process and HDP deposition.

In addition, the rounding oxidation process improves the rounding characteristics of the upper corners of the trenches to reduce parasitic currents, prevent GOI (Gate Oxide Integrity) deterioration, reverse narrowing effect and sub-throw hump phenomenon, thereby improving the electrical characteristics of the device Reliability can be improved.

Claims (12)

Sequentially forming a pad oxide film and a nitride film on the semiconductor substrate; Etching the nitride film, the pad oxide film, and the semiconductor substrate to form a first trench, and then forming a first rounding oxide film inside the first trench; Depositing a first HDP oxide layer over the entire structure and forming first sidewall spacers on the first trench sidewalls; Etching a semiconductor substrate under the first trench to form a second trench, and then forming a second rounding oxide layer inside the second trench; Forming a second sidewall spacer on the sidewalls of the second trench after depositing a second HDP oxide layer over the entire structure; Etching the semiconductor substrate under the second trench to form a third trench, and then forming a third rounding oxide layer inside the third trench; Depositing a third HDP oxide layer over the entire structure and forming third sidewall spacers on the third trench sidewalls; Depositing a fourth HDP oxide layer on the entire structure and then performing a planarization process; And And removing the nitride film. The method of claim 1, Wherein the first to third HDP oxide layers are deposited to a thickness of 2500 to 3500 kV. The method of claim 1, And performing a heat treatment process for about 30 minutes at 1000 ° C. and N ₂ gas after the deposition of the first to third HDP oxide films. delete The method of claim 1, And the fourth HDP oxide film is deposited to a thickness of 5500 to 6500 kV. The method of claim 1, Wherein the first to third rounding oxides are formed to a thickness of 90 to 110 kPa under a temperature of about 1000 to 1100 ° C. The method of claim 1, And performing a pretreatment cleaning process prior to forming the first rounded oxide film. The method of claim 7, wherein The pretreatment washing step was performed at 50 ° C. for 10 minutes using SC-1 having a ratio of NH ₄ OH: H ₂ O ₂ : H ₂ O 1: 5: 50, and then the ratio of HF: H ₂ O was 99: 1. A device isolation film forming method of a semiconductor device, characterized in that carried out for 180 seconds using a phosphorus solution. The method of claim 1, And performing a pretreatment cleaning process prior to forming the second and third rounding oxides. The method of claim 9, The pretreatment washing step is a method for forming a device isolation film of a semiconductor device, characterized in that the NH ₄ OH: H ₂ O ₂ : H ₂ O ratio is 1: 5: 50 using SC-1 for 10 minutes at 50 ℃. . The method of claim 1, The nitride film is a device isolation film forming method of a semiconductor device, characterized in that formed in a thickness of 1000 to 1500Å. The method of claim 1, And the planarization step is performed until the fourth HDP oxide film has a height of 700 to 800 GPa from the semiconductor substrate.