JP2002353330A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the reduction of contact resistance and the reduction of leakage current in a contact hole, and further to enable electrostatic discharge breakdown resistance to be secured. SOLUTION: In a MOS transistor having a salicide structure, a silicide film 9a to 9c is formed on a surface of a gate electrode 7a, a source region 4a, and a drain region 5b. In a MOS transistor having a nonsalicide structure, a silicide film 9d, 9e is formed only at a portion corresponding to the contact hole on a surface of a gate electrode 7b, a source region 4b, and the drain region 5b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an MO
The present invention relates to a semiconductor device for forming an S transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a salicide structure has been known in an LSI in which a gate electrode, a source region, and a drain region of a MOS transistor are silicided to reduce wiring resistance due to a demand for high-speed circuit elements. For example, it is not preferable to reduce the wiring resistance in all MOS transistors provided in an LSI, such as a MOS transistor used in a protection circuit for preventing electrostatic breakdown. From this, Japanese Patent Application Laid-Open
In Japanese Patent Application Laid-Open No. 2-40819, utilizing the fact that the oxidation rate is different in a region where silicidation has not been performed first, regions where silicidation is not performed and regions where silicidation is not performed are determined by a difference in thickness of an oxide film to be formed. A method has been proposed in which a salicide structure MOS transistor and a non-salicide structure MOS transistor (hereinafter referred to as a non-salicide structure MOS transistor) are simultaneously formed.

[0003]

However, according to the method of manufacturing a semiconductor device disclosed in the above publication, the source region and the drain region of a MOS transistor having a non-salicide structure have a contact hole serving as a connection portion with a wiring portion. Also, since silicide is not formed, the problem that the contact resistance is increased and the problem that the leak current in the contact hole is increased occur.

Since only the source region and the drain region are not silicided and silicide is formed on the gate electrode, when a MOS transistor is used in a protection circuit for preventing electrostatic breakdown, This causes a problem that the breakdown voltage of the electrostatic breakdown is reduced. Although it is possible to avoid this reduction in breakdown voltage by devising the circuit, it is not preferable because the protection circuit becomes complicated and the chip size increases.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to provide a semiconductor device capable of reducing contact resistance and reducing leakage current in a contact hole and a method of manufacturing the same. Further, it is another object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can ensure a withstand voltage against electrostatic breakdown.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, a semiconductor substrate (1) having a semiconductor layer (2) of a first conductivity type and a surface layer portion of the semiconductor layer are provided. The source region (4a, 4b) and the drain region (5a, 5a, 5a, 5b) of the second conductivity type formed so as to be separated from each other
b), a channel region between the source region and the drain region, a gate insulating film (6a, 6b) formed on the channel region, and a gate electrode (7a, 7b) formed on the gate insulating film. ), An interlayer insulating film (10) formed on a semiconductor substrate including a gate electrode, a source region and a drain region, and a gate electrode formed on the interlayer insulating film.
A contact hole communicating with the source region or the drain region, and a wiring portion (1) electrically connected to the gate electrode, the source region, or the drain region through the contact hole.
1, 12), a part of the plurality of MOS transistors has a silicide film (9a to 9c) on the surface of the gate electrode, the source region and the drain region. Is formed,
A MOS transistor different from a part thereof is characterized in that silicide films (9d, 9e) are formed only in portions corresponding to contact holes on the surfaces of a source region and a drain region.

As described above, the MOS having the salicide structure
For the transistor, a silicide film was formed on the surface of the gate electrode, the source region and the drain region, and for the MOS transistor having a non-salicide structure, the silicide film was formed only on the portion corresponding to the contact hole on the surface of the source and drain regions. It has a configuration. Therefore, it is possible to reduce the contact resistance and the leakage current in the contact hole.

[0008] The invention according to claim 2 is characterized in that a MOS transistor different from a part does not have a silicide film formed on the surface of a gate electrode. As described above, if the silicide film is not formed on the surface of the gate electrode for the MOS transistor having the non-salicide structure, it is possible to secure the electrostatic breakdown voltage. Note that even if the silicide film is formed only at the position corresponding to the contact hole on the surface of the gate electrode,
It is possible to ensure the electrostatic breakdown voltage in the region where the electrostatic breakdown is not formed.

According to the fourth aspect of the present invention, in a region where a MOS transistor different from a part is formed, one side of a gate width of a surface of a gate electrode is closer to a drain region side.
/ 2 or more regions are covered with a mask layer. With this configuration, since the silicide film is not formed on the surface of the gate electrode on the drain region side, the electrostatic breakdown resistance can be improved, and further, since the silicide film is formed on the source region side. The resistance can be reduced, and a high current capability can be secured.

According to the fifth aspect of the present invention, in a region where a different MOS transistor is formed,
The distance from the contact electrode portion in the drain region of the transistor to the center of the gate electrode is longer than the distance from the contact electrode portion in the source region to the center of the gate electrode.

With such a configuration, the drain-side resistance Rdrain from the contact electrode portion of the drain region to the gate electrode is equal to the source-side resistance Rsource from the contact electrode portion of the source region to the gate electrode.
Can be larger than Thereby, the electrostatic withstand voltage against the electrostatic surge input from the drain region side can be further improved.

[0012] The invention according to claims 6 to 9 is the first invention.
The present invention relates to a method for manufacturing a semiconductor device according to any one of Items 1 to 5. According to the sixth aspect of the present invention, the step of arranging the mask layer (13) on the surface of the semiconductor substrate including the gate electrode, the source region and the drain region, and the step of etching the mask layer make the plurality of MOS transistors out of the plurality of MOS transistors. The mask layer is removed in a region where a part is formed, and M
A step of removing the mask layer in a region corresponding to the contact hole in the region where the OS transistor is formed, and forming silicide with the mask layer used as a mask, thereby exposing the gate electrode, the source region, and the drain region to the exposed portions. Forming silicide films (9a to 9e). According to this manufacturing method, the semiconductor device according to the first aspect can be manufactured.

According to a seventh aspect of the present invention, in the step of disposing the mask layer, the thickness of the mask layer is set to 200 ° or more. By doing so, it is possible to prevent the formation of the silicide film even in the region where the silicide film is not desired to be formed.

The reference numerals in the parentheses of the above means indicate the correspondence with the specific means described in the embodiments described later.

[0015]

(First Embodiment) FIG. 1 shows a cross-sectional structure of a semiconductor device to which one embodiment of the present invention is applied.
Hereinafter, the configuration of the semiconductor device will be described with reference to FIG.

As shown in FIG. 1, the silicon substrate 1 has p
A mold well layer 2 is formed. A trench 3a is formed in the p-type well layer 2, and the inside of the trench 3a is filled with an insulating film 3b to form an STI structure. The STI structure achieves element isolation between the elements. Then, a salicide structure MOS transistor is formed in one element formation region (left side in the drawing) separated by the STI structure, and a non-salicide structure MOS transistor is formed in the other element formation region (right side in the drawing). ing.

In the salicide structure MOS transistor, a source region 4a and a drain region 5a are formed in the surface layer of the silicon substrate 1 so as to be separated from each other.
And a gate oxide film 6a formed on a channel region formed between source region 4a and drain region 5a.
And a gate electrode 7a formed on gate oxide film 6a
And a side wall 8a formed on the side wall of the gate electrode 7a. A silicide film 9a to 9c is formed on the surface of the gate electrode 7a, the source region 4a, and the drain region 5a. The electrical connection is made with the W plug 11 in the inside and the wiring portion composed of the Al wiring 12 on the interlayer insulating film 10.

On the other hand, the MOS transistor having the non-salicide structure has a source region 4b and a drain region 5 which are formed in the surface layer of the silicon substrate 1 so as to be separated from each other.
and a gate oxide film 6b formed on a channel region formed between the source region 4b and the drain region 5b.
And a gate electrode 7b formed on the gate oxide film 6b
And a side wall 8b formed on the side wall of the gate electrode 7b. In the region having the non-salicide structure, the region other than the region corresponding to the contact hole formed in the interlayer insulating film 10 is an oxide film 13 serving as a mask layer.
Covered with. Then, among the surfaces of the gate electrode 7b, the source region 4b and the drain region 5b, the interlayer insulating film 10
Has a structure in which silicide films 9d and 9e are formed in a region corresponding to the contact hole formed. That is, the gate electrode 7b, the source region 4a, and the drain region 5b are configured to be electrically connected to the wiring portion through the silicide films 9d and 9e formed only at the portions corresponding to the contact holes. Although the silicide film formed on the gate electrode 7b does not appear in the cross section shown in FIG. 1, a silicide film is formed in another cross section.

In the MOS transistor having a non-salicide structure, the distance from the salicide film 9e, which is a contact electrode portion of the drain region 5b, to the center of the gate electrode 7b is equal to the distance from the salicide film 9d, which is a contact electrode portion of the source region 4b, to the gate. It is longer than the distance to the center of the electrode 7b.

With such a configuration, the salicide film 9e is formed.
From the drain to the gate electrode 7e.
ain can be greater than the source-side resistance Rsource from the salicide film 9d to the gate electrode 7b. Thereby, the electrostatic withstand voltage against the electrostatic surge input from the drain region 5b side can be further improved.

Next, the manufacturing steps of the semiconductor device shown in FIG. 1 are shown in FIGS. 2 to 4, and a method of manufacturing the semiconductor device will be described with reference to these drawings.

[Step shown in FIG. 2A] First, a silicon substrate 1 on which a p-type well layer 2 is formed is prepared. Next, a well-known STI structure forming process is performed on the silicon substrate 1 to form the trench 3a and fill the trench 3a with an insulating film 3b. Thereafter, the surface of the silicon substrate 1 is thermally oxidized to form the gate oxide films 6a and 6b.
Is formed, a polysilicon layer is formed on the gate oxide films 6a and 6b, and the polysilicon layers are patterned to form gate electrodes 7a and 7b.

Next, T is applied to the entire surface of the wafer by CVD.
After depositing an insulating film such as an EOS film, the insulating film is etched back by an anisotropic
Side walls 8a and 8b are formed on the side surfaces of a and 7b. Thereafter, after forming a through film, source regions 4a and 4b and drain regions 5a and 5b are formed by ion-implanting n-type impurities. Thereby, both the region having the salicide structure and the region having the non-salicide structure have M
An OS transistor is formed.

[Step shown in FIG. 2B] An oxide film 13 is deposited on the entire surface of the wafer. If the thickness of the oxide film 13 at this time is too small, the oxide film 13 will be silicided in the subsequent processing, and a silicide film will be formed even in a region where the silicide film is not desired to be formed. Has a thickness of 200 ° or more.

[Step shown in FIG. 2C] After the resist 14 is deposited on the entire surface of the wafer, unnecessary portions of the resist 14 are removed by photolithography. Specifically, in a region having a salicide structure and a region corresponding to a contact hole formed in the above-described interlayer insulating film 10 in a region having a non-salicide structure, a resist is left in a region not to be silicided. Then, the resist 14 is removed.

[Step shown in FIG. 3A] Etching is performed using the resist 14 as a mask. Thereby, the oxide film 1
Among the regions 3, the region corresponding to the contact hole formed in the above-described interlayer insulating film 10 in the region having the salicide structure and the region having the non-salicide structure are removed, and the region not to be silicided remains.

[Step shown in FIG. 3B] After a Ti film is formed on the entire surface of the wafer, heat treatment is performed to convert the formed Ti film into a silicide. At this time, since the silicidation is performed using the self-alignment, the Ti film is not silicided in the region where the oxide film 13 remains, and the Ti film is silicided in the region where the oxide film 13 is removed. Is done.

Thus, the MOS having the salicide structure is formed.
Silicide films 9a to 9c are formed on the surfaces of the gate electrode 7a, the source region 4a, and the drain region 5a of the transistor. Silicide films 9d and 9e are formed at portions corresponding to the contact holes of FIG.

[Steps shown in FIGS. 3C and 4A] First, as shown in FIG. 3C, an interlayer insulating film 10 is formed on the entire surface of the wafer, and then the interlayer insulating film 10 is formed by CMP polishing or the like. The insulating film 10 is flattened. Then, by performing photolithography and dry etching, a contact hole is formed in the interlayer insulating film 10 as shown in FIG.

[Step shown in FIG. 4B] Interlayer insulating film 10
After burying the inside of the contact hole formed in the above with a W plug 11, the W plug 11 is flattened, an Al film is formed on the interlayer insulating film 10, and then the Al film is patterned to form an Al wiring 12. . In this way,
The semiconductor device shown in FIG. 1 is completed.

According to the semiconductor device as described above,
Also in the MOS transistor having the non-salicide structure, the gate electrode 7b, the source region 4b, and the drain region 5b are electrically connected to the wiring portion through the silicide films 9d and 9e formed only at the portions corresponding to the contact holes. With this configuration, the contact resistance can be reduced. The silicide films 9d and 9e formed as described above allow the source region 4b and the drain region 5 including contact holes and diffusion layers to be formed.
This prevents direct contact with b, thereby minimizing leakage current.

Further, even if a silicide film is formed,
Since the MOS transistor is formed only in a portion corresponding to the contact hole on the surface of the gate electrode 7b, when the MOS transistor is used in a protection circuit for preventing electrostatic breakdown,
It is possible to prevent the breakdown voltage of the electrostatic breakdown from being reduced. Thereby, the electrostatic breakdown strength can be improved.

(Other Embodiments) In the above embodiment, only the portion of the surface of the gate electrode 7b corresponding to the contact hole is silicided, and the other portions are not silicided.
On the drain region 5b side of the surface b, for example, a region having a half or more of the gate width (gate length) may not be silicided. Specifically, in a MOS transistor having a non-salicide structure, a region having half or more of the gate width on the drain region 5b side may be covered with the oxide film 13.

With this configuration, since no silicide film is formed on the surface of the gate electrode 7b on the drain region 5b side, the resistance to electrostatic breakdown can be improved, and the silicide film on the source region 4b side can be improved. Since the film is formed, the resistance can be reduced, and a high current capability can be secured.

Although a surge which causes electrostatic discharge is input from the drain electrode 9e due to circuit design, a part of the drain electrode 9e has an area overlapping the gate electrode 7b. Therefore, in order to completely cover the drain region with the mask layer 13, the width is set to １ ／ of the gate width.

Further, in the above embodiment, the case where the silicide film is formed in the portion corresponding to the contact hole also with respect to the gate electrode 7b of the MOS transistor having the non-salicide structure has been described, but the gate electrode 7b is completely formed on the surface of the gate electrode 7b. The silicide film may not be formed. By doing so, the resistance to electrostatic breakdown can be further improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1;

FIG. 3 is a view illustrating a manufacturing step of the semiconductor device following FIG. 2;

FIG. 4 is a view illustrating a manufacturing step of the semiconductor device following FIG. 3;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... p-type well layer, 4a, 4b ... Source region, 5a, 5b ... Drain region, 6a, 6b ... Gate oxide film, 7a, 7b ... Gate electrode, 9a-9e ... Silicide film, 10 ... Interlayer insulating film, 11 ... W plug, 12
... Al wiring.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB02 BB18 BB25 CC01 CC05 DD02 DD04 DD08 DD16 DD26 DD78 DD84 EE09 EE14 FF01 FF14 FF18 FF22 FF28 GG09 GG10 GG14 HH12 HH15 HH16 HH20 KK01 KK11 MM13 NN03 NN07 QQ09 QQ11 QQ31 QQ37 QQ48 QQ58 QQ59 QQ65 QQ70 QQ73 RR04 SS04 SS11 TT02 TT08 XX00 XX01 XX09 XX10 XX31 5F048 AA02 AA07 AB03 AC01 BA01 BB05 BB08 BB12 BF06 BF06 BF06

Claims (9)

[Claims] 1. A semiconductor substrate (1) having a semiconductor layer (2) of a first conductivity type, and a source region (4a, 2a) of a second conductivity type formed so as to be separated from each other in a surface portion of the semiconductor layer. 4b) and a drain region (5a, 5b); a channel region between the source region and the drain region; a gate insulating film (6a, 6b) formed on the channel region; The gate electrode (7a,
7b) and an interlayer insulating film (1) formed on the semiconductor substrate including the gate electrode, the source region, and the drain region.
0), a contact hole formed in the interlayer insulating film and communicating with the gate electrode, the source region or the drain region, and an electrical connection with the gate electrode, the source region or the drain region through the contact hole. In a semiconductor device provided with a plurality of MOS transistors having formed wiring portions (11, 12), a part of the plurality of MOS transistors includes the gate electrode, the source region, and the drain region. In the MOS transistor different from the above part, the silicide films (9d, 9c) are formed only at portions corresponding to the contact holes on the surfaces of the source region and the drain region.
e) a semiconductor device characterized by being formed. 2. The semiconductor device according to claim 1, wherein a MOS transistor different from said part does not have a silicide film formed on a surface of said gate electrode. 3. A mask layer (13) is formed on a surface of the semiconductor substrate including the gate electrode, the source region or the drain region in a region where a MOS transistor different from the part is formed. 3. The semiconductor device according to claim 1, wherein the mask layer has an opening only on the surface of the source region and the drain region where the silicide film is formed. 4. 4. In a region where a MOS transistor different from said part is formed, on the drain region side,
4. The semiconductor device according to claim 3, wherein a region of the surface of the gate electrode that is equal to or less than half of a gate width is covered with the mask layer. 5. 5. In a region where a MOS transistor different from said part is formed, a distance from a contact electrode portion of said drain region to said gate electrode of said MOS transistor is different from a contact electrode portion of said source region to said gate. The semiconductor device according to claim 1, wherein the distance is longer than a distance to the electrode. 6. A semiconductor substrate (1) provided with a semiconductor layer (2) of a first conductivity type, and a source region (4a, 2a) of a second conductivity type formed so as to be separated from each other in a surface layer portion of the semiconductor layer. 4b) and a drain region (5a, 5b); a channel region between the source region and the drain region; a gate insulating film (6a, 6b) formed on the channel region; The gate electrode (7a,
7b) and an interlayer insulating film (1) formed on the semiconductor substrate including the gate electrode, the source region, and the drain region.
0), a contact hole formed in the interlayer insulating film and communicating with the gate electrode, the source region or the drain region, and an electrical connection with the gate electrode, the source region or the drain region through the contact hole. In a method of manufacturing a semiconductor device having a plurality of MOS transistors having formed wiring portions (11, 12), a mask layer is provided on a surface of the semiconductor substrate including the gate electrode, the source region and the drain region (13) arranging the plurality of MOs by etching the mask layer;
The mask layer is removed in a region where a part of the S transistor is formed, and an M transistor different from the part is removed.
Removing the mask layer in a region corresponding to the contact hole in the region where the OS transistor is formed; and siliciding the mask layer using the mask layer as a mask, so that the gate electrode, the source region, and the Silicide films (9a to 9e) on exposed portions of the drain region
Forming a semiconductor device. 7. The method according to claim 6, wherein in the step of disposing the mask layer, the thickness of the mask layer is set to 200 ° or more. 8. The step of removing the mask layer, wherein the mask layer on the surface of the gate electrode is not removed in a region where a MOS transistor different from the part is formed. A method for manufacturing a semiconductor device according to claim 6. 9. In the step of removing the mask layer, in a region where a MOS transistor different from the part is formed, a gate width of 表面 or less of a gate width on a side of the drain region on a surface of the gate electrode. The method according to claim 6, wherein the mask layer is removed in a region.