KR100950890B1 - Method for forming salicide of semiconductor device - Google Patents

Method for forming salicide of semiconductor device Download PDF

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KR100950890B1
KR100950890B1 KR1020030003956A KR20030003956A KR100950890B1 KR 100950890 B1 KR100950890 B1 KR 100950890B1 KR 1020030003956 A KR1020030003956 A KR 1020030003956A KR 20030003956 A KR20030003956 A KR 20030003956A KR 100950890 B1 KR100950890 B1 KR 100950890B1
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salicide
forming
region
hard mask
mask layer
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KR20040067017A (en
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이준현
고창진
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

본 발명은 반도체소자의 살리사이드 형성방법을 개시한다. 개시된 발명은, 비살리사이드 영역과 살리사이드영역으로 구분된 실리콘기판상에 도전층과 하드 마스크층을 형성하는 단계; 상기 비살리사이드 영역상에 제1감광막패턴을 형성하는 단계; 상기 제1감광막패턴을 마스크로 상기 하드마스크층을 선택적으로 제거하여 상기 비살리사이드영역에만 하드마스크층패턴을 형성하는 단계; 상기 제1감광막패턴 을 제거하고 상기 살리사이드 영역상에 제2감광막패턴을 형성하는 단계; 상기 제2 감광막패턴과 상기 하드마스크패턴을 마스크로 상기 도전층을 선택적으로 제거하여 게이트전극을 형성하는 단계; 상기 제2감광막을 제거한후 상기 게이트전극측면에 스페이서를 형성하는 단계; 상기 실리콘기판과 게이트전극의 노출된 표면에 살리 사이드를 형성하는 단계; 상기 비살리사이드영역의 게이트전극상에 있는 하드마스크 층패턴을 제거하는 단계를 포함하여 구성되며, 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide) 영역과 비살리사이드(non-salicide 또는 non-cosalicide)영역을 선택적으로 동시에 형성할 수 있어 공정단계수를 줄일 수 있는 것이다.
The present invention discloses a method of forming a salicide of a semiconductor device. The disclosed invention includes forming a conductive layer and a hard mask layer on a silicon substrate divided into a nonsalicide region and a salicide region; Forming a first photoresist pattern on the nonsalicide region; Selectively removing the hard mask layer using the first photoresist pattern as a mask to form a hard mask layer pattern only in the nonsalicide region; Removing the first photoresist pattern and forming a second photoresist pattern on the salicide region; Forming a gate electrode by selectively removing the conductive layer using the second photoresist pattern and the hard mask pattern as a mask; Forming a spacer on the gate electrode side after removing the second photosensitive film; Forming salicide on an exposed surface of the silicon substrate and the gate electrode; And removing a hard mask layer pattern on the gate electrode of the nonsalicide region, wherein the salicide (salicide or co-salicide) region and the non-salicide are formed in one chip of the semiconductor device. Alternatively, non-cosalicide zones can be formed simultaneously, thereby reducing the number of process steps.

Description

반도체소자의 살리사이드 형성방법{Method for forming salicide of semiconductor device} Method for forming salicide of semiconductor device

도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도.2A to 2E are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 실리콘기판 33 : 폴리실리콘층31 silicon substrate 33 polysilicon layer

33a, 33b : 게이트전극 35 : 하드마스크층33a, 33b: gate electrode 35: hard mask layer

37 : 제1감광막패턴 39 : 제2감광막패턴37: first photosensitive film pattern 39: second photosensitive film pattern

41 : LDD 스페이서 43 : 살리사이드막 41: LDD spacer 43: salicide film

본 발명은 반도체소자의 살리사이드 형성방법에 관한 것으로서, 보다 상세하게는 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide)영역과 비살리사이드(non-salicide 또는 non-cosalicide)영역을 선택적으로 동시에 형성할 수 있는 반도체소자의 살리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a salicide of a semiconductor device, and more particularly, to a salicide (salicide or co-salicide) region and a non-salicide (non-salicide or non-cosalicide) region in one chip of a semiconductor device. The present invention relates to a method for forming a salicide of a semiconductor device that can be formed simultaneously.

종래기술에 따른 반도체소자의 살리사이드 형성방법에 대해 도 1a 내지 도 1d를 참조하여 설명하면 다음과 같다.A method of forming a salicide of a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1D.

도 1a 내지 도 1d는 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a salicide of a semiconductor device.

종래기술에 따른 반도체소자의 살리사이드 형성방법은, 도 1a에 도시된 바와같이, 살리사이드가 형성되지 않을 영역(A)과 살리사이드가 형성될 영역(B)으로 분할된 실리콘기판(11)상에 게이트산화막(13)과 게이트전극(15)을 차례로 형성한후 이들 측면에 LDD 스페이서(17)를 형성한다.In the method of forming a salicide of a semiconductor device according to the related art, as illustrated in FIG. 1A, the silicon substrate 11 is divided into a region A in which salicide is not formed and a region B in which salicide is to be formed. After the gate oxide film 13 and the gate electrode 15 are formed in this order, LDD spacers 17 are formed on these side surfaces.

그다음, 도 1b에 도시된 바와같이, 상기 전체 구조의 상면에 산화막(19)을 증착한후 살리사이드가 형성되지 않을 영역(A)에 해당하는 기판부분상에 감광막패턴(21)을 형성한다. 이때, 상기 산화막(19)은 나중에 살리사이드 생성과정에서 비살리사이드부위의 살리사이드가 생성되지 않도록 배리어산화막 물질로 작용한다.Then, as shown in FIG. 1B, after the oxide film 19 is deposited on the upper surface of the entire structure, a photosensitive film pattern 21 is formed on the substrate portion corresponding to the region A where salicide is not formed. At this time, the oxide film 19 serves as a barrier oxide film material so that the salicide of the non-salicide portion is not produced later in the process of forming salicide.

이어서, 도 1c에 도시된 바와같이, 상기 감광막패턴(21)을 마스크로 상기 살리사이드가 형성될 영역(B)에 해당하는 기판부분에 있는 산화막(19)부분을 선택적으로 제거한후 감광막패턴(21)을 제거한다. 이때, 상기 산화막(19)의 일부분의 식각진행은 CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한 것이며, 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2 가스 등을 포함할 수 있다. Subsequently, as shown in FIG. 1C, a portion of the oxide film 19 in the substrate corresponding to the region B on which the salicide is to be formed is selectively removed using the photoresist pattern 21 as a mask, and then the photoresist pattern 21 is removed. ). In this case, the etching of the portion of the oxide layer 19 is performed by using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar, and the like C 4 F 8 , C2F 6 , C 5 F 8 And / or CxFy, N 2 gas, and the like.

그다음, 도 1d에 도시된 바와같이, 상기 살리사이드가 형성될 영역(B)에 해당하는 실리콘기판(11) 및 게이트전극(15)의 노출된 부분에 살리사이드 (또는 Co-salicide) (23)을 형성한다. 이때, 비 살리사이드 부분에는 잔류하는 산화막 배리 어에 의해서 살리사이드 (또는 Co-salicide)가 생성되지 않는다.Next, as shown in FIG. 1D, the salicide (or co-salicide) 23 is exposed to the exposed portions of the silicon substrate 11 and the gate electrode 15 corresponding to the region B on which the salicide is to be formed. To form. At this time, salicide (or co-salicide) is not generated by the remaining oxide barrier in the non-salicide portion.

상기와 같은 종래기술에 의하면, LDD 구조를 형성한다음 감광막패턴을 배리어로 사용하여 살리사이드 부위의 산화막을 제거하고 이어 감광막패턴을 제거한후 살리사이드를 형성하므로 인해 공정 단계수가 증가하게 된다.According to the prior art as described above, since the LDD structure is formed and then the photoresist pattern is used as a barrier, an oxide film of the salicide region is removed, followed by the removal of the photoresist pattern, thereby forming a salicide, thereby increasing the number of process steps.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide) 영역과 비살리사이드(non-salicide 또는 non-cosalicide)영역을 선택적으로 동시에 형성할 수 있어 공정단계수를 줄일 수 있는 반도체소자의 살리사이드 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and a salicide (salicide or co-salicide) region and a non-salicide (non-salicide or non-cosalicide) region in one chip of a semiconductor device. It is an object of the present invention to provide a method for forming a salicide of a semiconductor device which can be formed at the same time selectively, thereby reducing the number of process steps.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 살리사이드 형성방법은, Salicide forming method of a semiconductor device according to the present invention for achieving the above object,

비살리사이드 영역과 살리사이드영역으로 구분된 실리콘기판상에 도전층과 하드마스크층을 형성하는 단계;Forming a conductive layer and a hard mask layer on the silicon substrate divided into an unsalicide region and a salicide region;

상기 비살리사이드 영역상에 제1감광막패턴을 형성하는 단계;Forming a first photoresist pattern on the nonsalicide region;

상기 제1감광막패턴을 마스크로 상기 하드마스크층을 선택적으로 제거하여 상기 비살리사이드영역에만 하드마스크층패턴을 형성하는 단계;Selectively removing the hard mask layer using the first photoresist pattern as a mask to form a hard mask layer pattern only in the nonsalicide region;

상기 제1감광막패턴을 제거하고 상기 살리사이드 영역상에 제2감광막패턴을 형성하는 단계; Removing the first photoresist pattern and forming a second photoresist pattern on the salicide region;                     

상기 제2감광막패턴과 상기 하드마스크층패턴을 마스크로 상기 도전층을 선택적으로 제거하여 게이트전극을 형성하는 단계;Forming a gate electrode by selectively removing the conductive layer using the second photoresist pattern and the hard mask layer pattern as a mask;

상기 제2감광막을 제거한후 상기 게이트전극측면에 스페이서를 형성하는 단계;Forming a spacer on the gate electrode side after removing the second photosensitive film;

상기 실리콘기판과 게이트전극의 노출된 표면에 살리사이드를 형성하는 단계;Forming salicide on exposed surfaces of the silicon substrate and the gate electrode;

상기 비살리사이드영역의 게이트전극상에 있는 하드마스크층패턴을 제거하는 단계를 포함하여 구성되는 것을 특징으로한다.And removing the hard mask layer pattern on the gate electrode of the nonsalicide region.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 살리사이드 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming a salicide of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도이다.2A to 2E are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 살리사이드 형성방법은, 도 2a에 도시된 바와같이, 먼저 살리사이드가 형성되지 않을 영역(A)와 살리사이드영역이 형성될 영역(B)으로 분할된 실리콘기판(31)상에 게이트 형성용 폴리실리콘층(33)을 증착한후 그 위에 하드마스크층(35)을 증착한다.In the method for forming a salicide of a semiconductor device according to the present invention, as shown in FIG. 2A, a silicon substrate 31 is divided into a region A in which salicide is not to be formed and a region B in which the salicide region is to be formed. ) And then depositing a gate layer polysilicon layer 33 on the hard mask layer 35 thereon.

그다음, 상기 살리사이드가 형성되지 않을 영역(A)에 위치하는 상기 하드마스크층(35)의 일부분상에 제1감광막패턴(37)을 형성한다.Next, a first photoresist layer pattern 37 is formed on a portion of the hard mask layer 35 positioned in the region A where the salicide is not formed.

이어서, 도 2b에 도시된 바와같이, 상기 제1감광막패턴(37)을 마스크로 상기 상기 하드마스크층(35)을 선택적으로 제거한다. 이때, 상기 하드마스크층(35)의 식각진행은, CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한 것이며, 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2 가스 등을 포함할 수 있다. 여기서, 식각가스 및 가스유량으로는 CHF3 : 1∼200sccm, CF4 : 1∼200sccm, O2 : 0∼20sccm, Ar : 1∼1000sccm이거나 이들외에 C4F8,: 1∼50sccm, N2, : 0∼500sccm을 사용한다. Subsequently, as illustrated in FIG. 2B, the hard mask layer 35 is selectively removed using the first photoresist pattern 37 as a mask. In this case, the etching of the hard mask layer 35 is performed by using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar, and C 4 F 8 , C 2 F 6 , C 5 F 8 / etc., CxFy, N 2 gas and the like. Here, the etching gas and the gas flow rate may be CHF 3 : 1-200 sccm, CF 4 : 1-200 sccm, O 2 : 0-20 sccm, Ar: 1-1000 sccm, or else C 4 F 8 ,: 1-50 sccm, N 2 ,: 0 to 500sccm is used.

그다음, 제1감광막패턴(37)을 제거한후 전체 구조의 상면에 감광물질을 도포한후 포토리소그라피 공정기술에 의해 노광 및 현상공정을 거쳐 상기 감광물질층을 선택적으로 제거하여 상기 살리사이드 형성영역(B)의 일부분에 제2감광막패턴(39)을 형성한다.Then, after removing the first photoresist pattern 37, the photosensitive material is applied to the upper surface of the entire structure, and then the photosensitive material layer is selectively removed by photolithography process technology to selectively remove the salicide forming region ( A second photoresist pattern 39 is formed on a portion of B).

이어서, 도 2c에 도시된 바와같이, 상기 제2감광막패턴(39)과 상기 하드마스크층패턴(35a)을 마스크로 상기 게이트 형성용 폴리실리콘층(33)을 선택적으로 제거하여 게이트전극(33a)(33b)를 형성한후 제2감광막패턴(39)을 제거한다. 이때, 상기 살리사이드가 형성되지 않을 영역(A)에는 하드마스크층패턴(35a)이 존재하여 마스크 역할을 하기 때문에 감광막패턴은 필요하지 않는다. 또한, 상기 게이트전극(33a)는 살리사이드가 형성되지 않을 영역(A)에 위치하고, 게이트전극(33b)는 살리사이드가 형성될 영역(B)에 위치한다. 이때, 상기 게이트형성용 폴리실리콘층(33) 식각은 Cl2/HBr/He-O2/Ar 등의 활성화된 플라즈마를 이용하여 진행한다. 또한, 상기 폴리실리콘과 질화막간의 선택비는 약 200∼300:1 정도가 되기 때문에 질화막 하드마스크를 배리어로 사용하여 패턴 진행시에 하드마스크인 질화막은 폴리실리콘에 비해 식각되는 정도가 적기 때문에 질화막 하드마스크층(35a)은 계속 남아 있게 된다.Subsequently, as shown in FIG. 2C, the gate forming polysilicon layer 33 is selectively removed using the second photoresist layer pattern 39 and the hard mask layer pattern 35a as a mask to form a gate electrode 33a. After forming 33b, the second photosensitive film pattern 39 is removed. In this case, since the hard mask layer pattern 35a exists in the region A in which the salicide is not formed, and serves as a mask, the photoresist pattern is not necessary. In addition, the gate electrode 33a is positioned in a region A where salicide is not formed, and the gate electrode 33b is positioned in a region B in which salicide is to be formed. At this time, the gate forming polysilicon layer 33 is etched using an activated plasma such as Cl 2 / HBr / He-O 2 / Ar. In addition, since the selectivity ratio between the polysilicon and the nitride film is about 200 to 300: 1, the nitride film hard mask is used as a barrier so that the nitride film, which is a hard mask during etching, is less etched than the polysilicon. The mask layer 35a remains.

그다음, 전체 구조의 상면에 LDD용 산화막(미도시)을 증착한후 이를 이방성 식각에 의해 선택적으로 제거하여 상기 게이트전극(33a)(33b)측면에 LDD스페이서(41)를 형성한다. 이때, 상기 LDD산화막(미도시)의 일부분의 식각진행은 CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한 것이며, 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2, O 2 등을 포함할 수 있다.Then, an LDD oxide film (not shown) is deposited on the top surface of the entire structure and then selectively removed by anisotropic etching to form the LDD spacer 41 on the side of the gate electrodes 33a and 33b. At this time, the etching progress of a portion of the LDD oxide film (not shown) is performed by using an activated plasma, such as CHF 3 / CF 4 / O 2 / Ar, such as C 4 F 8 , C2F 6 , C 5 It may include F 8 / etc. of CxFy, N 2, O 2 or the like.

이어서, 도 2d에 도시된 바와같이, 실리콘기판(31)과 게이트전극(33b)의 노출된 표면에 살리사이드막(43)을 형성한다. 이때, 살리사이드가 형성되지 않을 영역(A)의 게이트전극(33a)표면에는 하드마스크층패턴(35a)이 존재하기 때문에 이 부위를 제외한 나머지 부분에 살리사이드가 생성된다.Subsequently, as shown in FIG. 2D, the salicide film 43 is formed on the exposed surfaces of the silicon substrate 31 and the gate electrode 33b. At this time, since the hard mask layer pattern 35a is present on the surface of the gate electrode 33a of the region A in which salicide is not formed, salicide is generated in the remaining portions except for this region.

그다음, 도 2e에 도시된 바와같이, 잔류하는 하드마스크층패턴(35a)을 제거한다. 이때, 상기 하드마스크층패턴(35a)의 제거는 활성화된 플라즈마를 이용하여 식각하는 것이 아니라 O2/CF4 가스를 이용하여 다운 플로우(down flow)방식으로 식각을 진행한다. 이렇게 다운 플로우 방식으로 식각을 진행하게 되면 질화막과 산화막간의 선택비가 12:1정도가 되어 산화막 물질은 조금만 제거된다.Then, as shown in Fig. 2E, the remaining hard mask layer pattern 35a is removed. In this case, the hard mask layer pattern 35a is not etched using the activated plasma, but is etched in a downflow manner using O 2 / CF 4 gas. When the etching is performed in the downflow manner, the selectivity between the nitride film and the oxide film is about 12: 1, and the oxide material is removed slightly.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 살리사이드 형성방 법에 의하면, 선택적으로 게이트전극부위에 비살리사이드영역과 살리사이드 부위를 동시에 형성시킬 수가 있게 되어 전류의 흐름을 억제할 수 있는 폴리 라인이 존재하는 ESD나 전류의 흐름을 원할히 공급할 수 있는 긴 라인 폴리패턴을 정의할 수 있게 된다.As described above, according to the salicide formation method of the semiconductor device according to the present invention, it is possible to selectively form a non-salicide region and a salicide region at the gate electrode portion at the same time to suppress the flow of current It is possible to define long line polypatterns that can smoothly supply ESD or current flow in which polylines exist.

또한, 기존의 구조는 LDD구조를 형성한다음 감광물질을 배리어로 사용하여 살리사이드부위의 산화막을 제거한다음 감광물질을 제거한 후 살라사이드를 형성하는 것인데 본 발명은 LDD 스페이서를 형성하는 단계에서 살리사이드를 형성하는 단계에서 살리사이드를 형성하는 것으로 기존에 비해 공정 단계수가 줄어든다.In addition, the conventional structure is to form an LDD structure and then to remove the oxide film of the salicide site using a photosensitive material as a barrier, and then to remove the photosensitive material to form a salicide, the present invention in the step of forming a LDD spacer Forming the salicide in the step of forming a process number is reduced compared to the conventional.

또한, 기존과는 달리 LDD 스페이서를 형성하는 단계에서 비살리사이드와 살리사이드막을 구분하여 형성시킬 수 있다.In addition, unlike the conventional method, the non-salicide and the salicide layer may be formed by separating the LDD spacer.

그리고, 비살리사이드 형성과 살리사이드영역을 선택적으로 살리사이드를 형성할 수 있게 된다.In addition, it is possible to form salicide by selectively forming the salicide and the salicide region.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (7)

비살리사이드 영역과 살리사이드영역으로 구분된 실리콘기판상에 도전층과 하드마스크층을 형성하는 단계;Forming a conductive layer and a hard mask layer on the silicon substrate divided into an unsalicide region and a salicide region; 상기 비살리사이드 영역상에 제1감광막패턴을 형성하는 단계;Forming a first photoresist pattern on the nonsalicide region; 상기 제1감광막패턴을 마스크로 상기 하드마스크층을 선택적으로 제거하여 상기 비살리사이드영역에만 하드마스크층패턴을 형성하는 단계;Selectively removing the hard mask layer using the first photoresist pattern as a mask to form a hard mask layer pattern only in the nonsalicide region; 상기 제1감광막패턴을 제거하고 상기 살리사이드 영역상에 제2감광막패턴을 형성하는 단계;Removing the first photoresist pattern and forming a second photoresist pattern on the salicide region; 상기 제2감광막패턴과 상기 하드마스크층패턴을 마스크로 상기 도전층을 선택적으로 제거하여 게이트전극을 형성하는 단계;Forming a gate electrode by selectively removing the conductive layer using the second photoresist pattern and the hard mask layer pattern as a mask; 상기 제2감광막을 제거한후 상기 게이트전극측면에 스페이서를 형성하는 단계;Forming a spacer on the gate electrode side after removing the second photosensitive film; 상기 실리콘기판과 게이트전극의 노출된 표면에 살리사이드를 형성하는 단계;Forming salicide on exposed surfaces of the silicon substrate and the gate electrode; 상기 비살리사이드영역의 게이트전극상에 있는 하드마스크층패턴을 제거하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.And removing a hard mask layer pattern on the gate electrode of the non-salicide region. 제1항에 있어서, 상기 도전층 식각시에 상기 하드마스크층패턴은 도전층 식각배리어로 사용하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of claim 1, wherein the hard mask layer pattern is used as an etching layer for the conductive layer during the etching of the conductive layer. 제1항에 있어서, 상기 하드마스크층은 1 내지 2000Å 두께의 질화막을 포함하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of claim 1, wherein the hard mask layer comprises a nitride film having a thickness of 1 to 2000 microns. 제1항에 있어서, 상기 하드마스크층패턴 식각은 다운 플로우방식 또는 플라즈마방식으로 진행하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of claim 1, wherein the hard mask layer pattern etching is performed in a downflow method or a plasma method. 제4항에 있어서, 상기 다운플로우 방식을 이용하는 경우, 약 12:1 정도인 질화막과 산화막의 식각선택비를 이용하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of claim 4, wherein an etching selectivity ratio of a nitride film and an oxide film is about 12: 1 when the downflow method is used. 제4항에 있어서, 상기 다운플로우방식에 이용하는 가스종류로는 O2/CF4 가스를 이용하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of forming a salicide of a semiconductor device according to claim 4, wherein the gas used in the downflow method is O 2 / CF 4 gas. 제4항에 있어서, 상기 제1감광막패턴을 마스크로 하드마스크층을 식각하는 단계는, 플라즈마 방식을 이용하되, 식각가스 및 가스유량으로는 CHF3 : 1∼200sccm, CF4 : 1∼200sccm, O2 : 0∼20sccm, Ar : 1∼1000sccm이거나 이들외에 C4F8,: 1∼50sccm, N2, : 0∼500sccm을 사용하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The method of claim 4, wherein the etching of the hard mask layer using the first photoresist layer pattern as a mask is performed using a plasma method, and the etching gas and the gas flow rate are CHF 3 : 1 to 200 sccm, CF 4 : 1 to 200 sccm, A method of forming a salicide in a semiconductor device, comprising O 2 : 0-20 sccm, Ar: 1-1000 sccm, or C 4 F 8 ,: 1-50 sccm, N 2 ,: 0-500 sccm.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007220A (en) 1999-04-21 2001-01-12 Matsushita Electronics Industry Corp Manufacture of semiconductor device
KR20020032740A (en) * 2000-10-27 2002-05-04 박종섭 method for manufacturing semiconductor device
JP2002353330A (en) 2001-05-25 2002-12-06 Denso Corp Semiconductor device and its manufacturing method
KR20040057641A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for forming salicide of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001007220A (en) 1999-04-21 2001-01-12 Matsushita Electronics Industry Corp Manufacture of semiconductor device
KR20020032740A (en) * 2000-10-27 2002-05-04 박종섭 method for manufacturing semiconductor device
JP2002353330A (en) 2001-05-25 2002-12-06 Denso Corp Semiconductor device and its manufacturing method
KR20040057641A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for forming salicide of semiconductor device

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