US20130059441A1 - Method for fabricating a semiconductor structure - Google Patents
Method for fabricating a semiconductor structure Download PDFInfo
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- US20130059441A1 US20130059441A1 US13/666,980 US201213666980A US2013059441A1 US 20130059441 A1 US20130059441 A1 US 20130059441A1 US 201213666980 A US201213666980 A US 201213666980A US 2013059441 A1 US2013059441 A1 US 2013059441A1
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- hard mask
- trimming process
- material layer
- patterned resist
- trimming
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- 238000000034 method Methods 0.000 title claims abstract description 134
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000009966 trimming Methods 0.000 claims abstract description 110
- 239000000463 material Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 34
- 229920005591 polysilicon Polymers 0.000 claims description 33
- 238000000059 patterning Methods 0.000 claims description 9
- 239000006117 anti-reflective coating Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 125000000392 cycloalkenyl group Chemical group 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
Definitions
- the invention relates to a method for fabricating a semiconductor structure, and more particularly, to a method of trimming hard mask for forming a gate electrode layer of a MOS structure.
- MOS transistors metal oxide semiconductor transistors
- the formation of a conductive gate plays an important role.
- the current channel length under the gate must meet the standard of less than 35 nm.
- it is crucial to control the critical dimension (CD) during the process of exposure of the gate so as to control the line width of the conductive layer (poly-Si layer for example) after the etching process.
- CD critical dimension
- trimming methods are employed in some prior art methods to reduce the size of gate line width.
- photo resist layers useful in the current gate exposure process are 193 nm photo resist layers which are intrinsically less resistant to the etching condition than 365 nm photo resist layers are on account of acrylic and cycloalkenyl polymer composition in contrast to 365 nm photo resist layers composed of aryl moiety. Furthermore, the thickness of 193 nm photo resist layers reduces as the exposure wavelength shortens. Under the dual disadvantages of poor etching resistance and less and less thickness, it is hard for 193 nm photo resist layers to meet the minimum requirement of 30 nm owing to the available thickness being 10 nm or less during the trimming process on 193 nm photo resist layers.
- the current techniques deals with the problems by transferring the pattern on the photo resist layer to the hard mask beneath the photo resist layer. After being patterned, the hard mask is ready for the trimming process to reduce the gate line width. In addition, the hard mask must have high etching selectivity to the conductive layer used in forming gate layer. Accordingly, the trimmed hard mask is ready to be the template for etching transfer process to define the line width of gate layer.
- a method for fabricating a semiconductor structure includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.
- Another aspect of the present invention discloses a method for fabricating a semiconductor structure, which includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.
- Another aspect of the present invention discloses a method for fabricating a semiconductor structure, which includes the steps of: providing a substrate; depositing a material layer on the substrate; forming a plurality of trimming layers on the material layer; and performing at least a two-step trimming process on the trimming layers such that the trimming layers are trimmed twice.
- FIGS. 1-4 illustrate a method for fabricating a semiconductor structure according to a preferred embodiment of the present invention.
- FIGS. 5-8 illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention.
- FIGS. 1-4 illustrate a method for fabricating a semiconductor structure according to a preferred embodiment of the present invention.
- a substrate 12 such as a silicon substrate is provided.
- a gate dielectric layer (not shown) preferably composed of oxide, oxy-nitride, nitrogen-containing dielectric materials or a combination thereof may be formed on the substrate by thermal oxidation, chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD).
- a material layer, such as a silicon layer or a polysilicon layer 14 is then deposited on the gate dielectric layer and at least a dielectric layer 16 is formed on the polysilicon layer 14 thereafter.
- the at least one dielectric layer 16 may be composed of one single dielectric layer or a plurality of dielectric layers.
- a plurality of dielectric layers are deposited on the polysilicon layer 14 , in which the dielectric layers include a hard mask 18 and a bottom anti-reflective coating (BARC) 20 .
- the hard mask 18 could be selected from a material consisting of SiON, SiO 2 , TEOS, or a combination thereof
- the BARC 20 may be formed from an organic polymer anti-reflective coating material, such as a 365 nm (I-line) resist layer.
- a patterned resist 22 is formed on the BARC 20 thereafter.
- a trimming process 24 could be conducted to narrow the width of the patterned resist 22 .
- the trimming process 24 may be accomplished by a plasma etch using gases such as oxygen, ozone, CF 4 , CHF 3 or HBr/O 2 , and if the target layer to be trimmed were resist material, ashing may be used.
- an etching process is carried out by using the patterned resist as mask to remove a portion of the BARC 20 underneath.
- another trimming process 26 is conducted to narrow the width of the patterned resist 22 and the BARC 20 .
- the etching gas used in this trimming process 26 preferably trims only the target layers such as the aforementioned patterned resist 22 and BARC 20 without affecting any other layer underneath, and could be identical or different from the etching gas used in the previous trimming step 24 .
- an etching is performed by using the patterned resist 22 and the BARC 20 as mask to remove a portion of the hard mask 18 underneath.
- the etching is carried out on the hard mask 18 , a portion of the polysilicon layer 14 surface is exposed and the patterned resist 22 may be etched away as the pattern of the BARC 20 is transferred to the hard mask 18 .
- another trimming process 28 could be conducted to narrow the width of the BARC 20 and the hard mask 18 .
- the etching gas used in this trimming process 28 could be identical or different from the etching gas used in the previous trimming steps 24 or 26 .
- a fixed time were to be calculated for the trimming process 28 after exposing the polysilicon layer 14 to control the width difference between the top of the polysilicon layer 14 and the bottom of the polysilicon layer 14 no more than 10%.
- the fixed time of the trimming procedure is calculated after trimming greater than 70% of a total trimming value.
- a width of the BARC 20 and the hard mask 18 were to be reduced from 60 nm to 40 nm after the surface of the polysilicon layer 14 is exposed, 6 nm from the total of 20 nm being etched away in the trimming procedure would be reserved for the polysilicon layer 14 .
- a fixed time of 30 seconds is calculated to trim the 6 nm for the polysilicon layer 14 .
- the patterned resist 22 could also be remained on the BARC 20 and the hard mask 18 until exposing the surface of the polysilicon layer 14 .
- one ore more etching process could be carried by using the patterned resist 22 as mask to pattern the BARC 20 and hard mask 18 until exposing the surface of the polysilicon layer 14 .
- another trimming process is conducted to trim the patterned resist 22 , the patterned BARC 20 , and the patterned hard mask 18 before patterning the polysilicon layer 14 . This approach of performing at least two trimming process that all involves the trimming of patterned resist is also within the scope of the present invention.
- an etching is performed by using the patterned BARC 20 and the hard mask 18 as mask to remove a portion of the polysilicon layer 14 underneath for forming a patterned polysilicon layer 14 .
- the patterned polysilicon layer 14 is preferably used as a gate electrode of a metal-oxide semiconductor (MOS) device, and after the patterned polysilicon 14 is formed, typical MOS fabrication involving the formation of offset spacer, lightly doped drain, main spacer, source/drain region, epitaxial layers, stress layers, salicides, and contact plugs could be employed to form a MOS structure. As the fabrication of these MOS structure elements are commonly known to those skilled in the art in this field, the details of which are omitted herein for the sake of brevity.
- MOS metal-oxide semiconductor
- the material layer can include other suitable materials, such as silicon, silicon oxide or metal. Therefore, the patterned material layer fabricated by above mentioned steps can be used as other semiconductor structure, such as STI or contact plug.
- FIGS. 5-8 illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention.
- a substrate 42 such as a silicon substrate is provided.
- a gate dielectric layer (not shown) preferably composed of oxide, oxy-nitride, nitrogen-containing dielectric materials or a combination thereof may be formed on the substrate by thermal oxidation, chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD).
- a polysilicon layer 44 is then deposited on the gate dielectric layer and at least a dielectric layer 46 is formed on the polysilicon layer 44 thereafter.
- the at least one dielectric layer 46 may be composed of one single dielectric layer or a plurality of dielectric layers.
- a plurality of dielectric layers are deposited on the polysilicon layer 44 , in which the dielectric layers include a hard mask 48 , an advanced patterning film (APF) 50 from Applied Materials, Inc., and a dielectric anti-reflective coating (DARC) 52 .
- the hard mask 48 could be selected from a material consisting of SiON, SiO 2 , TEOS, or a combination thereof, and the DARC 52 may be formed from an organic polymer anti-reflective coating material, such as a silicon-rich silicon oxynitride layer.
- a patterned resist 54 is formed on the DARC thereafter.
- etching is then carried out by using the patterned resist 54 as mask to remove a portion of the DARC 52 underneath for forming a patterned DARC 52 .
- a trimming process could be conducted before the DARC 52 is etched.
- a trimming process is conducted to narrow the width of the patterned resist 54 and the patterned DARC 52 .
- the trimming process 56 may be accomplished by a plasma etch using gases such as oxygen, ozone, CF 4 , CHF 3 or HBr/O 2 , and if the target layer to be trimmed were resist material, ashing may be used.
- an etching process is carried out by using the patterned resist 54 and DARC 52 as mask to remove a portion of the APF 50 underneath.
- the patterned resist 54 could be removed as the APF 50 is patterned, or could be removed by a separate etching step prior to the patterning of the APF 50 , which is also within the scope of the present invention.
- another trimming process 58 is conducted to narrow the width of the DARC 52 and the APF 50 .
- the etching gas used in this trimming process 58 could be identical or different from the etching gas used in the previous trimming step 56 .
- an etching process is carried out by using the trimmed DARC 52 and APF 50 as mask to remove a portion of the hard mask 48 underneath.
- the DARC 52 could be removed as the hard mask 48 is patterned, or could be removed by a separate etching step prior to the patterning of the hard mask 48 , which is also within the scope of the present invention.
- another trimming process 60 is conducted to narrow the width of the APF 50 and the hard mask 48 .
- the etching gas used in this trimming process 60 could be identical or different from the etching gas used in the previous trimming steps 56 or 58 .
- the patterned resist 54 could also be remained on the DARC 52 until exposing the surface of the polysilicon layer 44 .
- one ore more etching process could be carried by using the patterned resist 54 and DARC 52 as mask to pattern the APF 50 and hard mask 48 until exposing the surface of the polysilicon layer 44 .
- an etching is performed by using the patterned APF 50 and the hard mask 48 as mask to remove a portion of the polysilicon layer 44 underneath.
- the patterned APF 50 and the hard mask 48 could be removed by another etching thereafter.
- the patterned polysilicon layer 44 is preferably used as a gate electrode of a metal-oxide semiconductor (MOS) device, and after the patterned polysilicon 44 is formed, typical MOS fabrication involving the formation of offset spacer, lightly doped drain, main spacer, source/drain region, epitaxial layers, salicides, and contact plugs could be employed to form a MOS structure.
- MOS metal-oxide semiconductor
- the present invention conducts at least two trimming process through the fabrication of a semiconductor structure, such as a polysilicon gate of a MOS device.
- a semiconductor structure such as a polysilicon gate of a MOS device.
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Abstract
A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.
Description
- This is a continuation application of U.S. patent application Ser. No. 12/851,550, filed on Aug. 5, 2010, and all benefits of such earlier application are hereby claimed for this new continuation application.
- 1. Field of the Invention
- The invention relates to a method for fabricating a semiconductor structure, and more particularly, to a method of trimming hard mask for forming a gate electrode layer of a MOS structure.
- 2. Description of the Prior Art
- During the process of manufacturing metal oxide semiconductor transistors (MOS transistors), the formation of a conductive gate plays an important role. In order to meet the demand of miniaturization of the semiconductor industry, the current channel length under the gate must meet the standard of less than 35 nm. To meet the less than 35 nm channel length requirement, it is crucial to control the critical dimension (CD) during the process of exposure of the gate so as to control the line width of the conductive layer (poly-Si layer for example) after the etching process. Because the current lithographic tool techniques are incapable of obtaining the ideal CD, trimming methods are employed in some prior art methods to reduce the size of gate line width. However, most photo resist layers useful in the current gate exposure process are 193 nm photo resist layers which are intrinsically less resistant to the etching condition than 365 nm photo resist layers are on account of acrylic and cycloalkenyl polymer composition in contrast to 365 nm photo resist layers composed of aryl moiety. Furthermore, the thickness of 193 nm photo resist layers reduces as the exposure wavelength shortens. Under the dual disadvantages of poor etching resistance and less and less thickness, it is hard for 193 nm photo resist layers to meet the minimum requirement of 30 nm owing to the available thickness being 10 nm or less during the trimming process on 193 nm photo resist layers.
- In order to overcome the problem, the current techniques deals with the problems by transferring the pattern on the photo resist layer to the hard mask beneath the photo resist layer. After being patterned, the hard mask is ready for the trimming process to reduce the gate line width. In addition, the hard mask must have high etching selectivity to the conductive layer used in forming gate layer. Accordingly, the trimmed hard mask is ready to be the template for etching transfer process to define the line width of gate layer.
- However, as only one trimming process is typically employed on the photo resist layer and the hard mask above the designated gate layer, issues such as line twisting or line less often occur on the hard mask beneath the photo resist layer and result in a flawed gate structure. Moreover, the hard mask is also prone to line collapse during the trimming procedure and the following etching on conductive layer, which would destroy the entire process or the results. Accordingly, it is important to develop a better method for trimming hard masks to form the gate of MOS transistors with ideal gate length.
- It is an objective of the present invention to provide a method of trimming hard masks for fabricating a gate layer of a MOS device.
- According to a preferred embodiment of the present invention, a method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.
- Another aspect of the present invention discloses a method for fabricating a semiconductor structure, which includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; and performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.
- Another aspect of the present invention discloses a method for fabricating a semiconductor structure, which includes the steps of: providing a substrate; depositing a material layer on the substrate; forming a plurality of trimming layers on the material layer; and performing at least a two-step trimming process on the trimming layers such that the trimming layers are trimmed twice.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-4 illustrate a method for fabricating a semiconductor structure according to a preferred embodiment of the present invention. -
FIGS. 5-8 illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention. - Referring to
FIGS. 1-4 ,FIGS. 1-4 illustrate a method for fabricating a semiconductor structure according to a preferred embodiment of the present invention. As shown inFIG. 1 , asubstrate 12, such as a silicon substrate is provided. Next, a gate dielectric layer (not shown) preferably composed of oxide, oxy-nitride, nitrogen-containing dielectric materials or a combination thereof may be formed on the substrate by thermal oxidation, chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). A material layer, such as a silicon layer or apolysilicon layer 14 is then deposited on the gate dielectric layer and at least adielectric layer 16 is formed on thepolysilicon layer 14 thereafter. - The at least one
dielectric layer 16 may be composed of one single dielectric layer or a plurality of dielectric layers. In this embodiment, a plurality of dielectric layers are deposited on thepolysilicon layer 14, in which the dielectric layers include ahard mask 18 and a bottom anti-reflective coating (BARC) 20. In this embodiment, thehard mask 18 could be selected from a material consisting of SiON, SiO2, TEOS, or a combination thereof, and theBARC 20 may be formed from an organic polymer anti-reflective coating material, such as a 365 nm (I-line) resist layer. A patternedresist 22 is formed on the BARC 20 thereafter. - After the patterned
resist 22 is formed, atrimming process 24 could be conducted to narrow the width of the patternedresist 22. Thetrimming process 24 may be accomplished by a plasma etch using gases such as oxygen, ozone, CF4, CHF3 or HBr/O2, and if the target layer to be trimmed were resist material, ashing may be used. - As shown in
FIG. 2 , after trimming the patternedresist 22, an etching process is carried out by using the patterned resist as mask to remove a portion of theBARC 20 underneath. After the pattern of the patternedresist 22 is transferred to theBARC 20, anothertrimming process 26 is conducted to narrow the width of thepatterned resist 22 and the BARC 20. The etching gas used in thistrimming process 26 preferably trims only the target layers such as the aforementioned patternedresist 22 andBARC 20 without affecting any other layer underneath, and could be identical or different from the etching gas used in theprevious trimming step 24. - As shown in
FIG. 3 , after thepatterned resist 22 and theBARC 20 are trimmed, an etching is performed by using the patternedresist 22 and the BARC 20 as mask to remove a portion of thehard mask 18 underneath. As the etching is carried out on thehard mask 18, a portion of thepolysilicon layer 14 surface is exposed and the patternedresist 22 may be etched away as the pattern of the BARC 20 is transferred to thehard mask 18. Next, anothertrimming process 28 could be conducted to narrow the width of the BARC 20 and thehard mask 18. The etching gas used in thistrimming process 28 could be identical or different from the etching gas used in theprevious trimming steps - Preferably, as a substantial amount of
polysilicon layer 14 is lost due to the etching gas used during the trimming procedure, a fixed time were to be calculated for thetrimming process 28 after exposing thepolysilicon layer 14 to control the width difference between the top of thepolysilicon layer 14 and the bottom of thepolysilicon layer 14 no more than 10%. According to a preferred embodiment of the present invention, the fixed time of the trimming procedure is calculated after trimming greater than 70% of a total trimming value. - For instance, if a width of the
BARC 20 and thehard mask 18 were to be reduced from 60 nm to 40 nm after the surface of thepolysilicon layer 14 is exposed, 6 nm from the total of 20 nm being etched away in the trimming procedure would be reserved for thepolysilicon layer 14. As the trimming procedure starts, a fixed time of 30 seconds is calculated to trim the 6 nm for thepolysilicon layer 14. - It should be noted that even though three
trimming processes trimming process - For instance, if only the
trimming processes trimming process 24 by using the un-trimmed patternedresist 22 directly as mask to pattern theBARC 20 and perform thesubsequent trimming processes - Moreover, despite the aforementioned embodiment strips the
patterned resist 22 after thetrimming process 26 by either a separate etching process or along with the patterning of thehard mask 18, the patternedresist 22 could also be remained on the BARC 20 and thehard mask 18 until exposing the surface of thepolysilicon layer 14. In other words, after trimming the patternedresist 22, one ore more etching process could be carried by using thepatterned resist 22 as mask to pattern the BARC 20 andhard mask 18 until exposing the surface of thepolysilicon layer 14. After thepolysilicon layer 14 is exposed, another trimming process is conducted to trim thepatterned resist 22, the patternedBARC 20, and the patternedhard mask 18 before patterning thepolysilicon layer 14. This approach of performing at least two trimming process that all involves the trimming of patterned resist is also within the scope of the present invention. - As shown in
FIG. 4 , after the patternedBARC 20 and thehard mask 18 are trimmed, an etching is performed by using the patternedBARC 20 and thehard mask 18 as mask to remove a portion of thepolysilicon layer 14 underneath for forming a patternedpolysilicon layer 14. The patternedpolysilicon layer 14 is preferably used as a gate electrode of a metal-oxide semiconductor (MOS) device, and after the patternedpolysilicon 14 is formed, typical MOS fabrication involving the formation of offset spacer, lightly doped drain, main spacer, source/drain region, epitaxial layers, stress layers, salicides, and contact plugs could be employed to form a MOS structure. As the fabrication of these MOS structure elements are commonly known to those skilled in the art in this field, the details of which are omitted herein for the sake of brevity. - In another embodiment of the present invention, the material layer can include other suitable materials, such as silicon, silicon oxide or metal. Therefore, the patterned material layer fabricated by above mentioned steps can be used as other semiconductor structure, such as STI or contact plug.
- Referring to
FIGS. 5-8 ,FIGS. 5-8 illustrate a method for fabricating a semiconductor structure according to an embodiment of the present invention. As shown inFIG. 5 , asubstrate 42, such as a silicon substrate is provided. Next, a gate dielectric layer (not shown) preferably composed of oxide, oxy-nitride, nitrogen-containing dielectric materials or a combination thereof may be formed on the substrate by thermal oxidation, chemical vapor deposition (CVD), or plasma enhanced chemical vapor deposition (PECVD). Apolysilicon layer 44 is then deposited on the gate dielectric layer and at least adielectric layer 46 is formed on thepolysilicon layer 44 thereafter. - The at least one
dielectric layer 46 may be composed of one single dielectric layer or a plurality of dielectric layers. In this embodiment, a plurality of dielectric layers are deposited on thepolysilicon layer 44, in which the dielectric layers include ahard mask 48, an advanced patterning film (APF) 50 from Applied Materials, Inc., and a dielectric anti-reflective coating (DARC) 52. In this embodiment, thehard mask 48 could be selected from a material consisting of SiON, SiO2, TEOS, or a combination thereof, and theDARC 52 may be formed from an organic polymer anti-reflective coating material, such as a silicon-rich silicon oxynitride layer. A patterned resist 54 is formed on the DARC thereafter. - An etching is then carried out by using the patterned resist 54 as mask to remove a portion of the
DARC 52 underneath for forming apatterned DARC 52. Despite the patterned resist 54 is used directly as an etching mask for patterning theDARC 52 underneath, a trimming process could be conducted before theDARC 52 is etched. After theDARC 52 is patterned, a trimming process is conducted to narrow the width of the patterned resist 54 and the patternedDARC 52. Thetrimming process 56 may be accomplished by a plasma etch using gases such as oxygen, ozone, CF4, CHF3 or HBr/O2, and if the target layer to be trimmed were resist material, ashing may be used. - As shown in
FIG. 6 , after trimming the patterned resist 54 and theDARC 52, an etching process is carried out by using the patterned resist 54 andDARC 52 as mask to remove a portion of theAPF 50 underneath. Depending on the etchant used for removing theAPF 50, the patterned resist 54 could be removed as theAPF 50 is patterned, or could be removed by a separate etching step prior to the patterning of theAPF 50, which is also within the scope of the present invention. After the pattern of theDARC 52 is transferred to theAPF 50, anothertrimming process 58 is conducted to narrow the width of theDARC 52 and theAPF 50. The etching gas used in thistrimming process 58 could be identical or different from the etching gas used in theprevious trimming step 56. - As shown in
FIG. 7 , after trimming the patternedDARC 52 and theAPF 50, an etching process is carried out by using the trimmedDARC 52 andAPF 50 as mask to remove a portion of thehard mask 48 underneath. Depending on the etchant used for removing thehard mask 48, theDARC 52 could be removed as thehard mask 48 is patterned, or could be removed by a separate etching step prior to the patterning of thehard mask 48, which is also within the scope of the present invention. After the pattern of theAPF 50 is transferred to thehard mask 48, anothertrimming process 60 is conducted to narrow the width of theAPF 50 and thehard mask 48. The etching gas used in thistrimming process 60 could be identical or different from the etching gas used in the previous trimming steps 56 or 58. - Similar to the aforementioned embodiment, even though three
trimming processes process - For instance, if only the trimming processes 58 and 60 were selected to be performed throughout the fabrication, operators could omit the
trimming process 24 by using the un-trimmed patterned resist 54 andDARC 52 directly as mask to pattern theAPF 50 and perform the subsequent trimming processes 58 and 60 as mentioned previously. - Moreover, despite the aforementioned embodiment strips the patterned resist 54 after the
trimming process 56 by either a separate etching process or along with the patterning of theAPF 50, the patterned resist 54 could also be remained on theDARC 52 until exposing the surface of thepolysilicon layer 44. In other words, after trimming the patterned resist 54 and theDARC 52, one ore more etching process could be carried by using the patterned resist 54 andDARC 52 as mask to pattern theAPF 50 andhard mask 48 until exposing the surface of thepolysilicon layer 44. After thepolysilicon layer 44 is exposed, another trimming process is conducted to trim the patterned resist 54, the patternedDARC 52, patternedAPF 50, and the patternedhard mask 48 before transferring the pattern to thepolysilicon layer 44. This approach of performing at least two trimming process that all involves the trimming of patterned resist is also within the scope of the present invention. - As shown in
FIG. 8 , after the patternedAPF 50 and thehard mask 48 are trimmed, an etching is performed by using the patternedAPF 50 and thehard mask 48 as mask to remove a portion of thepolysilicon layer 44 underneath. The patternedAPF 50 and thehard mask 48 could be removed by another etching thereafter. - The patterned
polysilicon layer 44 is preferably used as a gate electrode of a metal-oxide semiconductor (MOS) device, and after the patternedpolysilicon 44 is formed, typical MOS fabrication involving the formation of offset spacer, lightly doped drain, main spacer, source/drain region, epitaxial layers, salicides, and contact plugs could be employed to form a MOS structure. As the fabrication of these MOS structure elements are commonly known to those skilled in the art in this field, the details of which are omitted herein for the sake of brevity. - Overall, the present invention conducts at least two trimming process through the fabrication of a semiconductor structure, such as a polysilicon gate of a MOS device. By applying two or more trimming process on the patterned resist and dielectric layers above the designated polysilicon layer, issued such as line lost or line collapse during the trimming procedure of gate layer formation could be improved substantially.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (21)
1. A method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
depositing a material layer on the substrate;
forming at least one dielectric layer on the material layer;
forming a patterned resist on the dielectric layer;
performing a first trimming process on at least the patterned resist; and
performing a second trimming process on at least the dielectric layer, wherein the second trimming process comprises trimming greater than 70% of a total trimming value.
2. The method of claim 1 , wherein the material layer comprises silicon, polysilicon layer or metal.
3. The method of claim 1 , further comprising calculating a fixed time of the second trimming process after trimming greater than 70% of the total trimming value.
4. The method of claim 1 , wherein the at least one dielectric layer comprises a bottom anti-reflective coating (BARC) and a hard mask.
5. The method of claim 4 , further comprising:
performing the first trimming process on the patterned resist;
using the patterned resist for etching the BARC;
performing the second trimming process on the patterned resist and the BARC;
using the patterned resist and the BARC to etch the hard mask for exposing the material layer;
performing a third trimming process on the BARC and the hard mask; and
using the BARC and the hard mask for etching the material layer.
6. The method of claim 4 , further comprising:
performing the first trimming process on the patterned resist and the BARC;
using the patterned resist and the BARC to etch the hard mask for exposing the material layer;
performing the second trimming process on the BARC and the hard mask; and
using the BARC and the hard mask for etching the material layer.
7. The method of claim 1 , wherein the at least one dielectric layer comprises a dielectric anti-reflective coating (DARC), an advanced patterning film (APF), and a hard mask.
8. The method of claim 7 , further comprising:
performing the first trimming process on the patterned resist and the DARC;
using the patterned resist and the DARC for etching the APF;
performing the second trimming process on the DARC and the APF; and
using the DARC and the APF to etch the hard mask for exposing the material layer; and
performing a third trimming process on the APF and the hard mask; and
using the APF and the hard mask for etching the material layer.
9. The method of claim 7 , further comprising:
performing the first trimming process on the patterned resist and the DARC;
using the patterned resist and the DARC for etching the APF and the hard mask for exposing the material layer;
performing the second trimming process on the APF and the hard mask; and
using the APF and the hard mask for etching the material layer.
10. The method of claim 1 , wherein the second trimming process is conducted according to a fixed time for controlling the width difference between the top of the material layer and the bottom of the material layer no more than 10%.
11. The method of claim 1 , wherein the second trimming process is performed on at least the dielectric layer after exposing the material layer.
12. A method for fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
depositing a material layer on the substrate;
forming at least one dielectric layer on the material layer;
forming a patterned resist on the dielectric layer;
performing a first trimming process on at least the patterned resist; and
performing a second trimming process on at least the dielectric layer after exposing the material layer.
13. The method of claim 12 , wherein the material layer comprises silicon, polysilicon layer or metal.
14. The method of claim 12 further comprising calculating a fixed time of the second trimming process after trimming greater than 70% of the total trimming value.
15. The method of claim 12 , wherein the at least one dielectric layer comprises a bottom anti-reflective coating (BARC) and a hard mask.
16. The method of claim 15 , further comprising:
performing the first trimming process on the patterned resist;
using the patterned resist for etching the BARC;
performing the second trimming process on the patterned resist and the BARC;
using the patterned resist and the BARC to etch the hard mask for exposing the material layer;
performing a third trimming process on the BARC and the hard mask; and
using the BARC and the hard mask for etching the material layer.
17. The method of claim 15 , further comprising:
performing the first trimming process on the patterned resist and the BARC;
using the patterned resist and the BARC to etch the hard mask for exposing the material layer;
performing the second trimming process on the BARC and the hard mask; and
using the BARC and the hard mask for etching the material layer.
18. The method of claim 12 , wherein the at least one dielectric layer comprises a dielectric anti-reflective coating (DARC), an advanced patterning film (APF), and a hard mask.
19. The method of claim 18 , further comprising:
performing the first trimming process on the patterned resist and the DARC;
using the patterned resist and the DARC for etching the APF;
performing the second trimming process on the DARC and the APF; and
using the DARC and the APF to etch the hard mask for exposing the material layer; and
performing a third trimming process on the APF and the hard mask; and
using the APF and the hard mask for etching the material layer.
20. The method of claim 18 , further comprising:
performing the first trimming process on the patterned resist and the DARC;
using the patterned resist and the DARC for etching the APF and the hard mask for exposing the material layer;
performing the second trimming process on the APF and the hard mask; and
using the APF and the hard mask for etching the material layer.
21. The method of claim 12 , wherein the second trimming process is conducted according to a fixed time for controlling the width difference between the top of the material layer and the bottom of the material layer no more than 10%.
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US12/851,550 US8329594B2 (en) | 2010-08-05 | 2010-08-05 | Method for fabricating a semiconductor structure |
US13/666,980 US20130059441A1 (en) | 2010-08-05 | 2012-11-02 | Method for fabricating a semiconductor structure |
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US9564340B2 (en) | 2015-02-03 | 2017-02-07 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
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US8951918B2 (en) * | 2013-03-27 | 2015-02-10 | United Microelectronics Corp. | Method for fabricating patterned structure of semiconductor device |
CN103441067B (en) * | 2013-08-16 | 2016-04-27 | 上海华力微电子有限公司 | Be applied to the double-pattern forming method of grid line end cutting |
CN103441068B (en) * | 2013-08-16 | 2016-03-30 | 上海华力微电子有限公司 | Based on the double-pattern forming method of DARC mask structure |
CN109524300B (en) * | 2018-11-28 | 2021-08-03 | 上海华力微电子有限公司 | Etching method and semiconductor device |
CN111341725B (en) * | 2018-12-19 | 2022-09-13 | 联华电子股份有限公司 | Method for manufacturing semiconductor pattern |
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US6096659A (en) | 1998-04-13 | 2000-08-01 | Advanced Micro Devices, Inc. | Manufacturing process for reducing feature dimensions in a semiconductor |
US6121155A (en) | 1998-12-04 | 2000-09-19 | Advanced Micro Devices | Integrated circuit fabrication critical dimension control using self-limiting resist etch |
US6924088B2 (en) * | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method and system for realtime CD microloading control |
US7306746B2 (en) | 2004-01-30 | 2007-12-11 | Taiwan Semiconductor Manufacturing Co. Ltd. | Critical dimension control in a semiconductor fabrication process |
JP2007081383A (en) * | 2005-08-15 | 2007-03-29 | Fujitsu Ltd | Method of manufacturing fine structure |
US20070161255A1 (en) * | 2006-01-06 | 2007-07-12 | Wilfred Pau | Method for etching with hardmask |
US7851369B2 (en) * | 2006-06-05 | 2010-12-14 | Lam Research Corporation | Hardmask trim method |
US7592265B2 (en) | 2007-01-04 | 2009-09-22 | United Microelectronics Corp. | Method of trimming a hard mask layer, method for fabricating a gate in a MOS transistor, and a stack for fabricating a gate in a MOS transistor |
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US9564340B2 (en) | 2015-02-03 | 2017-02-07 | Samsung Electronics Co., Ltd. | Method of manufacturing semiconductor device |
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