KR100955920B1 - Method for forming salicide of semiconductor device - Google Patents

Method for forming salicide of semiconductor device Download PDF

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KR100955920B1
KR100955920B1 KR1020030003957A KR20030003957A KR100955920B1 KR 100955920 B1 KR100955920 B1 KR 100955920B1 KR 1020030003957 A KR1020030003957 A KR 1020030003957A KR 20030003957 A KR20030003957 A KR 20030003957A KR 100955920 B1 KR100955920 B1 KR 100955920B1
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salicide
region
forming
film
oxide film
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KR20040067018A (en
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이준현
김운용
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매그나칩 반도체 유한회사
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Priority to KR1020030003957A priority Critical patent/KR100955920B1/en
Priority to TW092135665A priority patent/TWI323917B/en
Priority to US10/740,136 priority patent/US7262103B2/en
Publication of KR20040067018A publication Critical patent/KR20040067018A/en
Priority to US11/782,073 priority patent/US7537998B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체소자의 살리사이드 형성방법을 개시한다. 개시된 발명은, 실리콘기판의 비살리사이드 영역과 살리사이드영역의 각각에 상대적으로 두꺼운 두께를 가진 제1게이트산화막과 상대적으로 얇은 두께를 가진 제2게이트산화막을 형성하는 단계; 상기 전체 구조의 상면에 도전층을 형성하는 단계; 상기 도전층 및 제1게이트산화막과 제2게이트산화막을 선택적으로 제거하여 비살리사이드영역과 살리사이드영역 각각에 게이트전극을 형성함과 동시에 상기 살리사이드영역의 활성영역을 드러나게 하는 단계; 상기 게이트전극을 포함한 전체 구조의 상면에 질화막을 형성하는 단계; 상기 살리사이드영역의 질화막부분을 선택적으로 제거하는 단계; 상기 비살리사이드영역에 잔류하는 질화막부분을 제거하는 단계; 상기 게이트전극측면에 스페이서를 형성하는 단계; 및 상기 비살리사이드영역과 살리사이드영역의 게이트전극상면과 살리사이드영역의 활성영역표면에 살리사이드막을 형성하는 단계;를 포함하여 구성되며, 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide) 영역과 비살리 사이드(non-salicide 또는 non-cosalicide)영역을 선택적으로 동시에 형성할 수 있어 공정단계수를 줄일 수 있는 것이다.The present invention discloses a method of forming a salicide of a semiconductor device. The disclosed invention includes forming a first gate oxide film having a relatively thick thickness and a second gate oxide film having a relatively thin thickness in each of a salicide region and a salicide region of a silicon substrate; Forming a conductive layer on an upper surface of the entire structure; Selectively removing the conductive layer, the first gate oxide film, and the second gate oxide film to form a gate electrode in each of the nonsalicide region and the salicide region, and simultaneously revealing an active region of the salicide region; Forming a nitride film on an upper surface of the entire structure including the gate electrode; Selectively removing the nitride film portion of the salicide region; Removing the nitride film portion remaining in the nonsalicide region; Forming a spacer on the side of the gate electrode; And forming a salicide film on an upper surface of the gate electrode of the nonsalicide region, the salicide region, and an active region surface of the salicide region. The salicide region and the non-salicide or non-cosalicide region can be selectively formed simultaneously, thereby reducing the number of process steps.

Description

반도체소자의 살리사이드 형성방법{Method for forming salicide of semiconductor device} Method for forming salicide of semiconductor device

도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도.2A to 2G are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 실리콘기판 33a : 제1게이트산화막31 silicon substrate 33a first gate oxide film

33b : 제2게이트산화막 35 : 폴리실리콘층33b: second gate oxide film 35: polysilicon layer

35a, 35b : 게이트전극 37 : 제1감광막패턴35a, 35b: gate electrode 37: first photosensitive film pattern

39 : ONO박막 41 : 질화막39: ONO thin film 41: nitride film

43 : 제2감광막패턴 45 : 스페이서용 산화막 43: second photosensitive film pattern 45: oxide film for spacer

45a : 스페이서 47 : 살리사이드막45a: spacer 47: salicide film

본 발명은 반도체소자의 살리사이드 형성방법에 관한 것으로서, 보다 상세하게는 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide)영역과 비살리사이드(non-salicide 또는 non-cosalicide)영역을 선택적으로 동시에 형성할 수 있는 반도체소자의 살리사이드 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a salicide of a semiconductor device, and more particularly, to a salicide (salicide or co-salicide) region and a non-salicide (non-salicide or non-cosalicide) region in one chip of a semiconductor device. The present invention relates to a method for forming a salicide of a semiconductor device that can be formed simultaneously.

종래기술에 따른 반도체소자의 살리사이드 형성방법에 대해 도 1a 내지 도 1e를 참조하여 설명하면 다음과 같다.A salicide formation method of a semiconductor device according to the related art will be described with reference to FIGS. 1A to 1E as follows.

도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the related art.

종래기술에 따른 반도체소자의 살리사이드 형성방법은, 도 1a에 도시된 바와같이, 살리사이드가 형성되지 않을 영역(A)과 살리사이드가 형성될 영역(B)으로 분할된 실리콘기판(11)상에 게이트산화막(13)과 게이트전극(15)을 차례로 형성한후 이들 측면에 LDD 스페이서(17)를 형성한다.In the method of forming a salicide of a semiconductor device according to the related art, as illustrated in FIG. 1A, the silicon substrate 11 is divided into a region A in which salicide is not formed and a region B in which salicide is to be formed. After the gate oxide film 13 and the gate electrode 15 are formed in this order, LDD spacers 17 are formed on these side surfaces.

그다음, 도 1b에 도시된 바와같이, 상기 전체 구조의 상면에 산화막(19)을 증착한후 살리사이드가 형성되지 않을 영역(A)에 해당하는 기판부분상에 감광물질층(21) (또는 BARC)을 도포한한다. 이때, 상기 산화막(19)은 나중에 살리사이드 생성과정에서 비살리사이드부위의 살리사이드가 생성되지 않도록 배리어산화막 물질로 작용한다.Then, as shown in FIG. 1B, after depositing the oxide film 19 on the upper surface of the entire structure, the photosensitive material layer 21 (or BARC) on the portion of the substrate corresponding to the region A where salicide is not formed. Apply). At this time, the oxide film 19 serves as a barrier oxide film material so that the salicide of the non-salicide portion is not produced later in the process of forming salicide.

이어서, 도 1c에 도시된 바와같이, 상기 감광물질층(21)을 에치백한후 감광물질층(21)을 제거한다. 이때, 상기 감광물질층(21)의 에치백공정시에 CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한 것이며, 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2 가스 등을 포함할 수 있다. 또한, 상기 감광물질층(21)의 에치백공정을 진행하면서 게이트전극(15)위의 산화막(19)까지 식 각이 진행되어 게이트전극(15)위의 산화막이 잔류하지 않도록 한다.Subsequently, as shown in FIG. 1C, the photosensitive material layer 21 is etched back and the photosensitive material layer 21 is removed. At this time, the etching proceeds using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar during the etch back process of the photosensitive material layer 21, and C 4 F 8 , C 2 F 6 , C 5 CxFy such as F 8 /, N 2 gas and the like. In addition, etching is performed to the oxide film 19 on the gate electrode 15 while the etch back process of the photosensitive material layer 21 is performed so that the oxide film on the gate electrode 15 does not remain.

그다음, 도 1d에 도시된 바와같이, 살리사이드가 형성되지 않을 영역(A)부분에 감광막패턴(23)을 형성한후 상기 제1감광막패턴(23)을 마스크로 상기 살리사이드가 형성될 영역(B)에 해당하는 기판부분에 있는 산화막(19)을 선택적으로 제거한후 감광막패턴(23)을 제거한다. 이때, 상기 산화막(19)의 일부분의 식각진행은 CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한 것이며, 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2 가스 등을 포함할 수 있다. Next, as shown in FIG. 1D, after forming the photoresist pattern 23 on the region A where salicide is not formed, the region where the salicide is to be formed using the first photoresist pattern 23 as a mask ( After selectively removing the oxide film 19 on the substrate corresponding to B), the photoresist pattern 23 is removed. In this case, the etching of the portion of the oxide layer 19 is performed by using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar, and the like C 4 F 8 , C2F 6 , C 5 F 8 And / or CxFy, N 2 gas, and the like.

이어서, 도 1e에 도시된 바와같이, 상기 살리사이드가 형성되지 않을 영역(A)의 게이트전극(15)부분과 살리사이드가 형성될 영역(B)에 해당하는 실리콘기판(11) 및 게이트전극(15)의 노출된 부분에 살리사이드 (또는 Co-salicide) (25)을 형성한다. 이때, 비 살리사이드 부분에는 잔류하는 산화막 배리어에 의해서 살리사이드 (또는 Co-salicide)가 생성되지 않는다.Subsequently, as illustrated in FIG. 1E, the silicon substrate 11 and the gate electrode corresponding to the portion of the gate electrode 15 of the region A in which the salicide is not formed and the region B in which the salicide is to be formed are formed. Form salicide (or Co-salicide) 25 in the exposed portion of 15). At this time, salicide (or co-salicide) is not generated in the non-salicide portion by the remaining oxide barrier.

상기와 같은 종래기술에 의하면, LDD 구조를 형성한다음 감광막패턴을 배리어로 사용하여 살리사이드 부위의 산화막을 제거하고 이어 감광막패턴을 제거한후 살리사이드를 형성하므로 인해 공정 단계수가 증가하게 된다.According to the prior art as described above, since the LDD structure is formed and then the photoresist pattern is used as a barrier, an oxide film of the salicide region is removed, followed by the removal of the photoresist pattern, thereby forming a salicide, thereby increasing the number of process steps.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 반도체 디바이스의 한 개의 칩내에 살리사이드(salicide 또는 Co-salicide) 영역과 비살리사이드(non-salicide 또는 non-cosalicide)영역을 선택 적으로 동시에 형성할 수 있어 공정단계수를 줄일 수 있는 반도체소자의 살리사이드 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and a salicide (salicide or co-salicide) region and a non-salicide (non-salicide or non-cosalicide) region in one chip of a semiconductor device. It is an object of the present invention to provide a method for forming a salicide of a semiconductor device which can be selectively formed simultaneously to reduce the number of process steps.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 살리사이드 형성방법은, 실리콘기판의 비살리사이드 영역과 살리사이드영역의 각각에 상대적으로 두꺼운 두께를 가진 제1게이트산화막과 상대적으로 얇은 두께를 가진 제2게이트산화막을 형성하는 단계; 상기 전체 구조의 상면에 도전층을 형성하는 단계; 상기 도전층 및 제1게이트산화막과 제2게이트산화막을 선택적으로 제거하여 비살리사이드영역과 살리사이드영역 각각에 게이트전극을 형성함과 동시에 상기 살리사이드영역의 활성영역을 드러나게 하는 단계; 상기 게이트전극을 포함한 전체 구조의 상면에 질화막을 형성하는 단계; 상기 살리사이드영역의 질화막부분을 선택적으로 제거하는 단계; 상기 비살리사이드영역에 잔류하는 질화막부분을 제거하는 단계; 상기 게이트전극측면에 스페이서를 형성하는 단계; 및 상기 비살리사이드영역과 살리사이드영역의 게이트전극상면과 살리사이드영역의 활성영역표면에 살리사이드막을 형성하는 단계;를 포함한다.
상기 게이트전극을 형성함과 동시에 상기 살리사이드영역의 활성영역을 드러나게 하는 단계 후, 그리고, 상기 질화막을 형성하는 단계 전, 상기 게이트전극을 포함한 전체 구조의 상면에 ONO막을 형성하는 단계;를 더 포함한다.
상기 질화막과 ONO막의 제거는, CHF3/CF4/O2/Ar 또는 C4F8/O2/Ar 등의 활성화된 플라즈마를 이용하는 식각 방식으로 수행한다.
상기 식각 방식은 1∼200sccm의 CHF3, 1∼200sccm의 CF4, 1∼20sccm의 O2 및 1∼1000sccm의 Ar을 사용하거나, 또는, 1∼50sccm의 C4F8, 1∼500sccm의 N2를 사용하여 수행한다.
상기 질화막의 제거는, 다운 플로우 방식으로 수행한다.
상기 다운 플로우 방식은 식각 가스로서 O2/CF4 가스를 이용하여 수행한다.According to an embodiment of the present invention, a method of forming a salicide of a semiconductor device may include a first gate oxide layer having a relatively thick thickness and a relatively thin thickness in each of a non-salicide region and a salicide region of a silicon substrate. Forming a second gate oxide film; Forming a conductive layer on an upper surface of the entire structure; Selectively removing the conductive layer, the first gate oxide film, and the second gate oxide film to form a gate electrode in each of the nonsalicide region and the salicide region, and simultaneously revealing an active region of the salicide region; Forming a nitride film on an upper surface of the entire structure including the gate electrode; Selectively removing the nitride film portion of the salicide region; Removing the nitride film portion remaining in the nonsalicide region; Forming a spacer on the side of the gate electrode; And forming a salicide film on an upper surface of the gate electrode of the nonsalicide region, the salicide region, and an active region surface of the salicide region.
Forming an ONO film on an upper surface of the entire structure including the gate electrode after forming the gate electrode and simultaneously exposing an active region of the salicide region, and before forming the nitride film; do.
The nitride film and the ONO film are removed by an etching method using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar or C 4 F 8 / O 2 / Ar.
The etching method uses 1 to 200 sccm CHF 3 , 1 to 200 sccm CF 4 , 1 to 20 sccm O 2 and 1 to 1000 sccm Ar, or 1 to 50 sccm C 4 F 8 , 1 to 500 sccm N Do this using 2
The nitride film is removed in a downflow manner.
The downflow method is performed using O 2 / CF 4 gas as an etching gas.

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(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 살리사이드 형성방법을 첨부된 도면을 참조하여 상세히 설명한다. Hereinafter, a method of forming a salicide of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.                     

도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 살리사이드 형성방법을 설명하기 위한 공정단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a salicide of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 살리사이드 형성방법은, 도 2a에 도시된 바와같이, 먼저 살리사이드가 형성되지 않을 영역(A)와 살리사이드영역이 형성될 영역(B)으로 분할된 실리콘기판(31)표면에 두꺼운 게이트산화막(33a)과 얇은 게이트산화막(33b)으로 구성된 이중 게이트산화막을 형성한다. 이때, 상기 두꺼운 게이트산화막(33a)은 비살리사이드영역(A)에 위치하고, 얇은 게이트산화막(33b)는 살리사이드영역(B)에 형성한다.In the method of forming a salicide of a semiconductor device according to the present invention, as shown in FIG. 2A, a silicon substrate 31 is divided into a region A in which salicide is not formed and a region B in which the salicide region is to be formed. A double gate oxide film composed of a thick gate oxide film 33a and a thin gate oxide film 33b is formed on the surface. In this case, the thick gate oxide film 33a is positioned in the nonsalicide region A, and the thin gate oxide film 33b is formed in the salicide region B.

그다음, 이중 게이트산화막상에 게이트 형성용 폴리실리콘층(35)을 증착한후 그 위에 폴리실리콘층 패터닝용 제1감광막패턴(37)을 형성한다. 이때, 상기 제1감광막패턴(37)는 비살리사이드영역(A)과 살리사이드영역(B) 각각에 형성한다.Thereafter, a gate forming polysilicon layer 35 is deposited on the double gate oxide layer, and then a first photoresist pattern 37 for patterning the polysilicon layer is formed thereon. In this case, the first photoresist pattern 37 is formed in each of the salicide region (A) and the salicide region (B).

이어서, 도 2b에 도시된 바와같이, 상기 제1감광막패턴(37)을 마스크로 상기 폴리실리콘층(35)을 선택적으로 제거하여 게이트전극(35a)(35b)을 형성한다.Subsequently, as shown in FIG. 2B, the polysilicon layer 35 is selectively removed using the first photoresist pattern 37 as a mask to form gate electrodes 35a and 35b.

그다음, 상기 제1감광막패턴(37)을 제거한후 게이트전극(35a)(35b)을 포함한 전체 구조의 상면에 ONO박막(39)과 질화막(41)을 적층한후 상기 비살리사이드영역(A)상에만 제2감광막패턴(43)을 형성한다.Next, after removing the first photoresist pattern 37, the ONO thin film 39 and the nitride film 41 are stacked on the upper surface of the entire structure including the gate electrodes 35a and 35b, and then the unsalicide region A is formed. The second photoresist pattern 43 is formed only on it.

이어서, 도 2c에 도시된 바와같이, 상기 제2감광막패턴(43)을 마스크로 상기 살리사이드영역(B)의 질화막(41)과 ONO박막(39)부분을 제거한다.이때, 상기 질화막(41)과 ONO박막(39)의 식각진행은, CHF3/CF4/O2/Ar 등의 활성화된 플라즈마를 이용하여 식각진행한다. 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2 가스 등을 포함할 수 있다. 여기서, 식각가스 및 가스유량으로는 CHF3 : 1∼200sccm, CF4 : 1∼200sccm, O2 : 0∼20sccm, Ar : 1∼1000sccm이거나 이들외에 C4F8,: 1∼50sccm, N 2, : 0∼500sccm을 사용한다.Subsequently, as shown in FIG. 2C, the nitride film 41 and the ONO thin film 39 portion of the salicide region B are removed by using the second photoresist pattern 43 as a mask. ) And the ONO thin film 39 are etched using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar. It may include CxFy, N 2 gas, such as C 4 F 8 , C 2 F 6 , C 5 F 8 /. Here, the etching gas and the gas flow rate may be CHF 3 : 1-200 sccm, CF 4 : 1-200 sccm, O 2 : 0-20 sccm, Ar: 1-1000 sccm, or else C 4 F 8 ,: 1-50 sccm, N 2 ,: 0 to 500sccm is used.

그다음, 제2감광막패턴(43)은 O2 플라즈마 또는 O2 다운 플로우 방식을 이용하여 제거한다. Next, the second photoresist pattern 43 is removed using an O 2 plasma or O 2 down flow method.

이어서, 도 2d에 도시된 바와같이, 다운 플로우 방식으로 블랭킷식각을 진행하여 상기 잔류하는 질화막(41)과 ONO박막(39)부분을 선택적으로 제거한다. 이때, 질화막 식각은 O2/CF4 가스를 이용한 다운 플로우(down flow)방식으로 진행한다. 이렇게 다운 플로우 방식으로 식각을 진행하게 되면 질화막과 산화막간의 선택비가 12:1정도가 되어 산화막 물질은 거의 제거되지 않게 되어 상기 ONO박막(39)부분중 NO부분만 제거되고 O(oxide)부분만 남게 된다.Next, as shown in FIG. 2D, blanket etching is performed in a downflow manner to selectively remove the remaining nitride film 41 and the ONO thin film 39. At this time, the nitride film etching is performed in a down flow method using O 2 / CF 4 gas. When the etching is performed in the downflow manner, the selectivity between the nitride film and the oxide film is about 12: 1, so that the oxide material is hardly removed. Only the NO part of the ONO thin film 39 is removed and only the O (oxide) part remains. do.

그다음, 도 2e에 도시된 바와같이, 전체 구조의 상면에 LDD구조를 만들기 위한 산화막(45)을 증착한다.Then, as shown in Fig. 2E, an oxide film 45 for forming an LDD structure is deposited on the upper surface of the entire structure.

이어서, 도 2f에 도시된 바와같이, 상기 산화막(45)을 건식식각하여 게이트전극(35a)(35b)측면에 스페이서(45a)을 형성한다. 이때, 상기 산화막(45)의 식각진행은 CHF3/CF4/O2/Ar 또는 C4F8/O2/Ar 등의 활성화된 플라즈마를 이용하여 진행한다. 여기에 C4F8, C2F6, C5F8/등의 CxFy, N2, O2 등을 포함할 수 있다. 이렇게 식각공정을 진행하게 되면, 비살리사이드영역(A)부분의 활성영역에는 잔류산화막이 계속 남게 되고, 나머지 부분인 이중 게이트전극부분과 살리사이드영역(B)가 형성될 활성영역표면에는 산화막이 남지 않게 된다.Subsequently, as illustrated in FIG. 2F, the oxide layer 45 is dry-etched to form spacers 45a on the side surfaces of the gate electrodes 35a and 35b. In this case, the etching process of the oxide layer 45 is performed using an activated plasma such as CHF 3 / CF 4 / O 2 / Ar or C 4 F 8 / O 2 / Ar. It may include C 4 F 8 , C 2 F 6 , C 5 F 8 / CxFy, N 2 , O 2 , and the like. When the etching process is performed, the remaining oxide film remains in the active region of the non-salicide region (A), and the oxide film is formed on the surface of the active region where the remaining double gate electrode portion and the salicide region (B) are to be formed. It will not remain.

그다음, 도 2g에 도시된 바와같이, 상기 드러난 이중 게이트전극(35a)(35b)상면과 살리사이드영역(B)의 활성영역표면에 살리사이드막(47)을 형성한다.Then, as shown in FIG. 2G, a salicide film 47 is formed on the exposed double gate electrodes 35a and 35b and on the active region surface of the salicide region (B).

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 살리사이드 형성방법에 의하면, 감광막(또는, BARC)의 에치백공정을 진행하지 않기 때문에 공정상 파티클에 대한 오염이 적게 된다.As described above, according to the method for forming a salicide of a semiconductor device according to the present invention, since the etch back process of the photosensitive film (or BARC) is not performed, contamination to particles is reduced in the process.

또한, 기존과는 다르게 LDD스페이서를 형성하는 단계에서 비살리사이드 (또는 Co-salicide)와 살리사이드영역을 구분하여 형성시킬 수 있게 된다.In addition, unlike the conventional method, the non-salicide (or co-salicide) and the salicide region may be formed by forming the LDD spacer.

그리고, 비살리사이드영역과 살리사이드영역에 선택적으로 살리사이드를 형성할 수 있게 된다.Then, the salicide can be selectively formed in the nonsalicide region and the salicide region.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (6)

실리콘기판의 비살리사이드 영역과 살리사이드영역의 각각에 제1게이트산화막과 상기 제1게이트산화막 보다 상대적으로 얇은 두께를 가진 제2게이트산화막을 형성하는 단계;Forming a first gate oxide film and a second gate oxide film having a thickness relatively thinner than that of the first gate oxide film in each of the nonsalicide region and the salicide region of the silicon substrate; 상기 전체 구조의 상면에 도전층을 형성하는 단계;Forming a conductive layer on an upper surface of the entire structure; 상기 도전층 및 제1게이트산화막과 제2게이트산화막을 선택적으로 제거하여 비살리사이드영역과 살리사이드영역 각각에 게이트전극을 형성하는 단계;Selectively removing the conductive layer, the first gate oxide film, and the second gate oxide film to form a gate electrode in each of the nonsalicide region and the salicide region; 상기 게이트전극을 포함한 전체 구조의 상면에 ONO막 및 질화막을 차례로 형성하는 단계;Sequentially forming an ONO film and a nitride film on the upper surface of the entire structure including the gate electrode; 상기 살리사이드영역의 질화막 및 ONO막 부분을 선택적으로 제거하는 단계;Selectively removing portions of the nitride film and the ONO film of the salicide region; 상기 비살리사이드영역에 잔류하는 질화막부분을 제거하는 단계;Removing the nitride film portion remaining in the nonsalicide region; 상기 비살리사이드영역과 살리사이드영역 상에 산화막을 형성하는 단계; Forming an oxide film on the salicide region and the salicide region; 상기 게이트전극의 상면이 노출되도록 상기 산화막을 식각하여 상기 비살리사이드 영역과 살리사이드 영역 각각에 형성된 상기 게이트전극측면에 스페이서를 형성하는 단계; 및Etching the oxide layer to expose the top surface of the gate electrode to form a spacer on the gate electrode side surface formed in each of the nonsalicide region and the salicide region; And 상기 비살리사이드영역과 살리사이드영역의 게이트전극상면과 살리사이드영역의 활성영역표면에 살리사이드막을 형성하는 단계;Forming a salicide film on an upper surface of the gate electrode of the nonsalicide region and the salicide region and an active region surface of the salicide region; 를 포함하여 구성되는 것을 특징으로 하는 반도체소자의 살리사이드 형성방법.Salicide forming method of a semiconductor device comprising a. 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 질화막과 ONO막의 제거는, CHF3/CF4/O2/Ar 또는 C4F8/O2/Ar 의 활성화된 플라즈마를 이용하는 식각 방식으로 수행하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The removal of the nitride film and the ONO film is performed by an etching method using an activated plasma of CHF 3 / CF 4 / O 2 / Ar or C 4 F 8 / O 2 / Ar. . 제 3 항에 있어서,The method of claim 3, wherein 상기 식각 방식은 1∼200sccm의 CHF3, 1∼200sccm의 CF4, 1∼20sccm의 O2 및 1∼1000sccm의 Ar을 사용하거나, 또는, 1∼50sccm의 C4F8, 1∼500sccm의 N2를 사용하여 수행하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The etching method uses 1 to 200 sccm CHF 3 , 1 to 200 sccm CF 4 , 1 to 20 sccm O 2 and 1 to 1000 sccm Ar, or 1 to 50 sccm C 4 F 8 , 1 to 500 sccm N Salicide formation method of a semiconductor device, characterized in that carried out using 2 . 제 1 항에 있어서,The method of claim 1, 상기 질화막의 제거는, 다운 플로우 방식으로 수행하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The removal of the nitride film, the salicide forming method of a semiconductor device, characterized in that performed in a downflow method. 제 5 항에 있어서,The method of claim 5, 상기 다운 플로우 방식은 식각 가스로서 O2/CF4 가스를 이용하여 수행하는 것을 특징으로하는 반도체소자의 살리사이드 형성방법.The downflow method is a salicide forming method of a semiconductor device, characterized in that carried out using an O 2 / CF 4 gas as an etching gas.
KR1020030003957A 2003-01-21 2003-01-21 Method for forming salicide of semiconductor device KR100955920B1 (en)

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US10/740,136 US7262103B2 (en) 2003-01-21 2003-12-18 Method for forming a salicide in semiconductor device
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Publication number Priority date Publication date Assignee Title
KR19990048485A (en) * 1997-12-10 1999-07-05 구본준 Manufacturing Method of Semiconductor Device
US6337240B1 (en) * 1998-10-21 2002-01-08 United Microelectronics Corp. Method for fabricating an embedded dynamic random access memory
JP2002353330A (en) 2001-05-25 2002-12-06 Denso Corp Semiconductor device and its manufacturing method
KR20040057641A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for forming salicide of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990048485A (en) * 1997-12-10 1999-07-05 구본준 Manufacturing Method of Semiconductor Device
US6337240B1 (en) * 1998-10-21 2002-01-08 United Microelectronics Corp. Method for fabricating an embedded dynamic random access memory
JP2002353330A (en) 2001-05-25 2002-12-06 Denso Corp Semiconductor device and its manufacturing method
KR20040057641A (en) * 2002-12-26 2004-07-02 주식회사 하이닉스반도체 Method for forming salicide of semiconductor device

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