KR100575871B1 - Method for forming metal line contact of semiconductor device - Google Patents

Method for forming metal line contact of semiconductor device Download PDF

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KR100575871B1
KR100575871B1 KR1020030091414A KR20030091414A KR100575871B1 KR 100575871 B1 KR100575871 B1 KR 100575871B1 KR 1020030091414 A KR1020030091414 A KR 1020030091414A KR 20030091414 A KR20030091414 A KR 20030091414A KR 100575871 B1 KR100575871 B1 KR 100575871B1
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sion
hard mask
layer
low dielectric
mask layer
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KR20050059700A (en
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길민철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

본 발명은 금속배선콘택 형성방법을 개시한다. 개시된 발명은 실리콘기판 상에 마련된 하부층간절연막상에 금속배선을 형성하는 단계; 상기 금속배선을 포함 한 하부층간절연막상에 SiON 박막을 형성하는 단계; 상기 SiON박막을 선택적으로 제거하여 상기 금속배선측면에 SiON 스페이서를 형성하는 단계; 상기 SiON 스페 이서를 포함한 전체 구조의 상면에 저유전상수물질층과 제2하드마스크층을 차례로 적층하는 단계; 및 상기 제2하드마스크층과 저유전상수물질층을 차례로 식각하여 상기 금속배선상면을 노출시키는 비아홀을 형성하는 단계를 포함하여 구성된다.The present invention discloses a method for forming a metal wiring contact. The disclosed invention comprises the steps of forming a metal wiring on the lower interlayer insulating film provided on the silicon substrate; Forming a SiON thin film on the lower interlayer insulating film including the metal wiring; Selectively removing the SiON thin film to form a SiON spacer on the metal wiring side; Sequentially stacking a low dielectric constant material layer and a second hard mask layer on an upper surface of the entire structure including the SiON spacer; And etching the second hard mask layer and the low dielectric constant material layer in order to form a via hole exposing the upper surface of the metal wiring.

Description

반도체소자의 금속배선콘택 형성방법{Method for forming metal line contact of semiconductor device} Method for forming metal line contact of semiconductor device

도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도,1A to 1E are cross-sectional views illustrating a method for forming a metallization contact of a semiconductor device according to the prior art;

도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도.2A to 2G are cross-sectional views illustrating a method of forming a metallization contact of a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 하부절연막 33 : 금속층31: lower insulating film 33: metal layer

35 : TiN층 37 : 제1하드마스크층35 TiN layer 37 First hard mask layer

39 : 하부금속배선 41 : SiON 박막39: lower metal wiring 41: SiON thin film

41a : SiON 스페이서 43 : 저유전상수물질층41a: SiON spacer 43: low dielectric constant material layer

45 : 제2하드마스크층 47 : 감광막패턴45: second hard mask layer 47: photosensitive film pattern

49 : 비아홀49: via hole

본 발명은 반도체소자의 금속배선콘택 형성방법에 관한 것으로서, 보다 상세 하게는 중간금속유전체(inter metal dielectric ; IMD)층을 증착하기 전에 금속위에 TiN/SiON막의 제거목적으로 SiON막을 증착한후 등방성 식각으로 TiN/SiON막을 제거하므로써 실제 비아콘택 식각시에 저유전물질막의 어택(attack)없이 식각할 수 있는 반도체소자의 금속배선콘택 형성방법에 관한 것이다.The present invention relates to a method for forming a metal interconnection contact of a semiconductor device, and more particularly, isotropic etching after depositing a SiON film for the purpose of removing a TiN / SiON film on the metal before depositing an inter metal dielectric (IMD) layer. The present invention relates to a method for forming a metal interconnection contact of a semiconductor device which can be etched without attacking a low dielectric material film during actual via contact etching by removing a TiN / SiON film.

종래기술에 따른 반도체소자의 금속배선콘택 형성방법에 대해 도 1a 내지 도 1e를 참조하여 설명하면 다음과 같다.A method of forming a metallization contact of a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1E as follows.

도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도이다.1A through 1E are cross-sectional views illustrating a method of forming a metallization contact of a semiconductor device according to the related art.

종래기술에 따른 반도체소자의 금속배선콘택 형성방법은, 도 1a에 도시된 바와같이, 실리콘기판(미도시)상에 층간절연막(11)을 증착한후 그 위에 금속층(13), TiN박막(15) 및 SiON 하드마스크층(17)을 차례로 적층한다.In the method of forming a metallization contact of a semiconductor device according to the related art, as shown in FIG. 1A, an interlayer insulating film 11 is deposited on a silicon substrate (not shown), and then a metal layer 13 and a TiN thin film 15 are deposited thereon. ) And the SiON hard mask layer 17 are sequentially stacked.

그다음, 상기 금속층(13), TiN박막(15) 및 SiON 하드마스크층(17)을 포토공정 및 식각공정을 거쳐 패터닝하여 금속배선(19)을 형성한다.Next, the metal layer 13, the TiN thin film 15, and the SiON hard mask layer 17 are patterned through a photo process and an etching process to form a metal wiring 19.

이어서, 상기 금속배선(19)을 포함한 전체 구조의 상면에 저유전상수 물질층(21)과 제2하드마스크층(23)을 차례로 증착한후 그 위에 비아콘택을 형성하기 위한 마스크로 사용할 포토레지스트를 도포한다.Subsequently, the low dielectric constant material layer 21 and the second hard mask layer 23 are sequentially deposited on the upper surface of the entire structure including the metal wiring 19, and then a photoresist to be used as a mask for forming a via contact thereon is used. Apply.

그다음, 포토리쏘그라피 공정기술에 의한 노광 및 현상공정을 진행한후 이를 선택적으로 제거하여 감광막패턴(25)을 형성한다.Then, after performing the exposure and development process by the photolithography process technology, it is selectively removed to form the photoresist pattern 25.

이어서, 도 1b에 도시된 바와같이, 상기 감광막패턴(25)을 마스크로 상기 제2하드마스크층(23)을 건식식각한다.Subsequently, as illustrated in FIG. 1B, the second hard mask layer 23 is dry-etched using the photoresist pattern 25 as a mask.

그다음, 도 1c에 도시된 바와같이, 상기 감광막패턴(25)을 제거한후 상기 건식식각된 제2하드마스크층(23)을 마스크로 상기 저유전상수물질층(21)을 건식식각하여 상기 SiON 하드마스크층(17)의 상면을 노출시킨다.Next, as shown in FIG. 1C, after removing the photoresist pattern 25, the low dielectric constant material layer 21 is dry-etched using the dry-etched second hard mask layer 23 as a mask to form the SiON hard mask. The top surface of layer 17 is exposed.

이어서, 도 1d에 도시된 바와같이, 제2하드마스크층(23a)과 건식식각된 저유전상수물질층(21)을 마스크로 노출되어 있는 SiON 하드마스크층(17)을 일정두께만큼 건식식각한다. 이때, 상기 SiON 하드마스크층(17) 식각시에 제2하드마스크층 (23)의 상단 가장자리부(edge)가 깨어지게 된다.Subsequently, as illustrated in FIG. 1D, the SiON hard mask layer 17 having the second hard mask layer 23a and the dry etched low dielectric constant material layer 21 exposed as a mask is dry-etched by a predetermined thickness. At this time, an upper edge of the second hard mask layer 23 is broken when the SiON hard mask layer 17 is etched.

그다음, 도 1e에 도시된 바와같이, 제2하드마스크층(25b)과 저유전상수물질층(21)을 마스크로 남아 있는 SiON 하드마스크층(17)과 TiN 박막(15)을 차례로 건식식각하여 상기 금속층(13)상면을 노출시키는 비아홀(27)을 형성한다. 이때, 비아홀(27) 식각시에, 상기 제2하드마스크층(25b)과 저유전상수물질층(21)의 일부가 식각된다.Next, as shown in FIG. 1E, the SiON hard mask layer 17 and the TiN thin film 15, which remain as the masks of the second hard mask layer 25b and the low dielectric constant material layer 21, are sequentially dry-etched to perform the above etching. The via hole 27 exposing the upper surface of the metal layer 13 is formed. At this time, when the via hole 27 is etched, a portion of the second hard mask layer 25b and the low dielectric constant material layer 21 are etched.

그러나, 종래의 유기 저유전상수물질을 사용한 비아콘택 형성공정의 경우에 금속위의 반사방지막 개념을 넘어서 하드마스크 개념으로 사용된 SiON층을 식각할 때, 금속위의 TiN/SiON 막의 식각이 진행됨에 따라 산화막 제2하드마스크층의 상단부분이 깨어져서 결국 저유전상수 유전막이 함께 식각되는 문제점이 발생되었다.However, in the case of the via contact forming process using the organic low dielectric constant material, when the SiON layer used as the hard mask concept is etched beyond the antireflection film on the metal, as the etching of the TiN / SiON film on the metal proceeds, The upper portion of the oxide second hard mask layer is broken, resulting in a problem that the low dielectric constant dielectric film is etched together.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 중간금속유전체(inter metal dielectric ; IMD)층을 증착하기 전에 금속위 에 TiN/SiON막의 제거목적으로 SiON막을 증착한후 등방성 식각으로 TiN/SiON막을 제거하므로써 실제 비아콘택 식각시에 저유전물질막의 어택(attack)없이 식각할 수 있는 반도체소자의 금속배선콘택 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, isotropic etching after depositing a SiON film for the purpose of removing the TiN / SiON film on the metal before depositing the inter-metal dielectric (IMD) layer It is an object of the present invention to provide a method for forming a metal interconnection contact of a semiconductor device which can be etched without attacking a low dielectric material film during actual via contact etching by removing a TiN / SiON film.

상기 목적을 달성하기 위한 본 발명에 따른 금속배선콘택 형성방법은 실리콘기판상에 마련된 하부층간절연막상에 금속층, TiN층 및 SiON 하드마스크층을 포함하는 금속배선을 형성하는 단계; 상기 금속배선을 포함한 하부층간절연막상에 SiON 박막을 형성하는 단계; 상기 SiON박막을 상기 SiON 하드마스크층과 TiN층과 함께 순차적으로 이방성 식각하여 상기 금속층의 측면에 SiON 스페이서를 형성하는 단계; 상기 SiON 스페이서를 포함한 전체 구조의 상면에 저유전상수물질층과 하드마스크층을 차례로 적층하는 단계; 및 상기 하드마스크층과 저유전상수물질층을 차례로 식각하여 상기 금속배선상면을 노출시키는 비아홀을 형성하는 단계를 포함한다.Metal interconnection contact forming method according to the present invention for achieving the above object comprises the steps of forming a metal wiring including a metal layer, a TiN layer and a SiON hard mask layer on the lower interlayer insulating film provided on a silicon substrate; Forming a SiON thin film on the lower interlayer insulating film including the metal wiring; Sequentially anisotropically etching the SiON thin film together with the SiON hard mask layer and the TiN layer to form a SiON spacer on the side of the metal layer; Sequentially stacking a low dielectric constant material layer and a hard mask layer on an upper surface of the entire structure including the SiON spacers; And etching the hard mask layer and the low dielectric constant material layer in order to form a via hole exposing the upper surface of the metal wiring.

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(실시예)(Example)

이하, 본 발명에 따른 금속배선콘택 형성방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a metal wiring contact according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따른 반도체소자의 금속배선콘택 형성방법을 설명하기 위한 공정단면도이다.2A to 2G are cross-sectional views illustrating a method of forming a metallization contact of a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 금속배선콘택 형성방법은, 도 2a에 도시된 바 와같이, 먼저 실리콘기판(미도시)상에 층간절연막(31)을 증착한후 그 위에 금속층(33), TiN박막(35) 및 제1하드마스크층(37)을 차례로 적층한다.In the method for forming a metal interconnection contact of a semiconductor device according to the present invention, as shown in FIG. (35) and the first hard mask layer 37 are laminated in this order.

그다음, 포토마스크공정 및 식각공정을 거쳐 상기 금속층(33), TiN박막(35) 및 제1하드마스크층(37)을 패터닝하여 금속배선(39)을 형성한다.Next, the metal layer 33, the TiN thin film 35, and the first hard mask layer 37 are patterned through a photomask process and an etching process to form a metal wiring 39.

이어서, 도 2b에 도시된 바와같이, 상기 금속배선(39)을 포함한 전체 구조의 상면에 300∼1000Å 두께로 SiON 박막(41)을 증착한다. 이때, 상기 SiON 박막 증착시의 조성물질로는 비정질 실리콘, SiO2, Si3N4 로 구성한다.Subsequently, as shown in FIG. 2B, a SiON thin film 41 is deposited on the upper surface of the entire structure including the metal wiring 39 to a thickness of 300 to 1000 GPa. At this time, the composition of the SiON thin film deposition is composed of amorphous silicon, SiO 2 , Si 3 N 4 .

그다음, 도 2c에 도시된 바와같이, 상기 SiON 박막(41)을 감광막패턴없이 이방성 식각 방법으로 제거하여 상기 금속층(33)의 측면에 SiON 스페이서(41a)을 형성한다. 이때, 상기 SiON 박막(41) 식각시에 금속배선(39)을 구성하는 제1하드마스크층(37)과 TiN층(35)부분도 함께 식각된다. 또한, 상기 SiON 박막(41)의 이방성 식각시에 플루오린 계열의 가스를 사용하고, 첨가 기체로는 O2, CO, Ar 기체를 사용한다.Next, as shown in FIG. 2C, the SiON thin film 41 is removed by an anisotropic etching method without a photosensitive film pattern to form a SiON spacer 41a on the side surface of the metal layer 33. At this time, the portion of the first hard mask layer 37 and the TiN layer 35 constituting the metal wiring 39 are also etched when the SiON thin film 41 is etched. In addition, a fluorine-based gas is used for anisotropic etching of the SiON thin film 41, and O 2 , CO, and Ar gas are used as the additive gas.

이어서, 도 2d에 도시된 바와같이, 상기 SiON 스페이서(41a)를 포함한 전체 구조의 상면에 저유전상수물질층(43)과 제2하드마스크층(45)을 차례로 증착한후 그 위에 감광물질을 도포한다. 이때, 상기 상기 제2하드마스크층(45)는 1000∼5000Å 두께로 증착한다.Subsequently, as shown in FIG. 2D, the low dielectric constant material layer 43 and the second hard mask layer 45 are sequentially deposited on the upper surface of the entire structure including the SiON spacer 41a and then a photosensitive material is applied thereon. do. In this case, the second hard mask layer 45 is deposited to a thickness of 1000 ~ 5000Å.

그다음, 상기 감광물질을 포토리쏘그라피 공정기술에 의한 노광 및 현상공정을 진행한후 이를 선택적으로 제거하여 감광막패턴(47)을 형성한다.Thereafter, the photosensitive material is exposed to light and developing by a photolithography process technology, and then selectively removed to form the photoresist pattern 47.

이어서, 도 2e에 도시된 바와같이, 상기 감광막패턴(47)을 마스크로 상기 제2하드마스크층(45)을 건식식각하여 상기 저유전상수물질층(43)상면을 노출시킨다. 이때, 상기 제2하드마스크층 식각시에 플루오린 계열의 가스를 사용하고, 첨가 기체로는 O2, CO, Ar 기체를 사용한다. 또한, 상기 제2하드마스크층 식각시에 감광막패턴(47)도 일정두께만큼 식각된다.Subsequently, as illustrated in FIG. 2E, the second hard mask layer 45 is dry-etched using the photoresist pattern 47 as a mask to expose an upper surface of the low dielectric constant material layer 43. In this case, a fluorine-based gas is used for etching the second hard mask layer, and O 2 , CO, and Ar gas are used as the additive gas. In addition, the photoresist pattern 47 is also etched by a predetermined thickness when the second hard mask layer is etched.

그다음, 도 2f에 도시된 바와같이, 상기 감광막패턴(47)과 상기 건식식각된 제2하드마스크층(45a)을 마스크로 상기 저유전상수물질층(41)을 건식식각한다. 이때, 상기 저유전상수물질층의 식각시에 식각기체로는 O2, N2, Ar, SO2 기체를 사용한다. 또한, 상기 건식식각공정시에 감광막패턴(47a)은 모두 식각된다.Next, as shown in FIG. 2F, the low dielectric constant material layer 41 is dry-etched using the photoresist pattern 47 and the dry-etched second hard mask layer 45a as a mask. At this time, when etching the low dielectric constant material layer is used as an etching gas O 2 , N 2 , Ar, SO 2 gas. In addition, all of the photoresist pattern 47a is etched during the dry etching process.

이어서, 도 2g에 도시된 바와같이, 남아 있는 제2하드마스크층(45a)을 마스크로 상기 금속층(33)상면에 남아 있는 저유전상수물질층(41)부분을 제거하여 비아홀(49)을 형성한다. 이때, 상기 저유전상수물질층을 사용한 비아홀 형성공정은 인시튜 또는 엑스 시튜 방식에 의해 진행한다. 또한, 상기 비아홀(49)은 5000∼15000Å정도의 콘택 깊이를 갖는다. 한편, 상기 저유전상수물질층에 대한 감광막패턴의 선택비는 0.5∼1.5가 되도록 한다. Subsequently, as shown in FIG. 2G, a portion of the low dielectric constant material layer 41 remaining on the upper surface of the metal layer 33 is removed using the remaining second hard mask layer 45a as a mask to form a via hole 49. . In this case, the via hole forming process using the low dielectric constant material layer is performed by an in-situ or x-situ method. In addition, the via hole 49 has a contact depth of about 5000 to 15000 kPa. On the other hand, the selection ratio of the photosensitive film pattern to the low dielectric constant material layer is to be 0.5 to 1.5.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 금속배선콘택 형성방법에 의하면, 중간금속유전체(inter metal dielectric ; IMD)층을 증착하기 전에 금속층위에 TiN/SiON막의 제거목적으로 SiON막을 증착한후 이방성 식각으로 TiN/SiON막을 제거하므로써 실제 비아콘택 식각시에 저유전물질막의 어택(attack)없이 식각할 수 있으므로 반도체공정 개발 기간을 단축시키는 효과가 있다. As described above, according to the method for forming a metal wiring contact of a semiconductor device according to the present invention, after depositing a SiON film on the metal layer for the purpose of removing the TiN / SiON film before depositing the inter metal dielectric (IMD) layer By removing the TiN / SiON film by anisotropic etching, it is possible to etch without attack of the low dielectric material film during the actual via contact etching, thereby shortening the semiconductor process development period.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (15)

실리콘기판상에 마련된 하부층간절연막상에 금속층, TiN층 및 SiON 하드마스크층을 포함하는 금속배선을 형성하는 단계;Forming a metal wiring including a metal layer, a TiN layer, and a SiON hard mask layer on a lower interlayer insulating film provided on a silicon substrate; 상기 금속배선을 포함한 하부층간절연막상에 SiON 박막을 형성하는 단계;Forming a SiON thin film on the lower interlayer insulating film including the metal wiring; 상기 SiON박막을 상기 SiON 하드마스크층과 TiN층과 함께 순차적으로 이방성 식각하여 상기 금속층의 측면에 SiON 스페이서를 형성하는 단계;Sequentially anisotropically etching the SiON thin film together with the SiON hard mask layer and the TiN layer to form a SiON spacer on the side of the metal layer; 상기 SiON 스페이서를 포함한 전체 구조의 상면에 저유전상수물질층과 하드마스크층을 차례로 적층하는 단계; 및Sequentially stacking a low dielectric constant material layer and a hard mask layer on an upper surface of the entire structure including the SiON spacers; And 상기 하드마스크층과 저유전상수물질층을 차례로 식각하여 상기 금속배선상면을 노출시키는 비아홀을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.And forming a via hole exposing the upper surface of the metal wiring by sequentially etching the hard mask layer and the low dielectric constant material layer. 삭제delete 삭제delete 삭제delete 제1항에 있어서, 상기 SiON 박막의 이방성 식각시에 플루오린 계열의 가스를 사용하고, 첨가 기체로는 O2, CO, Ar 기체를 사용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein a fluorine-based gas is used for anisotropic etching of the SiON thin film, and an additive gas is O 2 , CO, or Ar gas. 제1항에 있어서, 상기 SiON 박막은 300∼1000Å 두께로 증착하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the SiON thin film is deposited to a thickness of 300 to 1000 Å. 제1항에 있어서, 상기 비아홀 형성공정은 3번에 걸친 건식식각공정을 거쳐 수행하는 것을 특징으로하는 반도체소자의 금속배선 콘택 형성방법.The method of claim 1, wherein the via hole forming process is performed through three dry etching processes. 제1항에 있어서, 상기 하드마스크층은 1000∼5000Å 두께로 증착하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the hard mask layer is deposited to a thickness of 1000 to 5000 GPa. 제1항에 있어서, 상기 하드마스크층 식각시에 플루오린 계열의 가스를 사용하고, 첨가 기체로는 O2, CO, Ar 기체를 사용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein a fluorine-based gas is used for etching the hard mask layer, and O 2 , CO, or Ar gas is used as an additive gas. 제1항에 있어서, 상기 저유전상수물질층의 식각시에 식각기체로는 O2, N2, Ar, SO2 기체를 사용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the low dielectric constant as the etching gas during etching of the material layer is O 2, N 2, Ar, the metal wire contact method for forming a semiconductor device characterized by using SO 2 gas. 제1항에 있어서, 상기 저유전상수물질층을 사용한 비아홀 형성공정은 인시튜 또는 엑스 시튜 방식에 의해 진행하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the via hole forming process using the low dielectric constant material layer is performed by an in-situ or x-situ method. 제1항에 있어서, 상기 SiON 박막 증착시의 조성물질로는 비정질 실리콘, SiO2, Si3N4 로 구성하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the composition of the SiON thin film is formed of amorphous silicon, SiO 2 , or Si 3 N 4 . 제1항에 있어서, 상기 비아홀의 콘택깊이는 5000∼15000Å인 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.The method of claim 1, wherein the via hole has a contact depth of 5000 to 15000 Å. 제1항에 있어서, 상기 하드마스크층과 저유전상수물질층 건식식각시에 감광막패턴을 이용하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.2. The method of claim 1, wherein a photoresist pattern is used for dry etching of the hard mask layer and the low dielectric constant material layer. 제14항에 있어서, 상기 저유전상수물질층에 대한 감광막패턴의 선택비는 0.5∼1.5가 되도록 하는 것을 특징으로하는 반도체소자의 금속배선콘택 형성방법.15. The method of claim 14, wherein the selectivity ratio of the photoresist pattern to the low dielectric constant material layer is 0.5 to 1.5.
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