KR100604540B1 - Method for improving Damascence Process by stopper - Google Patents

Method for improving Damascence Process by stopper Download PDF

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KR100604540B1
KR100604540B1 KR1020040106642A KR20040106642A KR100604540B1 KR 100604540 B1 KR100604540 B1 KR 100604540B1 KR 1020040106642 A KR1020040106642 A KR 1020040106642A KR 20040106642 A KR20040106642 A KR 20040106642A KR 100604540 B1 KR100604540 B1 KR 100604540B1
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teos
primary
stopper
film
etch stop
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KR20060067744A (en
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이대근
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 스토퍼를 이용한 다마신 공정 개선 방법에 관한 것으로, 보다 자세하게는 최상층(Top Layer)에서 기존의 스토퍼(Stopper)로 사용되는 질화막의 면적으로 최소한으로 줄임으로써, 정전용량(Capacitance) 값을 낮추고 질화막의 표면 높낮이(Topology)에 의한 상부 표면 높낮이 변화 부분을 최소화시키기 위한 스토퍼를 사용한 다마신 공정 개선 방법에 관한 것이다.The present invention relates to a method for improving a damascene process using a stopper, and more particularly, by reducing the capacitance to a minimum area of a nitride film used as a conventional stopper at the top layer, thereby reducing the capacitance value. The present invention relates to a method for improving a damascene process using a stopper for minimizing the change of the upper surface height due to the surface topology of the nitride film.

스토퍼, 다마신, 토폴로지, 정전용량Stopper, damascene, topology, capacitance

Description

스토퍼를 사용한 다마신 공정 개선 방법{Method for improving Damascence Process by stopper} Method for improving Damascence Process by stopper             

도 1은 종래기술에 의한 스토퍼를 이용한 다마신 공정을 나타낸 단면도.1 is a cross-sectional view showing a damascene process using a stopper according to the prior art.

도 2는 본 발명에 의한 스토퍼를 이용한 다마신 공정을 나타낸 단면도.2 is a cross-sectional view showing a damascene process using a stopper according to the present invention.

본 발명은 스토퍼를 이용한 다마신(Damascene) 공정 개선 방법에 관한 것으로, 보다 자세하게는 최상층(Top Layer)에서 기존의 스토퍼(Stopper)로 사용되는 질화막(Nitride Film)의 면적으로 최소한으로 줄임으로써, 정전용량(Capacitance) 값을 낮추고, 질화막의 표면 높낮이(Topology)에 의한 상부 표면 높낮이 변화 부분을 최소하는 스토퍼를 이용한 다마신 공정 개선 방법에 관한 것이다.The present invention relates to a method for improving a damascene process using a stopper, and more specifically, by reducing the area of a nitride film used as a conventional stopper at the top layer to a minimum, The present invention relates to a method for improving a damascene process using a stopper for lowering a capacitance value and minimizing an upper surface height change portion due to a surface topology of a nitride film.

도 1은 종래 기술에 의한 스토퍼를 이용한 다마신 공정을 나타낸 단면도이다. 도1에서 보는 바와 같이, 먼저 트렌치(101) 상에 소자 분리막으로 1차 TEOS(Tetra Ethyl Ortho Silicate)(102)가 형성된 반도체 기판 상에 식각 스토퍼로 질화막(103)을 형성한 다음, 1차 감광막(Photo Resistant)(104)을 도포하고 패터닝 한 후 상기 감광막(104)을 식각 마스크로 하여 상기 질화막(103)을 반응성 이온 식각(Reactive Ion Etching, 이하 RIE)으로 상기 1차 TEOS(102)막까지 일정 두께로 건식 식각한다. 이후 감광막을 제거한 후 패턴이 형성된 상태에서 전체적으로 2차 TEOS(105)를 증착하고, 한 차례 더 감광막(106)을 도포하고 패터닝 한 후 상기 패터닝 된 감광막(106)을 식각 마스크로 하여 상기 1차 및 2차 TEOS(102, 105)를 RIE식각하여 듀얼 다마신 패턴(Dual Damascene Pattern)을 형성한다. 1 is a cross-sectional view showing a damascene process using a stopper according to the prior art. As shown in FIG. 1, first, a nitride photo film 103 is formed on the semiconductor substrate on which the first TEOS (Tetra Ethyl Ortho Silicate) 102 is formed on the trench 101 with an etching stopper, and then the primary photoresist film. (Photo Resistant) (104) after applying and patterning the photoresist film 104 as an etch mask to the nitride film 103 to the first TEOS (102) film by reactive ion etching (hereinafter referred to as RIE) Dry etch to a certain thickness. Thereafter, after removing the photoresist film, the second TEOS 105 is entirely deposited in a patterned state, and the second photoresist film 106 is applied and patterned once more, and then the patterned photoresist 106 is used as an etching mask. The secondary TEOS 102 and 105 are RIE-etched to form a dual damascene pattern.

이상의 방법으로 종래의 듀얼 다마신 구조의 금속 배선 라인을 형성하기 위한 식각 공정을 진행하여 왔으나, 이러한 종래의 방법은 질화막을 식각 스토퍼로 사용할 경우 질화막의 면적이 넓어 정전용량 값이 증가하고, 상부에 표면 높낮이 변화가 발생하여 반도체 소자의 성능과 신뢰성(Reliablity)를 저하시킬 뿐만 아니라 후속 공정에도 악영향을 미치는 문제점이 있었다.In the conventional method, an etching process for forming a metal wiring line having a dual damascene structure has been performed. However, when the nitride film is used as an etch stopper, the nitride film has a large area, which increases capacitance, and The change in the surface height occurs, which not only degrades the performance and reliability of the semiconductor device, but also adversely affects subsequent processes.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 질화막의 면적을 최소화하여 반도체 소자의 정전용량 값을 최소한으로 낮출 수 있으며, 질화막의 표면 높낮이 변화를 최소한으로 줄여 사진식각공정(Photo Etching Process)시 최소치수(Critical Dimension)의 변화를 최소한으로 줄이는 스토퍼를 이용한 다마신 공정 개선 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by minimizing the area of the nitride film to minimize the capacitance value of the semiconductor device, and to minimize the change in the surface height of the nitride film to minimize the photolithography process ( An object of the present invention is to provide a method for improving a damascene process using a stopper that minimizes a change in the critical dimension during a photo etching process.

본 발명의 상기 목적은 트렌치가 형성된 반도체 기판 상에 1차 TEOS막을 증착시키는 단계, 상기 1차 TEOS막이 증착된 기판 상에 1차 감광막을 도포하고 패터닝하는 단계, 상기 패터닝된 1차 감광막을 식각 마스크로 하여 상기 1차 TEOS막을 RIE 방법으로 식각하는 단계, 상기 1차 감광막을 제거하고 캐핑층을 형성하는 단계, 상기 캐핑층을 CMP로 연마하는 단계, 상기 연마된 기판 상에 2차 TEOS막을 증착시키는 단계, 상기 2차 TEOS막이 증착된 기판 상에 2차 감광막을 도포하고 패터닝하는 단계, 상기 패터닝된 2차 감광막을 식각 마스크로 하여 상기 2차 TEOS막을 RIE 방법으로 식각하는 단계 및 상기 2차 감광막을 제거하고 상기 캐핑층을 제거하는 단계로 이루어진 스토퍼를 이용한 다마신 공정 개선방법에 의해 달성된다.The object of the present invention is to deposit a primary TEOS film on a trench formed semiconductor substrate, applying and patterning a primary photoresist film on the substrate on which the primary TEOS film is deposited, the patterned primary photoresist etching mask Etching the primary TEOS film by a RIE method, removing the primary photoresist film and forming a capping layer, polishing the capping layer with CMP, and depositing a secondary TEOS film on the polished substrate. The method may further include: coating and patterning a second photoresist film on a substrate on which the second TEOS film is deposited, etching the second TEOS film by an RIE method using the patterned second photoresist film as an etching mask, and the second photoresist film And a damascene process improvement method using a stopper consisting of removing and removing the capping layer.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2는 본 발명에 의한 스토퍼를 이용한 다마신 공정을 나타낸 단면도이다. 도에서 보는 바와 같이, 트렌치(201)가 형성된 반도체 기판 상에 소자 분리막으로 1차 TEOS(202)를 증착시키고, 상기 1차 TEOS막(202)이 증착된 기판 상에 1차 감광막(204)을 도포하고 패터닝한 다음, 상기 1차 감광막을 식각 마스크로 하여 1차 TEOS막을 RIE 방법으로 식각하고, 1차 감광막을 제거한 뒤 캐핑층(203)을 형성한다. 이 때 상기 캐핑층은 이 후 공정에서 형성되는 듀얼 다마신 패턴을 식각할 때 스토퍼로 작용하는데, 상기 캐핑층으로 형성시킨 실리콘 질화막(SiN)을 2000Å 내 지 6000Å의 두께로 증착한다. 2 is a cross-sectional view showing a damascene process using a stopper according to the present invention. As shown in the figure, the primary TEOS 202 is deposited on the semiconductor substrate on which the trench 201 is formed, and the primary photoresist film 204 is deposited on the substrate on which the primary TEOS film 202 is deposited. After coating and patterning, the primary TEOS film is etched by the RIE method using the primary photoresist as an etch mask, and the capping layer 203 is formed after removing the primary photoresist. In this case, the capping layer serves as a stopper when etching the dual damascene pattern formed in a subsequent process, and deposits a silicon nitride film (SiN) formed of the capping layer to a thickness of 2000 kPa to 6000 kPa.

이어서 상기 캐핑층 상부를 물리화학적연마(Chemical Mechanical Polishing)로 연마하고, 2차 TEOS막(205)을 증착하며, 상기 2차 TEOS막 상부에 2차 감광막을 도포하고 패터닝한 다음, 상기 패터닝된 2차 감광막을 식각 마스크로 하여 상기 2차 TEOS막 및 1차 TEOS막을 RIE 방법으로 식각하고, 상기 1차 TEOS막 상부에 남아 있는 상기 캐핑층을 제거하여 듀얼 다마신 패턴을 형성한다. Subsequently, the upper portion of the capping layer is polished by chemical mechanical polishing, a secondary TEOS layer 205 is deposited, a second photosensitive layer is coated and patterned on the secondary TEOS layer, and then the patterned 2 The secondary TEOS layer and the primary TEOS layer are etched using the primary photoresist layer as an etch mask, and the capping layer remaining on the upper TEOS layer is removed to form a dual damascene pattern.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above embodiments and should be made by those skilled in the art to which the present invention pertains without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 스토퍼를 이용한 다마신 공정 개선방법은 질화막의 면적을 최소화하여 반도체 소자의 정전용량 값을 최소한으로 낮출 수 있으며, 질화막의 표면 높낮이 변화를 최소한으로 줄여 사진식각 공정 시 치수 여유치의 한계를 최소한으로 줄이는 효과가 있다.Therefore, the method for improving the damascene process using the stopper of the present invention can minimize the area of the nitride film to minimize the capacitance value of the semiconductor device, and reduce the surface height change of the nitride film to the minimum to reduce the dimensional margin during the photolithography process. This has the effect of reducing the limit to a minimum.

Claims (2)

반도체 기판 상에 1차 TEOS막을 증착하는 단계; Depositing a primary TEOS film on a semiconductor substrate; 상기 1차 TEOS막의 표면을 식각하여 패터닝 하는 단계; Etching and patterning a surface of the primary TEOS film; 패터닝된 상기 1차 TEOS막 상면을 덮는 식각 멈춤막을 형성하는 단계;Forming an etch stop layer covering an upper surface of the patterned primary TEOS layer; 상기 식각 멈춤막을 CMP로 연마하여, 상기 1차 TEOS막 내부에 형성되고 비아홀과 대응하는 부분이 개구된 식각 멈춤 패턴을 형성하는 단계; Polishing the etch stop layer by CMP to form an etch stop pattern formed in the primary TEOS layer and having a portion corresponding to the via hole ; 상기 식각 멈춤 패턴이 덮이도록 상기 기판상에 2차 TEOS막을 증착시키는 단계;Depositing a secondary TEOS film on the substrate such that the etch stop pattern is covered; 상기 2차 TEOS막이 증착된 기판 상에 형성된 감광막 패턴을 식각 마스크로 이용하여 상기 2차 TEOS을 식각하고, 상기 식각 멈춤 패턴을 식각 마스크로 이용하여 상기 1차 TEOS막을 식각하여 패터닝하는 단계; 및Etching the second TEOS using a photoresist pattern formed on the substrate on which the second TEOS film is deposited as an etch mask, and etching and patterning the primary TEOS film using the etch stop pattern as an etch mask; And 상기 1차 TEOS막 상부에 남아 있는 상기 식각 멈춤 패턴을 제거하는 단계로 이루어짐을 특징으로 하는 스토퍼를 이용한 다마신 공정 개선방법. Removing the etch stop pattern remaining on the upper portion of the primary TEOS film . 제 1 항에 있어서, The method of claim 1, 상기 식각 멈춤 패턴은 실리콘 질화막을 2000Å 내지 6000Å의 두께로 형성함을 특징으로 하는 스토퍼를 이용한 다마신 공정 개선방법.The etch stop pattern is a damascene process improvement method using a stopper, characterized in that to form a silicon nitride film with a thickness of 2000 kPa to 6000 kPa.
KR1020040106642A 2004-12-15 2004-12-15 Method for improving Damascence Process by stopper KR100604540B1 (en)

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KR20040069786A (en) * 2003-01-30 2004-08-06 아남반도체 주식회사 Semiconductor metal wiring and its manufacturing method

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Publication number Priority date Publication date Assignee Title
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Title
1020040069786 *
1020040106642 - 629820 *

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