KR100309133B1 - Method for manufacturing metal interconnection of semiconductor device - Google Patents
Method for manufacturing metal interconnection of semiconductor device Download PDFInfo
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- KR100309133B1 KR100309133B1 KR1019950046321A KR19950046321A KR100309133B1 KR 100309133 B1 KR100309133 B1 KR 100309133B1 KR 1019950046321 A KR1019950046321 A KR 1019950046321A KR 19950046321 A KR19950046321 A KR 19950046321A KR 100309133 B1 KR100309133 B1 KR 100309133B1
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- Prior art keywords
- protective film
- metal
- etching
- metal layer
- layer
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 49
- 239000002184 metal Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 claims abstract 5
- 230000001681 protective effect Effects 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 238000000059 patterning Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000005368 silicate glass Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 24
- 238000000206 photolithography Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제 1A 내지 제 1D 도는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method for forming metal wirings in a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1 : 실리콘 기판 2 : 절연층1: silicon substrate 2: insulating layer
3 : 금속층 3A : 금속 배선3: metal layer 3A: metal wiring
4 : 보호막 5 : 감광막4: protective film 5: photosensitive film
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속층의 상부에 보호막을 형성하므로써 사진 공정시 불량의 발생을 방지할 수 있도록 한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices in which a defect can be prevented during a photolithography process by forming a protective film on top of the metal layer.
일반적으로 반도체 소자의 제조 공정에서 금속층은 이중 또는 다중 구조로 형성된다. 그런데 소자의 고집적화에 따라 금속 배선의 폭이 급격히 감소하기 때문에 상기 금속층을 패터닝하는 과정에서 많은 어려움이 따른다. 그러면 종래 반도체 소자의 금속 배선 형성 방법을 설명하면 다음과 같다.In general, in the process of manufacturing a semiconductor device, the metal layer is formed in a double or multiple structure. However, due to the high integration of the device, the width of the metal wires is drastically reduced, which causes a lot of difficulties in the process of patterning the metal layer. A method of forming metal wirings of a conventional semiconductor device will now be described.
종래에는 절연층이 형성된 실리콘 기판상에 알루미늄(Al)과 같은 금속을 증착하여 금속층을 형성하고, 금속 배선용 마스크를 이용한 사진 및 식각 공정으로 상기 금속층을 패터닝하여 금속 배선을 형성한다. 그런데 상기 사진 공정에서 상기 금속층과 감광막의 식각 선택비를 고려하여 상기 감광막의 두께를 약 20000Å 정도로 두껍게 형성하기 때문에 노광 공정시 촛점의 깊이가 부족하여 현상후 상기 감광막의 두께가 얇아지는 현상이 발생되고, 상기 감광막 찌꺼기도 생성된다. 그러므로 반사율이 높은 상기 금속층의 패터닝시 낫치(Notch) 및 넥킹(Necking) 현상이 발생되어 금속 배선의 불량을 야기시키므로서 소자의 소율 및 전기적 특성이 저하된다.Conventionally, a metal layer is formed by depositing a metal such as aluminum (Al) on a silicon substrate on which an insulating layer is formed, and the metal layer is formed by patterning the metal layer by a photo and etching process using a metal wiring mask. However, since the thickness of the photoresist film is formed to be about 20000Å thick in consideration of the etching selectivity of the metal layer and the photoresist film in the photolithography process, the thickness of the photoresist film becomes thin after development due to insufficient depth of focus during the exposure process. The photoresist debris is also produced. Therefore, a notch and necking phenomenon occurs during patterning of the metal layer having high reflectance, resulting in a defect in metal wiring, thereby degrading the small ratio and electrical characteristics of the device.
따라서 본 발명은 금속층상에 보호막을 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can solve the above disadvantages by forming a protective film on the metal layer.
상기한 목적을 달성하기 위한 본 발명은 절연층이 형성된 실리콘 기판상에 금속층, 보호막 및 감광막을 순차적으로 형성하는 제 1 단계와, 상기 제 1 단계로부터 금속 배선용 마스크를 이용하여 상기 감광막을 패터닝한 후 상기 패터닝된 감광막을 마스크로 이용한 식각 공정으로 상기 보호막 및 금속층을 순차적으로 식각하는 제 2 단계와, 상기 제 2 단계로부터 잔류된 상기 감광막을 제거하는 제 3 단계로 이루어지는 것을 특징으로 하며, 또한 상기 제 3 단계로부터 잔류된 상기 보호막을 식각하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a first step of sequentially forming a metal layer, a protective film and a photosensitive film on a silicon substrate with an insulating layer, and after the patterning the photosensitive film using a mask for metal wiring from the first step And a second step of sequentially etching the protective film and the metal layer by an etching process using the patterned photoresist as a mask, and a third step of removing the photoresist remaining from the second step. And etching the protective film remaining from step 3.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1A 내지 제 1D 도는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도로서,1A to 1D are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to the present invention.
제 1A 도는 절연층(2)이 형성된 실리콘 기판(1)상에 알루미늄(Al)과 같은 금속을 4000 내지 6000Å의 두께로 증착하여 금속층(3)을 형성한 후 상기 금속층(3)상에 보호막(4) 및 감광막(5)을 순차적으로 형성한 상태의 단면도로서, 상기 보호막(4)은 BPSG(Boro-Phospho-Silicate-Glass) 또는 PSG(Phospho-Silicate-Glass)를 400 내지 600Å의 두께로 증착하여 형성하며, 상기 감광막(5)은 8000 내지 12000Å의 두께로 도포한다.The metal layer 3 is formed by depositing a metal, such as aluminum (Al), to a thickness of 4000 to 6000 GPa on the silicon substrate 1 on which the insulating layer 2 is formed. 4) and the photoresist film 5 are formed in a cross-sectional view, in which the protective film 4 is formed by depositing Boro-Phospho-Silicate-Glass (BPSG) or Phospho-Silicate-Glass (PSG) at a thickness of 400 to 600 kPa. The photosensitive film 5 is coated with a thickness of 8000 to 12000 kPa.
제 1B 도는 금속 배선용 마스크를 이용하여 상기 감광막(5)을 패터닝한 상태의 단면도이고, 제 1C 도는 상기 패터닝된 감광막(5)을 마스크로 이용한 식각 공정으로 상기 보호막(4) 및 금속층(3)을 순차적으로 식각하여 금속 배선(3A)을 형성한 상태의 단면도로서, 상기 보호막(4) 식각시 사용되는 에천트(Etchant)는 300mT / 1300W / 50CHF3/ 30CF4/ 600Ar이며, 상기 금속층(3) 식각시 사용되는 에천트는 200mT / 800W / 75BCL3/ 30CL2/ 50N2이다.FIG. 1B is a cross-sectional view of the photosensitive film 5 patterned using a metal wiring mask, and FIG. 1C is an etching process using the patterned photosensitive film 5 as a mask. a cross-sectional view of the state of forming a metal wiring (3A) by sequentially etching, the protective film 4 etchant (etchant) to be used for etching is 300mT / 1300W / 50CHF 3 / 30CF 4 / 600Ar, the metal layer 3 The etchant used for etching is 200mT / 800W / 75BCL 3 / 30CL 2 / 50N 2 .
제 1D 도는 산소(O2) 플라즈마(Plasma)를 이용한 건식 식각 방법으로 하여 잔류된 상기 감광막(5)을 제거한 후 상기 보호막(4)을 제거한 상태의 단면도로서, 상기 보호막(4) 식각시 사용되는 에천트는 300mT / 1300W / 50CHF3/ 30CF4/ 600Ar이다. 그러나 이때, 상기 보호막(4)을 제거하지 않은 상태에서 후속 공정을 진행하여도 된다. 이와 같은 방법을 이용하면 상기 금속층(3)상에 보호막(4)이 형성되기 때문에 상기 감광막(5)을 패터닝하는 과정에서 상기 금속층(3)의 높은 반사율로 인해 발생되는 낫칭 및 넥킹 현상이 방지되고, 상기 감광막(5)의 두께를 얇게 형성하여도 되기 때문에 촛점 깊이를 깊게 조절할 수 있다.1D is a cross-sectional view of the protective film 4 removed after the photoresist film 5 is removed by a dry etching method using an oxygen (O 2 ) plasma, and is used when etching the protective film 4. The etchant is 300mT / 1300W / 50CHF 3 / 30CF 4 / 600Ar. At this time, however, the subsequent process may be performed without removing the protective film 4. By using this method, since the protective film 4 is formed on the metal layer 3, the curing and necking phenomenon caused by the high reflectance of the metal layer 3 is prevented in the process of patterning the photosensitive film 5. Since the thickness of the photosensitive film 5 may be formed thin, the depth of focus can be deeply adjusted.
상술한 바와 같이 본 발명에 의하면 금속층을 형성한 후 상기 금속층 상부에 보호막을 형성하므로써 감광막을 얇게 형성하여 사진 공정시 촛점 깊이를 깊게 조절할 수 있으며, 상기 금속층의 높은 반사율로 인해 발생되는 낫칭 및 넥킹 현상을 방지하여 소자의 전기적 특성 및 수율을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, by forming a protective layer on the metal layer after forming the metal layer, the photoresist layer may be formed to be thin to deeply control the depth of focus during the photolithography process, and may cause hardening and necking due to high reflectance of the metal layer. There is an excellent effect to improve the electrical properties and yield of the device by preventing the.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046321A KR100309133B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing metal interconnection of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950046321A KR100309133B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing metal interconnection of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970052923A KR970052923A (en) | 1997-07-29 |
| KR100309133B1 true KR100309133B1 (en) | 2001-12-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019950046321A KR100309133B1 (en) | 1995-12-04 | 1995-12-04 | Method for manufacturing metal interconnection of semiconductor device |
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| KR100831572B1 (en) * | 2005-12-29 | 2008-05-21 | 동부일렉트로닉스 주식회사 | Method of forming metal line for semiconductor device |
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1995
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| KR970052923A (en) | 1997-07-29 |
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