KR100827488B1 - Method for forming a metal line pattern of the semiconductor device - Google Patents

Method for forming a metal line pattern of the semiconductor device Download PDF

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KR100827488B1
KR100827488B1 KR1020060080529A KR20060080529A KR100827488B1 KR 100827488 B1 KR100827488 B1 KR 100827488B1 KR 1020060080529 A KR1020060080529 A KR 1020060080529A KR 20060080529 A KR20060080529 A KR 20060080529A KR 100827488 B1 KR100827488 B1 KR 100827488B1
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film
forming
pattern
photosensitive film
chemically amplified
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KR20080018433A (en
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문주형
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

본 발명은 반도체 소자의 금속 배선 패턴 형성 방법에 관한 것이다. The present invention relates to a method for forming a metal wiring pattern of a semiconductor device.

본 발명은, 반도체 기판(2)상에 하부절연막(4), 금속막(6), 상부질화막(8)을 순차적으로 적층 형성한 다음 상기 상부질화막(8)상에 화학증폭형 감광막(10)을 형성하고, 상기 화학증폭형 감광막(10)을 원자외선(DUV) 광원을 이용한 노광 및 현상하여 감광막 패턴(10')을 형성한 다음 상기 감광막 패턴(10')을 마스크로 하여 상기 금속막(6)을 식각하여 금속 배선 패턴(6')을 형성한 후 상기 감광막 패턴(10')을 제거하게 되는 반도체 소자의 금속 배선 패턴 형성 방법에 있어서, 상기 화학증폭형 감광막(10)과 상기 상부질화막(8)간의 화학 반응에 의해 상기 감광막 패턴(10') 형성시 풋팅(footing)현상이 발생되는 것을 방지하기 위해 상기 화학증폭형 감광막(10)의 형성전에 상기 상부질화막(8)상에 반응차단막을 미세 두께로 형성하게 되는 단계를 포함하는 것을 특징으로 한다. According to the present invention, a lower insulating film 4, a metal film 6, and an upper nitride film 8 are sequentially stacked on the semiconductor substrate 2, and then a chemically amplified photosensitive film 10 is formed on the upper nitride film 8. To form the photosensitive film pattern 10 'by exposing and developing the chemically amplified photosensitive film 10 using an ultraviolet (DUV) light source, and then using the photosensitive film pattern 10' as a mask. In the method of forming a metal wiring pattern of the semiconductor device to form a metal wiring pattern (6 ') by etching 6) to remove the photosensitive film pattern 10', the chemically amplified photosensitive film 10 and the upper nitride film A reaction blocking film on the upper nitride film 8 before the chemically amplified photosensitive film 10 is formed to prevent footing from being formed when the photosensitive film pattern 10 'is formed by the chemical reaction between the layers (8). Characterized in that it comprises the step of forming a fine thickness .

따라서, 화학증폭형 감광막이 하부의 질화막과 직접 접촉함에 따라 화학 반응하여 결과적으로 풋팅(footing)현상을 야기하는 것을 근본적으로 방지할 수 있게 되므로, 금속 배선 패턴을 정확하게 형성할 수 있게 되어, 생산되는 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있는 효과가 있게 된다.Therefore, it is possible to fundamentally prevent the chemically amplified photoresist from directly reacting with the underlying nitride film and thereby causing footing, thereby accurately forming a metal wiring pattern, thereby producing There is an effect that can improve the yield and reliability of the semiconductor device.

금속, 배선, 알루미늄, 질화막, 화학증폭형, 감광막, DUV, 원자외선, 노광, 현상, 식각, 풋팅, 반도체, 소자  Metal, wiring, aluminum, nitride, chemically amplified, photoresist, DUV, far ultraviolet, exposure, development, etching, putting, semiconductor, device

Description

반도체 소자의 금속 배선 패턴 형성 방법{METHOD FOR FORMING A METAL LINE PATTERN OF THE SEMICONDUCTOR DEVICE}METHOD FOR FORMING A METAL LINE PATTERN OF THE SEMICONDUCTOR DEVICE}

도 1은 종래의 반도체 소자의 금속 배선 패턴 형성 방법을 보여주는 공정 단면도, 1 is a cross-sectional view illustrating a method of forming a metal wiring pattern of a conventional semiconductor device;

도 2는 종래의 금속 배선 패턴 형성 방법에 있어서 화학증폭형 감광막의 하단부측에서 풋팅(footing)현상이 발생되는 것을 설명하는 설명도, 2 is an explanatory diagram for explaining that footing phenomenon occurs on the lower end side of the chemically amplified photosensitive film in the conventional metal wiring pattern forming method;

도 3은 본 발명에 따른 반도체 소자의 금속 배선 패턴 형성 방법을 설명하는 설명도이다. 3 is an explanatory diagram for explaining a method for forming a metal wiring pattern of a semiconductor device according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

2 : 반도체 기판 4 : 하부절연막2: semiconductor substrate 4: lower insulating film

6 : 금속막 6' : 금속 배선 패턴6: metal film 6 ': metal wiring pattern

8 : 상부질화막 9 : 산화막(반응차단막)8: upper nitride film 9: oxide film (reaction blocking film)

10 : 화학증폭형 감광막 10' : 감광막 패턴10: chemically amplified photosensitive film 10 ': photosensitive film pattern

본 발명은 반도체 소자의 금속 배선 패턴 형성 방법에 관한 것으로서, 더욱 상세하게는 금속 배선 패턴을 포토 리소그래피(photo-lithography) 공정을 통해 형성시 사용되는 화학증폭형 감광막에 의한 풋팅(footing)현상을 근본적으로 방지하여 금속 배선 패턴을 보다 정확하게 형성할 수 있게 되는 반도체 소자의 금속 배선 패턴 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring pattern of a semiconductor device, and more particularly, to the footing phenomenon caused by a chemically amplified photosensitive film used when a metal wiring pattern is formed through a photo-lithography process. The present invention relates to a method for forming a metal wiring pattern of a semiconductor device, which can be prevented to form a metal wiring pattern more accurately.

일반적으로, 반도체 소자는 반도체 기판상에 트랜지스터와 같은 개별 소자들을 소자 분리하여 형성한 다음 절연막을 증착하고, 패드 연결 또는 분리된 개별 소자들을 전기적으로 연결하기 위한 콘택홀을 형성한 후, 알루미늄과 같은 금속막을 증착하고 패터닝(patterning)하여 금속 배선 패턴을 형성한 다음, 패시베이션(passivation)막을 증착하는 것에 의해 제조되게 된다. In general, a semiconductor device is formed by separating individual devices such as transistors on a semiconductor substrate, depositing an insulating film, and forming contact holes for electrically connecting pads or separated individual devices, and then, such as aluminum. It is made by depositing and patterning a metal film to form a metal wiring pattern, and then depositing a passivation film.

도 1은 종래의 금속 배선 패턴 형성 방법을 보여주는 공정 단면도들이다. 1 is a cross-sectional view illustrating a conventional method for forming a metal wiring pattern.

금속 배선 패턴 형성 방법은, 반도체 기판(2)상에 이후 형성될 금속막(6)의 접착성 향상을 위해 하부절연막(4)을 증착하여 형성하는 단계와, 이 하부절연막(4)상의 전면에 금속 배선을 형성하기 위한 알루미늄(Al) 또는 알루미늄 합금으로 된 금속막(6)을 증착하여 형성하는 단계와, 이 금속막(6)상의 전면에 TiN 등으로 상부질화막(8)을 증착하여 형성하는 단계(도 1의 (a) 상태)와, 이 상부질화막(8)상에 감광액을 도포하여 감광막(10)을 형성하는 단계(도 1의 (b) 상태)와, 형성된 감광막(10)을 노광 및 현상하여 감광막 패턴(10')을 형성하는 단계(도 1의 (c) 상태)와, 감광막 패턴(10')을 통해 노출되는 상부질화막(8), 금속막(6) 및 하부절연막(4)을 차례로 식각하여 금속 배선 패턴(6')을 형성하는 단계(도 1의 (d) 상태)와, 감광막 패턴(10')을 애싱(ashing)하여 제거하는 단계(도 1의 (e) 상태)를 포함 하게 된다. The method for forming a metal wiring pattern is formed by depositing a lower insulating film 4 on the semiconductor substrate 2 to improve the adhesion of the metal film 6 to be formed later, and on the entire surface of the lower insulating film 4. Depositing and forming a metal film 6 made of aluminum (Al) or an aluminum alloy for forming a metal wiring; and depositing and forming an upper nitride film 8 by TiN or the like on the entire surface of the metal film 6. Step (a state of FIG. 1A), a step of forming a photosensitive film 10 by applying a photosensitive liquid on the upper nitride film 8 (state (b) of FIG. 1), and exposing the formed photosensitive film 10 And developing to form the photosensitive film pattern 10 '(state (c) of FIG. 1), and the upper nitride film 8, the metal film 6, and the lower insulating film 4 exposed through the photosensitive film pattern 10'. ) Are sequentially etched to form the metallization pattern 6 '(state (d) of FIG. 1), and ashing and removing the photosensitive film pattern 10' ( It will contain one of (e) state).

즉, 그 과정중에는 금속막(6)상에 먼저 감광막 패턴(10')을 형성한 다음, 해당 감광막 패턴(10')을 식각 마스크로 이용하여 금속막(6)의 노출된 부분을 식각하여 제거하는 과정이 포함되어 있다. That is, during the process, the photoresist pattern 10 'is first formed on the metal film 6, and then the exposed portion of the metal film 6 is etched and removed using the photoresist pattern 10' as an etching mask. The process of doing so is included.

이때, 최근에는 반도체 소자가 고집적화됨에 따라 형성되는 금속 배선 패턴(6')의 선폭도 수㎛로 미세화되었고, 따라서 노광시의 해상도를 높여 매우 미세한 금속 배선 패턴(6')의 임계치수(CD)를 원활히 구현할 수 있도록 노광시의 노광원으로는 300㎚ 이하 단파장의 원자외선(Deep UV ; DUV)를 이용함과 더불어, 감광액으로는 해당 노광원에 대해 우수한 감도를 갖는 화학증폭형 감광액(Photo-Resist ; PR)을 이용하게 되는 원자외 노광법을 주로 이용하고 있다. At this time, in recent years, the line width of the metal wiring pattern 6 'formed as the semiconductor device has been highly integrated has also been reduced to several micrometers, and thus the critical dimension (CD) of the very fine metal wiring pattern 6' is increased by increasing the resolution at the time of exposure. In order to realize smoothly, the exposure source at the time of exposure is used as deep UV (DUV) of short wavelength below 300 nm, and as the photoresist, a chemically amplified photoresist having excellent sensitivity to the exposure source (Photo-Resist) The extra-exposure exposure method using PR) is mainly used.

여기서, 화학증폭형 감광액내에는 광발산제(photo acid generator)가 주요 성분으로 함유되어 있으며, 이 광발산제는 노광시 산(H+)을 생성하게 된다. Here, the photo-acid generator is contained as a main component in the chemically amplified photosensitive liquid, and the photo-acid generator generates acid (H + ) upon exposure.

그러나, 종래에 있어서는 도 2에 나타낸 바와 같이, 이 광발산제의 산(H+)이 하부측 상부질화막(8)의 질화물과 화학적 반응을 일으켜, 상부질화막(8)과 접촉되는 부분의 감광막(10')내의 산(H+)이 소모되어 제거되게 됨으로써, 노광후 현상시 산(H+)이 제거된 부분의 감광막(10')은 깨끗하게 제거되지 못하고 일부 잔류하게 되는 풋팅(footing)형상이 발생되게 되며, 이와 같은 풋팅현상이 발생되게 되면, 이후 금속 배선 패턴(6')을 정확하게 식각하여 형성할 수 없게 되므로, 생산되는 반 도체 소자의 수율 및 신뢰성을 대폭 저하시키게 되는 문제점이 있었다. However, conventionally, as shown in FIG. 2, the acid (H + ) of the photo-acid emitter chemically reacts with the nitride of the lower upper nitride film 8, whereby the photosensitive film of the portion in contact with the upper nitride film 8 ( Since the acid (H + ) in the 10 ') is consumed and removed, the photosensitive film 10' of the portion where the acid (H + ) is removed during post-exposure development is not removed cleanly, and a footing shape is left. If such a putting phenomenon occurs, since the metal wiring pattern 6 'cannot be accurately etched and formed, there is a problem in that the yield and reliability of the semiconductor device produced are greatly reduced.

물론, 예전에는 노광시 금속막(6)에 의한 원자외선의 반사도를 최소화시켜 보다 정확하게 감광막 패턴(10')을 형성하기 위하여 상부질화막(8)상에 별도의 SiON막, TiON막과 같은 비반사막(Anti Reflectance Coating ; ARC)을 증착하여 형성하기도 하였는데, 그에 따라 해당 비반사막의 폴리머층이 화학증폭형 감광막(10)과 상부질화막(8)간의 직접적인 화학적 반응을 차단하여 전술한 바와 같은 풋팅현상이 방지될 수 있었으나, 비반사막을 이용하게 되면 이후 식각에 따라 폴리머 부산물이 다량 발생되어 치명적인 결함을 야기하게 되므로, 현재에는 거의 비반사막을 별도로 형성하지 않고 있다. Of course, in the past, non-reflective films such as a separate SiON film and a TiON film on the upper nitride film 8 in order to minimize the reflectance of the far ultraviolet rays by the metal film 6 during exposure to more accurately form the photosensitive film pattern 10 '. (Anti Reflectance Coating (ARC)) was also formed by depositing, so that the polymer layer of the anti-reflective film blocks the direct chemical reaction between the chemically amplified photosensitive film 10 and the upper nitride film (8), the putting phenomenon as described above Although it can be prevented, since the non-reflective film is used, a large amount of polymer by-products are generated by etching, which causes fatal defects.

본 발명은 상기와 같은 제반 문제점을 해결하기 위하여 창안된 것으로서, 비반사막을 형성하지 않는 경우에 있어 화학증폭형 감광막과 상부질화막간의 화학적 반응에 의한 풋팅현상의 발생을 근본적으로 방지할 수 있어 신뢰성 높게 금속 배선 패턴을 형성할 수 있게 되는 반도체 소자의 금속 배선 패턴 형성 방법을 제공하는데 그 목적이 있다. The present invention was devised to solve the above problems, and in the case of not forming the anti-reflective film, it is possible to fundamentally prevent the occurrence of the footing phenomenon due to the chemical reaction between the chemically amplified photoresist film and the upper nitride film, thereby providing high reliability. It is an object of the present invention to provide a method for forming a metal wiring pattern of a semiconductor device capable of forming a metal wiring pattern.

본 발명의 상기 목적과 여러가지 장점은 이 기술분야에 숙련된 사람들에 의해 첨부된 도면을 참조하여 아래에 기술되는 발명의 바람직한 실시예로부터 더욱 명확하게 될 것이다.The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

상술한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 패턴 형성 방법은, 반도체 기판(2)상에 하부절연막(4), 금속막(6), 상부질화막(8)을 순차적으로 적층 형성한 다음 상기 상부질화막(8)상에 화학증폭형 감광막(10)을 형성하고, 상기 화학증폭형 감광막(10)을 원자외선(DUV) 광원을 이용한 노광 및 현상하여 감광막 패턴(10')을 형성한 다음 상기 감광막 패턴(10')을 마스크로 하여 상기 금속막(6)을 식각하여 금속 배선 패턴(6')을 형성한 후 상기 감광막 패턴(10')을 제거하게 되는 반도체 소자의 금속 배선 패턴 형성 방법에 있어서, 상기 화학증폭형 감광막(10)과 상기 상부질화막(8)간의 화학 반응에 의해 상기 감광막 패턴(10') 형성시 풋팅(footing)현상이 발생되는 것을 방지하기 위해 상기 화학증폭형 감광막(10)의 형성전에 상기 상부질화막(8)상에 반응차단막을 미세 두께로 형성하게 되는 단계를 포함하는 것을 특징으로 한다. In the method for forming a metal wiring pattern of the semiconductor device of the present invention for achieving the above object, the lower insulating film 4, the metal film 6, and the upper nitride film 8 are sequentially stacked on the semiconductor substrate 2 Next, a chemically amplified photosensitive film 10 is formed on the upper nitride film 8, and the chemically amplified photosensitive film 10 is exposed and developed by using an ultraviolet light (DUV) light source to form a photosensitive film pattern 10 ′. Next, the metal film 6 is etched using the photoresist pattern 10 ′ as a mask to form a metal wiring pattern 6 ′, and then the metal wiring pattern formation of the semiconductor device to remove the photoresist pattern 10 ′. In the method, the chemically amplified photosensitive film in order to prevent the footing phenomenon occurs when the photosensitive film pattern (10 ') is formed by a chemical reaction between the chemically amplified photosensitive film 10 and the upper nitride film (8) Half on the upper nitride film 8 before the formation of the Characterized in that it comprises the step that forms a barrier film to the fine thickness.

이하, 첨부된 도면을 참조로 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 반도체 소자의 금속 배선 패턴 형성 방법을 설명하는 설명도이다. 3 is an explanatory diagram for explaining a method for forming a metal wiring pattern of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 금속 배선 패턴 형성 방법은, 반도체 기판(2)상에 이후 형성될 금속막(6)의 접착성 향상을 위해 하부절연막(4)을 증착하여 형성하는 단계와, 이 하부절연막(4)상의 전면에 금속 배선을 형성하기 위한 알루미늄(Al) 또는 알루미늄 합금으로 된 금속막(6)을 증착하여 형성하는 단계와, 이 금속막(6)상의 전면에 TiN 등으로 상부질화막(8)을 증착하여 형성하는 단계와, 이 상부질화막(8)상의 전면에 미세 두께로 산화막(9)을 형성하는 단계와, 이 산화막(9) 상에 화학증폭형 감광액을 도포하여 감광막(10)을 형성하는 단계와, 형성된 감광막(10)을 DUV 광원을 이용한 노광 및 현상하여 감광막 패턴(10')을 형성하는 단계와, 감광막 패턴(10')을 통해 노출되는 산화막(9), 상부질화막(8), 금속막(6) 및 하부절연막(4)을 차례로 식각하여 금속 배선 패턴(6')을 형성는 단계와, 감광막 패턴(10')을 애싱하여 제거하는 단계를 포함하게 된다. The method for forming a metal wiring pattern of a semiconductor device according to the present invention comprises the steps of depositing and forming a lower insulating film (4) on the semiconductor substrate (2) to improve the adhesion of the metal film (6) to be formed later, Depositing and forming a metal film 6 made of aluminum (Al) or an aluminum alloy on the entire surface of the insulating film 4, and forming an upper nitride film (TiN or the like) on the entire surface of the metal film 6; 8) depositing and forming an oxide film 9 on the entire surface of the upper nitride film 8 with a fine thickness, and applying a chemically amplified photosensitive liquid onto the oxide film 9 to form a photosensitive film 10. Forming a photoresist film; and exposing and developing the formed photoresist film 10 using a DUV light source to form a photoresist pattern 10 ', and an oxide film 9 and an upper nitride film (exposed through the photoresist pattern 10'). 8), the metal film 6 and the lower insulating film 4 are sequentially etched to remove the metal wiring pattern. (6 ') and the hyeongseongneun step, the photoresist pattern (10' is removed by ashing, comprising: a).

즉, 상부질화막(8)상에 추가적으로 미세 두께의 산화막(9)을 형성하는 단계를 더 포함하게 되며, 이와 같이 산화막(9)을 추가 형성하는 이유는 해당 산화막(9)이 상부질화막(8)과 화학증폭형 감광막(10) 사이에 개재되어 그들간의 직접적인 접촉에 따른 화학적 반응을 차단하여 화학증폭형 감광막(10)내의 광발산제의 산(H+)이 화학 반응에 따라 소모되어 이후 노광 다음에 실시되는 현상시 산(H+)이 소모된 부분의 감광막(10)이 제거되지 않고 잔류하게 되는 풋팅(footing)현상이 발생되는 것을 방지하기 위함이다. That is, the method may further include forming an oxide film 9 having a fine thickness on the upper nitride film 8. The reason for the additional formation of the oxide film 9 is that the oxide film 9 is formed on the upper nitride film 8. Interposed between the chemically amplified photosensitive film 10 and blocking a chemical reaction due to direct contact therebetween, so that the acid (H + ) of the photo-acid emitter in the chemically amplified photosensitive film 10 is consumed in accordance with the chemical reaction. This is to prevent the occurrence of a footing phenomenon in which the photoresist film 10 of the portion where the acid (H + ) is consumed is not removed during the development.

환언하면, 추가 형성되는 산화막(9)의 존재로 인해 화학증폭형 감광막(10)은 상부질화막(8)측과 전혀 화학 반응을 하지 않게 되므로, 해당 화학증폭형 감광막(10)내의 광발산제의 산(H+)이 그대로 양호하게 보존될 수 있게 됨으로써, 이후 노광후 현상시에 원하는 모든 부분에서 감광막(10)이 정확하게 제거되어 이후 그 정확하게 형성된 감광막 패턴(10')을 이용하여 금속 배선 패턴(6')도 정확하게 형성할 수 있게 되는 것이다. In other words, since the chemically amplified photosensitive film 10 does not undergo any chemical reaction with the upper nitride film 8 side due to the presence of the additionally formed oxide film 9, the photo-acid generator in the chemically amplified photosensitive film 10 Since the acid (H + ) can be well preserved as it is, the photoresist film 10 is accurately removed at all desired portions during the post-exposure development, and then the metal wiring pattern (10 ') is formed using the accurately formed photoresist film pattern 10'. 6 ') can also be formed accurately.

여기서, 바람직한 일 예로서, 반응차단막으로서, 반도체 소자 제조에 있어 버퍼(buffer)층 등으로 다용되고 있고 상대적으로 용이하게 형성될 수 있는 산화막(9)을 대표적으로 이용하는 것으로 하였으나, 화학증폭형 감광막(10)에 대한 화학적 반응을 제공하지 않으면서 금속 배선 패턴(6') 형성 공정의 원활한 진행을 방해하지 않을 수 있는 것이라면 다른 재질의 박막으로 형성될 수도 있음은 물론이다. Here, as a preferable example, as the reaction blocking film, an oxide film 9, which is widely used as a buffer layer and the like in the manufacture of semiconductor devices, may be used as a representative example, but a chemically amplified photosensitive film ( 10 may be formed of a thin film of another material as long as it does not provide a chemical reaction to 10) and may not prevent the smooth progress of the metallization pattern 6 'forming process.

그리고, 전술한 바와 같이 산화막(9)으로 형성되는 경우에 있어 해당 산화막(9)은 TEOS(Tetra Ethyl Ortho Silicate)와 같은 Si 계열의 산화물로 바람직하게 형성될 수 있다. In the case where the oxide film 9 is formed as described above, the oxide film 9 may be preferably formed of an Si-based oxide such as TEOS (Tetra Ethyl Ortho Silicate).

또한, 해당 산화막(9)은 증착방식을 통해 형성될 수 있으며, 100A 이하의 미세 두께를 갖도록 형성될 수 있다. In addition, the oxide film 9 may be formed through a deposition method, and may be formed to have a fine thickness of 100 A or less.

이로써, 단순한 공정 추가를 통해 산화막(9)을 부가적으로 형성하여, 풋팅현상의 발생을 근본적으로 방지할 수 있게 되므로, 금속 배선 패턴(6')을 매우 정확하게 형성하여, 생산되는 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있게 된다. As a result, the oxide film 9 can be additionally formed through a simple process, and the occurrence of the putting phenomenon can be fundamentally prevented. Therefore, the metal wiring pattern 6 'can be formed very accurately, resulting in the yield of the semiconductor device produced. And reliability can be improved.

또한, 이상과 같이 풋팅현상의 방지를 위해 형성되는 산화막(9)은 또한 습식식각(wet etch)이나 O2 플라즈마(plasma)를 이용한 건식식각(dry etch) 등을 통해 재작업(rework)하는 경우에 있어서도 금속막(6)을 덮어서 보호하는 역할도 부가적으로 제공할 수 있게 된다. In addition, the oxide film 9 formed to prevent the putting phenomenon as described above may also be reworked by wet etching or dry etching using O 2 plasma. In addition, the role of covering and protecting the metal film 6 can be additionally provided.

이상, 상기 내용은 본 발명의 바람직한 일 실시예를 단지 예시한 것으로 본 발명의 당업자는 본 발명의 요지를 변경시킴이 없이 본 발명에 대한 수정과 변경을 가할 수 있음을 인지해야 한다.In the foregoing description, it should be understood that those skilled in the art can make modifications and changes to the present invention without changing the gist of the present invention as merely illustrative of a preferred embodiment of the present invention.

본 발명에 따르면, 화학증폭형 감광막이 하부의 질화막과 직접 접촉함에 따라 화학 반응하여 결과적으로 풋팅(footing)현상을 야기하는 것을 근본적으로 방지할 수 있게 되므로, 금속 배선 패턴을 정확하게 형성할 수 있게 되어, 생산되는 반도체 소자의 수율 및 신뢰성을 향상시킬 수 있는 효과가 달성될 수 있다.According to the present invention, it is possible to fundamentally prevent the chemically amplified photosensitive film from directly reacting with the underlying nitride film and thereby causing footing, thereby accurately forming a metal wiring pattern. In addition, the effect of improving the yield and reliability of the semiconductor device to be produced can be achieved.

Claims (5)

반도체 기판(2)상에 하부절연막(4), 금속막(6), 상부질화막(8)을 순차적으로 적층 형성한 다음 상기 상부질화막(8)상에 화학증폭형 감광막(10)을 형성하고, 상기 화학증폭형 감광막(10)을 원자외선(DUV) 광원을 이용한 노광 및 현상하여 감광막 패턴(10')을 형성한 다음 상기 감광막 패턴(10')을 마스크로 하여 상기 금속막(6)을 식각하여 금속 배선 패턴(6')을 형성한 후 상기 감광막 패턴(10')을 제거하게 되는 반도체 소자의 금속 배선 패턴 형성 방법에 있어서, A lower insulating film 4, a metal film 6, and an upper nitride film 8 are sequentially stacked on the semiconductor substrate 2, and then a chemically amplified photosensitive film 10 is formed on the upper nitride film 8. The chemically amplified photosensitive film 10 is exposed and developed using a far ultraviolet (DUV) light source to form a photosensitive film pattern 10 ', and then the metal film 6 is etched using the photosensitive film pattern 10' as a mask. In the method for forming a metal wiring pattern of a semiconductor device to form a metal wiring pattern 6 'and then remove the photosensitive film pattern 10', 상기 화학증폭형 감광막(10)과 상기 상부질화막(8)간의 화학 반응에 의해 상기 감광막 패턴(10') 형성시 풋팅(footing)현상이 발생되는 것을 방지하기 위해 상기 화학증폭형 감광막(10)의 형성전에 상기 상부질화막(8)상에 반응차단막으로서 산화막(9)을 100Å 이하의 미세 두께로 형성하게 되는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 패턴 형성 방법.In order to prevent footing from occurring when the photosensitive film pattern 10 'is formed by a chemical reaction between the chemically amplified photosensitive film 10 and the upper nitride film 8, And forming an oxide film (9) on the upper nitride film (8) as a reaction blocking film to a fine thickness of 100 kPa or less before formation. 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 산화막(9)은, The oxide film 9 is Si 계열의 산화물로 이루어지는 것을 특징으로 하는 반도체 소자의 금속 배선 패턴 형성 방법.A method of forming a metal wiring pattern of a semiconductor device, characterized by comprising an oxide of Si series. 제 1 항에 있어서, The method of claim 1, 상기 산화막(9)은, The oxide film 9 is 증착방식을 통해 형성되게 되는 것을 특징으로 하는 반도체 소자의 금속 배선 패턴 형성 방법.Method for forming a metal wiring pattern of a semiconductor device, characterized in that formed by the deposition method. 삭제delete
KR1020060080529A 2006-08-24 2006-08-24 Method for forming a metal line pattern of the semiconductor device KR100827488B1 (en)

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US6093973A (en) * 1998-09-30 2000-07-25 Advanced Micro Devices, Inc. Hard mask for metal patterning
KR20000061743A (en) * 1999-03-30 2000-10-25 김영환 Method for fabricating metal line of semiconductor device

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Publication number Priority date Publication date Assignee Title
US6093973A (en) * 1998-09-30 2000-07-25 Advanced Micro Devices, Inc. Hard mask for metal patterning
KR20000061743A (en) * 1999-03-30 2000-10-25 김영환 Method for fabricating metal line of semiconductor device

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