KR100232185B1 - Method for etching low layer antireflection coating film - Google Patents
Method for etching low layer antireflection coating film Download PDFInfo
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- KR100232185B1 KR100232185B1 KR1019960066698A KR19960066698A KR100232185B1 KR 100232185 B1 KR100232185 B1 KR 100232185B1 KR 1019960066698 A KR1019960066698 A KR 1019960066698A KR 19960066698 A KR19960066698 A KR 19960066698A KR 100232185 B1 KR100232185 B1 KR 100232185B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 하부 반사방지막(Bottom Antireflective Coating : BARC) 식각방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a bottom antireflective coating (BARC).
이를위한 본 발명의 하부 반사방지막 식각방법은 기판에 식각층, BARC, 포토레지스트를 차례로 형성하는 공정과, 상기 포토레지스를 노광 및 현상하여 포토레지스트를 패터닝하는 공정과, 상기 포토레지스트 표면을 실란과 반응 시키는 공정과, 상기 실란과 반응한 포토레지스트를 마스크로 이용하여 상기 BARC, 식각층을 선택적으로 식각하는 공정과, 상기 포토레지스트와 BARC을 제거하는 공정을 포함하여 이루어짐을 특징으로 한다.The lower anti-reflective coating method of the present invention for this purpose is to form an etching layer, a BARC, a photoresist on a substrate in sequence, to expose and develop the photoresist to pattern the photoresist, and to the surface of the photoresist And a step of selectively etching the BARC and the etching layer using the photoresist reacted with the silane as a mask, and removing the photoresist and BARC.
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 하부 반사방지막(Bottom Antireflective Coating : BARC) 식각방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a bottom antireflective coating (BARC).
최근에 소자의 집적도가 증가해짐에 따라 CD(Critical Demension)도 비례하여 작아지는 추세에 있다.Recently, as the degree of integration of devices increases, the critical dimension (CD) also decreases in proportion.
종래 1M급에서는 0.81㎛, 64M급에서는 0.351㎛, 256M급에서는 0.251㎛ 그리고 1G급에서는 0.181㎛로 작아지고 있다.In the conventional 1M class, the thickness is reduced to 0.81 μm, the 64M class is 0.351 μm, the 256M class is 0.251 μm and the 1G class is 0.181 μm.
따라서 패터닝을 위한 노광방법도 종래 i- 라인에서 DUV(Deep Ultraviolet)노광방법으로 전환되고 있다.Therefore, the exposure method for patterning has also been shifted from the i-line to the deep ultraviolet (DUV) exposure method.
추후 1G급 이상에서는 X-ray 노광방법이 채택될 것으로 예상된다.In the future, the X-ray exposure method is expected to be adopted in the 1G class and above.
일반적으로 BARC는 유기성분과 무기성분으로 구분되며 유기성분의 BARC는 바인더 폴리머(Binder Polymer), 다이(Dye), 첨가제등으로 구성되며, 포토레지스트와 간층 C(Carbon), H(Hydrogen), O(Oxygen) 등의 성분을 가지며 점도가 높은 특성이 있다.Generally, BARC is divided into organic and inorganic components, and BARC of organic components is composed of binder polymer, die, and additives. Oxygen) and has a high viscosity.
그리고 BARC에 따라 S(Sulfur)가 포함되어 있기도 한다.And depending on BARC, S (Sulfur) may be included.
또한, 무기성분의 BARC는 SiO2계열 또는 카본(Carbon : C)계열의 주성분이다.In addition, BARC of the inorganic component is the main component of the SiO 2 series or carbon (Carbon: C) series.
이하, 종래의 하부 반사방지막 식각방법에 대하여 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a conventional lower anti-reflection film etching method will be described with reference to the accompanying drawings.
제1(a)도 내지 제1(c)도는 종래의 하부 반사방지막 식각방법을 나타낸 공정 단면도이다.1 (a) to 1 (c) are cross-sectional views illustrating a conventional lower anti-reflection film etching method.
먼저, 제1(a)도에 도시한 바와같이 반도체 기판(1)상에 선택적으로 식각하고자 하는 식각층(2)을 형성하고, 상기 식각층(2)상에 BARC(3)을 증착한 후, 베이킹공정한다.First, as shown in FIG. 1 (a), an etching layer 2 to be selectively etched is formed on the semiconductor substrate 1, and then a BARC 3 is deposited on the etching layer 2. , Baking process.
그리고 특히 BARC(3)상에 포토레지스트(4)를 도포하고 소프트 베이킹 공정을 실시한 후, 노광 및 현상공정으로 포토레지스트(4)를 패터닝한다.In particular, after the photoresist 4 is applied on the BARC 3 and the soft baking process is performed, the photoresist 4 is patterned by an exposure and development process.
이어, 제1(b)도에 도시한 바와같이 패터닝된 포토레지스트(4)를 하드 베이킹 공정을 실시한 후, 상기 패너닝된 포토레지스트(4)를 마스크로 하여 BARC(3)을 식각한다.Subsequently, as shown in FIG. 1 (b), after the hard baking process is performed on the patterned photoresist 4, the BARC 3 is etched using the panned photoresist 4 as a mask.
여기서, 포토레지스트(4)와 BARC(3)의 에칭 선택성은 1:1~1:1.5 정도 밖에 되지 않는다.Here, the etching selectivity of the photoresist 4 and BARC 3 is only about 1: 1 to 1: 1.5.
이어서, 제1(c)도에 도시한 바와같이 식각된 상기 BARC(3)을 마스크로 하여 식각층(2)을 식각한다. 그리고 상기 포토레지스트(4)와 BARC(3)을 제거한다.Subsequently, the etching layer 2 is etched using the BARC 3 etched as a mask as shown in FIG. 1 (c). Then, the photoresist 4 and the BARC 3 are removed.
그러나 상기와 같은 종래의 하부 반사방지막 식각방법은 다음과 같은 문제점이 있었다.However, the conventional lower anti-reflection film etching method has the following problems.
보통 사용하는 BARC의 두께는 2000Å미만으로 스텝 커버리지(Step coverage)가 낮은 경우에는 BARC 식각공정에 크게 문제가 되지 않으나 스텝 커버리지가 심한 경우에 있어서는 BARC 두께차가 심해 상당한 정도의 오버에칭이 요구된다.Normally, the thickness of BARC used is less than 2000Å and it is not a big problem for the BARC etching process when the step coverage is low. However, when the step coverage is severe, the BARC thickness difference is severe and a considerable amount of overetching is required.
따라서 포토레지스트에 대한 BARC의 선택성이 나빠져 요구되는 포토레지스트의 두께도 높아지고 결과적으로 포토 공정의 마진이 감소하여 사용할 수 없게된다.As a result, the selectivity of BARC relative to the photoresist is deteriorated, so that the required thickness of the photoresist is increased, and as a result, the margin of the photo process is reduced and cannot be used.
본 발명은 이와같은 문제점을 해결하기 위하여 안출한 것으로 BARC과 포토레지스트의 선택성을 향상시켜 단차가 심한 경우에도 포토 공정의 마진을 증대 시키는데 적당한 하부 반사방지막 식각방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a lower anti-reflection film etching method suitable for increasing the margin of the photo process even if the step is severe by improving the selectivity of the BARC and the photoresist to solve such a problem.
제1(a)도 내지 제1(c)는 종래의 하부 반사방지막 식각방법을 나타낸 공정 단면도.1 (a) to 1 (c) are cross-sectional views illustrating a conventional lower anti-reflection film etching method.
제2(a)도 내지 제2(d)도는 본 발명의 하부 반사방지막 식각방법을 나타낸 공정 단면도.2 (a) to 2 (d) are cross-sectional views illustrating a method of etching a lower anti-reflection film according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
20 : 기판 21 : 식각층20: substrate 21: etching layer
22 : BARC 23 : 포토레지스트22: BARC 23: photoresist
24 : 실리콘24: silicone
상기와 같은 목적을 달성하기 위한 본 발명의 하부 반사방지막 식각방법은 기판상에 식각층, BARC, 포토레지스트를 차례로 형성하는 공정과, 상기 포토레지스를 노광 및 현상하여 포토레지스트를 패터닝하는 공정과, 상기 포토레지스트 표면을 실란과 반응 시키는 공정과, 상기 실란과 반응한 포토레지스트를 마스크로 이용하여 BARC, 식각층을 선택적으로 식각하는 공정과, 상기 포토레지스트와 BARC을 제거하는 공정을 포함하여 이루어짐을 특징으로 한다.The lower anti-reflection film etching method of the present invention for achieving the above object is a step of sequentially forming an etching layer, BARC, photoresist on the substrate, the process of patterning the photoresist by exposing and developing the photoresist; And reacting the surface of the photoresist with silane, selectively etching the BARC and the etching layer using the photoresist reacted with the silane as a mask, and removing the photoresist and BARC. It features.
이하, 첨부된 도면을 참조하여 본 발명의 하부 반사방지막 식각방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the lower anti-reflection film etching method of the present invention will be described in detail with reference to the accompanying drawings.
제2(a)도 내지 제2(c)도는 본 발명의 하부 반사방지막 식각방법을 나타낸 공정 단면도이다.2 (a) to 2 (c) are cross-sectional views illustrating a method of etching the lower anti-reflection film of the present invention.
제2(a)도에 도시한 바와같이 반도체 기판(20)상에 선택적으로 식각하고자 하는 식각층(21)을 형성하고, 상기 식각층(21)상에 BARC(22)을 증착한 후, 베이킹 공정을 한다.As shown in FIG. 2 (a), an etching layer 21 to be selectively etched is formed on the semiconductor substrate 20, and the BARC 22 is deposited on the etching layer 21, followed by baking. Do the process.
그리고 상기 BARC(22)상에 포토레지스트(23)를 도포하고 소프트 베이킹 공정을 실시한 후, 노광 및 현상공정으로 포토레지스트(23)를 패터닝한다.After the photoresist 23 is applied on the BARC 22 and a soft baking process is performed, the photoresist 23 is patterned by an exposure and development process.
이어, 제2(b)도에 도시한 바와같이 패터닝된 포토레지스트(23)를 실란(Silane : SiH4)과 반응시키면, 상기 패터닝된 포토레지스트(23)상에 실리콘(24)이 발생한다.Subsequently, when the patterned photoresist 23 is reacted with silane (Silane: SiH 4 ), as shown in FIG. 2 (b), silicon 24 is generated on the patterned photoresist 23.
여기서 포토레지스트(23)를 실란과 반응 시키면 포토레지스트(23) 내에서 일어나는 반응은 다음과 같다.Here, when the photoresist 23 is reacted with silane, the reaction occurring in the photoresist 23 is as follows.
노광을 거친 수지(Resin)은 PAC와 결합(Coupling) 되거나 또는 수지끼리 가교결합을 하게 되는데 이러한 결합에서 사용되지 않고 남은 자유 -OH와 Si 화합물이 반응하게 된다. 이때, BARC(22)에는 Si 화합물이 반응하지 않도록 BARC(22)에 사용되는 폴리머는 페놀(phenol)기를 포함하지 않는것으로 한다.Resin is exposed (Coupling) to the PAC (Coupling) or the cross-linking between the resin and the remaining free -OH and Si compound that is not used in this bond will react. At this time, the polymer used in the BARC (22) does not contain a phenol (phenol) group so that the Si compound does not react with the BARC (22).
이어서, 제2(c)도에 도시한 바와같이 패터닝된 포토레지스트(23)를 하드 베이킹 공정을 실시한 후, 상기 패터닝된 포토레지스트(23)를 마스크로 하여 BARC(22), 식각층(21)을 식각한다.Subsequently, as shown in FIG. 2 (c), after the hard baking process is performed on the patterned photoresist 23, the BARC 22 and the etching layer 21 are formed using the patterned photoresist 23 as a mask. Etch
이어 제2(d)도에 도시한 바와같이 상기 포토레지스트(23)와 BARC(22)을 제거하여 하부 반사방지막을 식각하는 것을 완료한다.Subsequently, as shown in FIG. 2 (d), the photoresist 23 and the BARC 22 are removed to finish etching the lower anti-reflection film.
이상에서 설명한 바와같이 본 발명의 하부 반사방지막 식각방법에 있어서는 다음과 같은 효과가 있다.As described above, the lower anti-reflection film etching method of the present invention has the following effects.
패터닝된 포토레지스트에 Sidl 포함되기 때문에 하부 반사방지막 식각시 선택성을 향상 시킬 수 있다.Since Sidl is included in the patterned photoresist, selectivity may be improved when etching the lower anti-reflection film.
따라서 단차가 심한 경우에도 하부 반사방지막 공정을 적용하여 포토공정 마진 증대의 효과를 볼 수 있다.Therefore, even if the step is severe, it is possible to apply the lower anti-reflection film process to increase the photo process margin.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960066698A KR100232185B1 (en) | 1996-12-17 | 1996-12-17 | Method for etching low layer antireflection coating film |
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| KR1019960066698A KR100232185B1 (en) | 1996-12-17 | 1996-12-17 | Method for etching low layer antireflection coating film |
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| KR100232185B1 true KR100232185B1 (en) | 1999-12-01 |
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| KR100480611B1 (en) | 2002-08-14 | 2005-03-31 | 삼성전자주식회사 | Method for forming fine patterns of semiconductor device using vapor phase silylation |
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