KR20030058247A - A forming method of semiconductor device with improved protection of pattern deformation - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of minimizing the deformation of photoresist patterns. CONSTITUTION: An insulating layer(22) as an object layer and a polymer source providing layer(24) are sequentially formed on a substrate(20) having a transistor. A photoresist pattern(25) is formed on the polymer source providing layer. The polymer source providing layer(24) is selectively etched to expose the insulating layer(22) by using HBr plasma and the photoresist pattern(25) as a mask. At this time, polymers(26) are attached at sidewalls of the photoresist patterns(25). The insulating layer(22) is then etched by using the photoresist pattern(25) including the polymers(26) as a mask.

Description

A forming method of semiconductor device with improved protection of pattern deformation

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a semiconductor device manufacturing method capable of preventing pattern deformation.

The microfabrication technology that has supported the progress of semiconductor devices is a photolithography technology, and it is no exaggeration to say that the improvement in resolution of this technology is directly connected to the future of high integration of semiconductor devices.

As is well known, the photolithography process includes a process of forming a photoresist pattern and a process of etching a layer to be etched through an etching process using the photoresist pattern as an etch mask to form a pattern having a desired shape such as a contact hole. Wherein the photoresist pattern includes a process of applying a photoresist on the etched layer, a process of exposing the photoresist using a prepared exposure mask, and a portion of the photoresist exposed or not exposed with a predetermined chemical solution; Through the development process.

On the other hand, the critical dimension of the pattern that can be implemented by the photolithography process (hereinafter referred to as CD) depends on the wavelength of the light source used in the above-described exposure process. This is because the CD of the actual pattern is determined by the width of the photoresist pattern that can be realized through the exposure process.

The wavelength of the light source used in the initial stepper adopting the “step and repeat” exposure method is from 436 nm (g-line) to 365 nm (i-line), and is now 248 nm (KrF Excimer Laser) wavelength. It mainly uses stepper or scanner type exposure equipment using DUV (Deep Ultra-violet). The 248 nm DUV photolithography initially produced a number of problems, such as time delay effects and substrate dependence. However, in order to develop a product having a design of 0.15 μm or less, it is necessary to develop a technology with a new DUV photolithography technique having a wavelength of 193 nm (ArF Excimer Laser). However, even if a combination of various techniques for enhancing the resolution in the DUV photolithography technique is impossible to pattern less than 0.1㎛, the development of a photolithography technique having a new light source is actively progressing.

At present, an ArF (argon fluoride) laser (λ = 193 nm) is being developed to target a pattern up to 0.11 mu m. DUV photolithography is superior in terms of performance and resolution compared to i-rays, but process control is not easy. These problems can be divided into optical causes due to short wavelengths and chemical causes due to the use of chemically amplified resists. If the wavelength is shortened, the CD shake phenomenon due to the stationary wave effect and the reflection of reflected light due to the substrate phase become worse. CD oscillation refers to a phenomenon in which the line thickness changes periodically as the degree of interference between incident light and reflected light changes depending on the slight thickness difference of the resist or the thickness difference of the substrate film. In the DUV process, a chemically amplified photoresist has to be used to improve sensitivity, and problems related to the reaction mechanism include PED (Post Exposure Delay) stability and substrate dependence. Development of a photoresist for ArF. ArF is a chemically amplified type such as KrF, but the material needs to be fundamentally improved. ArF photoresist material development is difficult because benzene rings cannot be used. Benzene rings have been used in photoresists for i-rays and KrF to ensure dry etching resistance. However, when the benzene ring is used in the ArF photoresist, since the absorbance is large at 193 nm, which is the wavelength region of the ArF laser, the transparency is poor and the exposure to the lower portion of the photoresist is impossible. For this reason, the research of the material which can ensure dry etching resistance, does not have a benzene ring, and has good adhesive force and can develop in 2.38% TMAH is progressing. To date, many companies and research institutes around the world have published their research results, but the commercially available ones are in the form of polymers of COMA (CycloOlefin-Maleic Anhydride) or Acrylate system, or a mixture thereof. However, the photoresist has the benzene structure as described above.

Accordingly, when the etching process is performed to form a gate through photolithography using an ArF exposure source, a portion of the pattern is slit due to the deformation of the stripe pattern, or the photoresist is agglomerated during etching. The plastic deformation and the resistance of the photoresist during the etching are weakened, which causes the fluorine-based gas, which is an etching gas for a hard mask, to be used to prevent etching loss of the gate. This is because it reacts with the photoresist for ArF such as acrylate, causing deformation of the photoresist itself.

Therefore, it is an urgent task to compensate for the weak durability of the ArF photoresist and the weak physical properties of the fluorine-based gas.

1A to 1D to be described below are scanning electron microscopy (SEM) photographs showing examples of the above-described pattern deformation, and FIGS. 1A and 1B serve as a barrier when etching an oxide layer for forming a capacitor. When the photoresist pattern is deformed during etching, the deformed photoresist pattern shape is transferred as it is, so that the inner wall of the lower oxide film is locally striated or overall deformation occurs.

FIG. 1A is a SEM photograph of a wafer stopped and a wafer taken out to observe a change in photoresist pattern in the middle of a capacitor oxide layer etch, and clearly shows the overall deformation 11 and local patch 12 of the photoresist pattern 10. Can be observed.

FIG. 1B is a final cross section after the capacitor oxide film is completely etched, which may not be a big problem as a whole. However, as shown in the drawing, the photoresist pattern serving as an etch barrier is deformed during etching, so that the shape is formed on the lower oxide film. As a result, the oxide walls inside the capacitor are unevenly deformed, as seen from the upper end of the etched oxide film.

In addition, FIGS. 1C to 1D illustrate a pattern deformation caused in an Self Align Contact (hereinafter referred to as SAC) etching process using a high selectivity with an underlying layer, for example, a nitride layer, when the oxide layer is etched.

FIG. 1C illustrates a local dent 12 occurring during a Landing Plug Contact (LPC) -1 process, which is an etching process for forming a plug for electrical connection with a source / drain junction during a 0.10 μm process, and FIG. 1D shows a capacitor And a total deformation 11 of the photoresist pattern that occurred during the LPC-2 process to form the plug needed for electrical connection with the lower LPC-1 plug.

The present invention proposed to solve the problems of the prior art as described above, an object of the present invention to provide a method for manufacturing a semiconductor device that can minimize the deformation of the high-resolution photoresist pattern, such as ArF according to the etching process.

1A to 1D are electron scanning micrographs showing examples of pattern modification;

2A to 2F are cross-sectional views illustrating a capacitor forming process of a semiconductor device according to an embodiment of the present invention;

3 is a cross-sectional and planar SEM photograph comparing the pattern shape according to FIGS. 2A to 2F with the prior art;

Figure 4 is a planar and cross-sectional SEM image showing the comparison of the pattern shape before and after the LPC-2 process of another embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: infrastructure 21: etch stop

22 insulating film 23 hard mask layer

24: polymer source providing film 25: photoresist pattern

26: polymer

In order to solve the above problems, the present invention comprises the steps of sequentially forming an etching target layer and a polymer source providing film on the substrate; Forming a photoresist pattern on the polymer source providing film; Etching the polymer source providing film by using an HBr-based plasma using the photoresist pattern as a mask to expose a predetermined region of the etched layer, wherein attaching a polymer to sidewalls of the photoresist pattern; And etching the etched layer using at least the photoresist pattern as an etch mask to expose the surface of the substrate.

The present invention is to protect the photoresist pattern during subsequent etching of the etching layer by encapsulating the photoresist pattern around the etching layer using a hard mask material and an etching gas that generates a large amount of polymer before etching the etching layer, such as the oxide layer below. It is a technical feature to do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may more easily implement the present invention. 2F is a cross-sectional view illustrating a capacitor forming process of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a cross-sectional and planar SEM photograph comparing the pattern shape of FIGS. 2A to 2F with the prior art, and FIG. It is a planar and cross-sectional SEM photograph which shows the pattern shape before and after the LPC-2 process which is another embodiment of the present invention.

First, as shown in FIG. 2A, each layer for forming a capacitor is formed on a predetermined lower structure 20, that is, a substrate, on which a transistor forming process or the like is completed.

Specifically, in order to prevent etch damage of the lower structure 20 during overetch in the capacitor oxide layer etch, after depositing the nitride-based etch stop layer 21 for etching stop, the capacitor structure is formed thereon. An oxide film 22 is deposited. Subsequently, the thickness of the photoresist for pattern formation is gradually reduced due to the reduction of the design rule, and it is difficult to etch the capacitor oxide film 22 of 1.5 µm or more with the thickness of the photoresist alone. A hard mask layer having a high etching selectivity with an oxide film under the photoresist is deposited. For example, polysilicon or the like is used alone or laminated.

Next, as shown in FIG. 2B, the polymer source providing layer 24 may be formed to form a thin and dense polymer on the sidewalls of the photoresist pattern to prevent dents or deformation of the photoresist pattern during subsequent etching of the oxide layer 22. Is formed, a polymer source material film such as a silicon oxynitride film, a silicon nitride film, a tantalum oxynitride film, or a tantalum oxide film is used alone or in a lamination, and is formed to have a thickness of 50 kPa to 500 kPa.

At this time, the polymer source providing film 24 can be used in direct contact with the oxide film 22.

Then, a photoresist such as COMA or acrylate is applied to a predetermined thickness, and then argon fluoride (ArF), chromium fluoride (KrF), electron beam, X-ray or EUV (Extream) is applied. Selectively expose a predetermined portion of the photoresist using an exposure source (not shown) such as Ultra-Violet) and a reticle (not shown) for defining the etch width of the trilayer 22 After the exposed or unexposed portions are left through the process, the photoresist pattern 25 is formed by removing etching residues or the like through a post-cleaning process.

Next, as shown in FIG. 2C, the hardmask layer 23 is exposed by etching the polymer source providing film 24 using the HBr-based plasma using the photoresist pattern 25 as an etch mask. When the etching gas component of the HBr, the carbon (C) component of the photoresist and the polymer source providing film 24 react with each other, a very thin and dense polymer 26 adheres to the sidewall of the photoresist pattern 25. The etching process is appropriately adjusted to have a thickness of ˜500 Pa.

In other words, the chamber pressure and the temperature are maintained at 1 mTorr to 100 mTorr and 0 ° C. to 300 ° C. during the process for the thickness and the film density of the polymer 26 attached to the sidewall, and the source power is 100 W to 2000 W and the bias power is 0 W. The temperature of the substructure 20 is maintained at 0 ° C to 300 ° C.

In addition, the amount of HBr gas is used as 5SCCM to 500SCCM, and Cl ₂ or O ₂ alone or mixed is adjusted until the content is 0% to 90% of the total, and this etching process is performed by Helicon ), Helical, Transformer Coupled Plasma (TCP), Inductively Coupled Plasma (ICP), Electro Cyclotron Resonance (ECR), or Surface Wave Plasma (SWP), or high density plasma sources (Parallel) plate), low / medium density plasma sources such as reactive ion etching (hereinafter referred to as RIE) or magnetically enhanced reactive ion etching (MERIE).

Next, as shown in FIG. 2D, the hard mask layer 23 is etched using the photoresist pattern 25 having the polymer 26 attached to the sidewall as an etch mask to expose the surface of the oxide film 22. Part of the photoresist pattern 25 is then etched to lower its height and its sidewalls are protected by the dense polymer 26.

Next, as shown in FIG. 2E, a partial thickness of the oxide layer 22 is etched by using the hard mask layer 23 including the photoresist pattern 25 as an etch mask to form a cross-sectional shape for forming a capacitor. At this time, the photoresist pattern 250, the polymer 26, and the polymer source providing film 24 are removed.

Next, as shown in FIG. 2F, an open part exposing a predetermined region of the lower structure 20 by etching the remaining oxide layer 22 and the etch stop layer 21 using the hard mask layer 23 as an etch mask. A part of the hard mask layer 23 remains at this time.

Thereafter, a general capacitor forming process is performed. For example, the hard mask layer 23 may be removed through surface etching, and then the lower electrode may be deposited, and the lower electrode may be separated through photoresist coating and chemical etching (CMP). Then, the capacitor formation process is completed through a series of processes of depositing a dielectric and an upper electrode for charge storage.

FIG. 3A illustrates a conventional side trimming and pattern deformation. FIG. 3B illustrates a planar etching profile of a capacitor oxide film according to an embodiment of the present invention. Figure 3 (c) shows a cross-sectional etching profile, in the above-described embodiment of the present invention by attaching a polymer to the sidewall of the photoresist pattern by the polymer attached to the sidewall when etching the lower layer By protecting the photoresist pattern, side dents and pattern deformation of the photoresist pattern can be prevented.

Next, the LPC-2 process according to another embodiment of the present invention will be described. Here, the process is performed under the same process conditions as the above-described embodiment. That is, by etching the polymer source providing film using the HBr-based plasma to attach a polymer to the sidewall of the photoresist pattern, it is possible to prevent the dents and deformation of the pattern.

FIG. 4 (a) is a planar SEM photograph showing the patterning pattern of the photoresist before the LPC-2 process using, for example, an ArF photoresist. FIG. 4 (b) shows the process of the present invention in FIG. 4 (a). 4 is a planar SEM photograph after LPC-2 etching, and FIGS. 4C and 4D are cross-sectional SEM photographs taken along the X and Y-axis directions of FIG. 4B, respectively.

That is, as shown in FIG. 4, the above-described effects may also be achieved in the LPC-2 process.

According to the present invention, the polymer is attached to the photoresist pattern sidewalls through an etching process using a polymer source providing film and an HBr etching gas in order to prevent loss and deformation of the photoresist due to the etching process. There is this.

end. In the conventional capacitor formation process, the capacitor area may be reduced due to the deformation of the photoresist pattern, and the desired dielectric value may not be obtained from the capacitor, which may not satisfy the refresh spec and cause serious problems in device reliability. As can be seen, the application of the present technology can prevent the deformation of the photoresist pattern inherently, thereby ensuring a stable capacitor formation process.

I. In the conventional LPC-2 process, the area of the contact \ opened due to the dents and the deformed shape of the photoresist may be reduced, a short circuit between the gate electrode / LPC-1, or a short circuit between the bit line / LPC-2 may occur, thereby causing a refresh. Since it may not meet the specifications or cause a lot of defects, serious problems may occur in the reliability of the device. Since the application of the present technology can prevent the deformation of the photoresist pattern inherently, a stable SAC process is performed. It can be secured.

Therefore, the present invention can improve the reliability of the device and shorten the development of process technology such as ArF.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above, by preventing the deformation and loss of the PR pattern according to the photolithography process, it can be expected to have an excellent effect that can ultimately improve the yield of the semiconductor device.

Claims (11)

Sequentially forming an etched layer and a polymer source providing film on the substrate; Forming a photoresist pattern on the polymer source providing film; Etching the polymer source providing film by using an HBr-based plasma using the photoresist pattern as a mask to expose a predetermined region of the etched layer, wherein attaching a polymer to sidewalls of the photoresist pattern; And Etching the etched layer using at least the photoresist pattern as an etch mask to expose the substrate surface Semiconductor device manufacturing method comprising a. The method of claim 1, The method of manufacturing a semiconductor device, characterized in that the etched layer includes an oxide film. The method of claim 1, And attaching the polymer to sidewalls of the photoresist pattern so that the polymer has a thickness of 0 kV to 500 kV. The method of claim 1, And attaching the polymer to sidewalls of the photoresist pattern, wherein the amount of the HBr gas is used in the range of 5 SCCM to 500 SCCM. The method of claim 4, wherein The method of manufacturing a semiconductor device, characterized in that to adjust the use until the content of 0% to 90% of the total by adding Cl ₂ or O ₂ alone or mixed to the gas. The method of claim 1, Attaching the polymer to the photoresist pattern sidewalls under a pressure of 1 mTorr to 100 mTorr and a temperature of 0 ° C to 300 ° C. The method of claim 6, In the step of attaching the polymer to the sidewall of the photoresist pattern, using a source power of 100W to 2000W and a bias power of 0W to 2000W, the semiconductor device characterized in that the temperature of the substrate is maintained at 0 ℃ ~ 300 ℃ Manufacturing method. The method of claim 1, A method of manufacturing a semiconductor device, wherein the polymer source providing film is formed to a thickness of 50 kV to 500 kV. The method of claim 1, The polymer source providing film includes at least one selected from the group consisting of a silicon oxynitride film, a silicon nitride film, a tantalum oxynitride film, and a tantalum oxide film. The method of claim 1, And forming a hard mask layer interposed between the etched layer and the polymer source providing film in forming the polymer source providing film. The method of claim 10, The hard mask layer is a semiconductor device manufacturing method characterized in that it comprises polysilicon.