KR100688710B1 - Method for etching anti-reflective coating - Google Patents
Method for etching anti-reflective coating Download PDFInfo
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- KR100688710B1 KR100688710B1 KR1020020061421A KR20020061421A KR100688710B1 KR 100688710 B1 KR100688710 B1 KR 100688710B1 KR 1020020061421 A KR1020020061421 A KR 1020020061421A KR 20020061421 A KR20020061421 A KR 20020061421A KR 100688710 B1 KR100688710 B1 KR 100688710B1
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- 238000005530 etching Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000006117 anti-reflective coating Substances 0.000 title description 3
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 12
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052734 helium Inorganic materials 0.000 claims description 2
- 239000001307 helium Substances 0.000 claims description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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Abstract
0.01㎛ 이하의 CD를 갖는 금속 배선을 형성할 수 있고, 기판의 에치 부분이나 다른 국소적인 부분에서 발생되는 마이크로 브리지 현상을 막을 수 있는 본 발명에 따른 반사 방지막 식각 방법은 반도체 기판의 상부에 금속막 및 반사 방지막을 적층하여 형성하는 단계와, 반사 방지막의 상부에 금속 배선을 정의하는 DUV 포토레지스트 패턴을 형성하는 단계와, Cl2 가스를 포함한 식각가스를 이용하여 상기 반사 방지막 및 금속막을 동일한 챔버에서 인시튜 식각하는 단계를 포함한다.The anti-reflection film etching method according to the present invention can form a metal wiring having a CD of 0.01 μm or less, and can prevent the microbridge phenomenon occurring at the etched portion or other localized portions of the substrate. Stacking and forming an anti-reflection film; forming a DUV photoresist pattern defining a metal wiring on the anti-reflection film; and identifying the anti-reflection film and the metal film in the same chamber by using an etching gas containing Cl 2 gas. Tu etching.
Description
도 1a 내지 도 1c는 종래 기술에 의한 금속 배선 형성 과정을 도시한 공정 단면도이다.1A to 1C are cross-sectional views illustrating a metal wire forming process according to the prior art.
도 2는 본 발명에 따른 금속 배선 형성을 위해 반사 방지막을 식각하는 과정을 도시한 흐름도이다.2 is a flowchart illustrating a process of etching an anti-reflection film to form a metal line according to the present invention.
＜도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10 : 반도체 기판 12 : 금속막10
14 : 반사 방지막 16 : 포토레지스트 패턴14
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 미세한 크기를 갖는 금속 배선을 형성할 수 있는 반사 반사막 식각 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a reflective reflective film capable of forming a metal wiring having a fine size.
반도체 장치 제조 분야에서, 종래의 소위 I-라인 포토레지스트로 가능한 것 보다 더 소형의 전자 및 광 디바이스의 패터닝을 가능하게 하도록 자외선 방사의 단파장을 위한 DUV(Deep Ultra Violet)가 개발되어 왔다. 일반적으로, 포토레지스트는 여러 가지 재로의 적층 위에 도포되어 후속 처리 단계에서 패터닝된다. 적층 내의 일부 층은 기능 디바이스의 일부가 되는 하부 층을 패터닝하는 동안에 소모된다. 포토레지스트의 공각 해상도를 이용하기 위해서는, 포토레지스트의 아래에 있는 반사 방지막(ARC : Anti-Reflective Coating)을 이용하여 포토레지스트 노출 중에 적층 내의 다른 층들의 반사를 억제해야할 필요가 있다. 따라서 반사 방지막에 의해 포토레지스트의 패터닝은 정확한 패턴 복사를 제공할 수 있다.In the field of semiconductor device manufacturing, deep ultra violet (DUV) has been developed for short wavelengths of ultraviolet radiation to enable the patterning of smaller electronic and optical devices than is possible with conventional so-called I-line photoresists. In general, the photoresist is applied onto a stack of various materials and patterned in subsequent processing steps. Some layers in the stack are consumed during patterning the underlying layer that becomes part of the functional device. In order to take advantage of the conformal resolution of the photoresist, it is necessary to use an anti-reflective coating (ARC) under the photoresist to suppress reflection of other layers in the stack during photoresist exposure. Therefore, the patterning of the photoresist by the antireflective film can provide accurate pattern copying.
가장 흔희 사용되는 반사 방지막의 재료는 티타늄 질화물이지만, DUV 포토레지스트와 조합하여 잘 기능하는 반사막로서는 실리콘 산화 질화물(SiNO)을 들 수 있다.The most commonly used antireflective film is titanium nitride, but silicon oxynitride (SiNO) is mentioned as a reflective film that functions well in combination with a DUV photoresist.
이하, 첨부된 도면을 참조하여 반사 방지막을 이용한 금속 배선 형성 과정을 설명한다. 도 1a 내지 도 1c는 반사 방지막을 이용한 금속 배선을 형성하는 과정을 도시한 공정 단면도이다.Hereinafter, a metal wiring forming process using an antireflection film will be described with reference to the accompanying drawings. 1A to 1C are cross-sectional views illustrating a process of forming a metal wiring using an antireflection film.
도 1a에 도시된 바와 같이, 반도체 기판(10)의 상부 전면에 금속막(12)을 형성하고, 금속막(12)의 상부에 실리콘 산화 질화물로 이루어진 반사 방지막(14)을 형성한다.As shown in FIG. 1A, the
이후, 도 1b에 도시된 바와 같이, 반사 방지막(14)의 상부에 DUV 포토레지스트를 이용하여 포토레지스트 패턴(16)을 형성한다.Thereafter, as shown in FIG. 1B, the
그리고 나서, 도 1c에 도시된 바와 같이, 포토레지스트 패턴(16)에 맞춰서 반사 방지막(14) 및 금속막(12)을 식각한 후에 포토레지스트 패턴(16)을 제거함으로서, 패터닝된 반사 방지막(14 ) 및 금속막(12 )으로 이루어진 금속 배선을 형성시킨다.Then, as shown in FIG. 1C, the patterned
최근, 반도체 디바이스의 공정 선폭이 갈수록 줄어듦에 따라 반도체 소자 제조에서 식각하는 방법이 중요하고, 임의의 공정 한계 조건 내에서 최소의 CD 값을 얻을 수 있는 식각 방법 개발이 진행 중이다. 그중에서 포토레지스트 패턴의 CD 보다 식각 후에 금속 배선의 CD가 더 작은 역 바이어스 공정이 있다.Recently, as the process line width of semiconductor devices decreases, etching methods in semiconductor device manufacturing are important, and etching methods for obtaining a minimum CD value within an arbitrary process limit condition are under development. Among them, there is a reverse bias process in which the CD of the metal wiring is smaller after etching than the CD of the photoresist pattern.
그러나, 역 바이어스 공정을 금속 배선 형성 공정에 적용한 경우에, 역 바이어스 공정은 불안한 금속 프로파일을 형성하는 문제점이 있다. 다시 말해서, 반도체 소자가 고집적화됨에 따라 회로의 선폭이 좁아지면서 금속막을 식각한 후에 극소적인 부분 도는 기판의 에지 부분에서 마이크로 브리지(micro bridge) 현상이 발생되는 문제점이 있다. However, when the reverse bias process is applied to the metal wiring forming process, the reverse bias process has a problem of forming an unstable metal profile. In other words, as the semiconductor device is highly integrated, the line width of the circuit is narrowed, and there is a problem in that a micro bridge phenomenon occurs in a very small portion or an edge portion of the substrate after etching the metal film.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 0.01㎛ 이하의 CD를 갖는 금속 배선을 형성할 수 있을 뿐만 아니라 마이크로 브리지 현상을 억제시킬 수 있는 반사 방지막 식각 방법을 제공하고자 한다.An object of the present invention is to solve the problems of the prior art, and to provide a method of anti-reflection film etching that can not only form a metal wiring having a CD of 0.01㎛ or less, but also can suppress the microbridge phenomenon.
상기와 같은 목적을 달성하기 위하여 본 발명은, 반도체 기판의 상부에 금속막 및 반사 방지막을 적층하여 형성하는 단계와, 상기 반사 방지막의 상부에 금속 배선을 정의하는 DUV 포토레지스트 패턴을 형성하는 단계와, Cl2 가스를 포함한 식각가스를 이용하고, 상기 포토레지스트 패턴을 식각 마스크로 상기 반사 방지막 및 금속막을 동일한 챔버에서 인시튜 식각하는 단계를 포함한다.In order to achieve the above object, the present invention, the step of forming a metal film and the anti-reflection film laminated on top of the semiconductor substrate, and forming a DUV photoresist pattern defining a metal wiring on the top of the anti-reflection film and And etching the anti-reflection film and the metal film in the same chamber using the etching gas including the Cl 2 gas and using the photoresist pattern as an etching mask.
본 발명의 실시 예는 다수개가 존재할 수 있으며, 이하에서 첨부한 도면을 참조하여 바람직한 실시 예에 대하여 상세히 설명하기로 한다. 이 기술 분야의 숙련자라면 이 실시 예를 통해 본 발명의 목적, 특징 및 이점들을 잘 이해할 수 있을 것이다.There may be a plurality of embodiments of the present invention, and a preferred embodiment will be described in detail below with reference to the accompanying drawings. Those skilled in the art will be able to better understand the objects, features and advantages of the present invention through this embodiment.
도 2는 본 발명의 바람직한 실시 예에 따른 금속 배선 형성을 위해 반사 방지막의 식각 과정을 도시한 공정 흐름도이다.2 is a process flowchart illustrating an etching process of an anti-reflection film for forming metal wirings according to a preferred embodiment of the present invention.
도 2를 참조하여 본 발명의 금속 배선 형성 과정을 설명하면, 먼저 종래의 기술과 동일하게 반도체 기판(10)의 상부에 금속막(12) 및 실리콘 산화 질화물로 이루어진 반사 방지막(14)을 순차 증착하고, 반사 방지막(14)의 상부에 DUV 포토레지스트를 패턴(16)을 형성한다(S100, S102).Referring to FIG. 2, a process of forming a metal wiring according to the present invention will be described. First, the
이후, DUV 포토레지스트 패턴(16)에 맞춰서 반사 방지막(14) 및 금속막(12)을 식각하는 공정은 동일한 챔버에서 이루어지는 인시츄(In-situ) 건식 식각 공정이다(S104). Thereafter, the process of etching the
이러한 인시츄 식각 공정에서 반사 방지막(14)을 식각할 때 사용되는 가스로는 Cl2, CHF3, Ar 등이 주로 사용된다.Cl2, CHF3, Ar, etc. are mainly used as the gas used to etch the
이때, 반사 방지막 식각 공정시 식각 가스인 Cl2 가스량은 따라 금속 배선의 CD에 영향을 준다. 다시 말해서, Cl2 가스량이 많으면 금속 배선의 CD가 줄고, Cl2 가스량이 적으면 금속 배선의 CD가 늘어난다. 이러한 현상이 유발되려면 반사 방지막(14)을 식각할 때 반사 방지막(14)의 두께가 50% 정도 과도 식각되어야 한다.At this time, the amount of Cl 2 gas, which is an etching gas, is affected by the anti-reflection film etching process. In other words, when the amount of Cl2 gas is large, the CD of the metal wiring decreases, and when the amount of Cl2 gas is small, the CD of the metal wiring increases. In order to cause this phenomenon, the thickness of the
그러나, 인시튜 식각 공정 시에 Cl2 가스량이 챔버로 너무 많이 플로우된 상 태에서 반사 방지막(14)이 식각될 때 DUV 포토레지스트 패턴이 많이 소모되어 계속되는 금속막(12) 식각의 여유를 떨어뜨린다. 이러한 이유로 인하여 무한정으로 Cl2의 양을 증가시킬 수 없다. 이에 인시튜 식각 공정에서 적절한 Cl2 가스양은 40sccm∼90sccm이다. 이러한 Cl2 가스량의 범위에서 Cl2 가스량이 많을수록 작은 CD를 갖는 금속 배선이 형성된다.However, when the
이때, 반사 방지막(14)을 식각하는 식각 조건에서 소스 전력은 1000∼16000W이고, 바이어스 전력은 50∼100W이고, 공정 챔버의 압력은 8∼10mT이고, 공정 챔버에 공급되는 CHF3의 가스량은 10∼20sccm이고, Ar 가스량은 0∼20sccm이고, 반도체 기판(10)의 뒷면에 공급되는 헬륨(He) 가스의 압력은 10∼12Torr이다.At this time, the source power is 1000 to 16000 W, the bias power is 50 to 100 W, the pressure in the process chamber is 8 to 10 mT, and the amount of CHF3 gas supplied to the process chamber is 10 to 1 in etching conditions for etching the
이상 설명한 바와 같이, 본 발명은 Cl2 가스를 포함한 식각가스를 이용하여 반사 방지막 및 금속막을 동일한 챔버에서 인시튜 식각함으로써, 0.01㎛ 이하의 CD를 갖는 금속 배선을 형성할 수 있고, 기판의 에치 부분이나 다른 국소적인 부분에서 발생되는 마이크로 브리지 현상을 막을 수 있다.As described above, the present invention can in-situ etch the antireflection film and the metal film in the same chamber using an etching gas containing Cl2 gas, thereby forming a metal wiring having a CD of 0.01 μm or less, It can prevent the micro bridge phenomenon occurring at other local parts.
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