m3 五、發明說明（1) 本發明係有關於半導體積體電路的製造，且特別是 關於一種提昇光阻層與被蝕刻層間蝕刻選擇性之方法利 用一斜角度離子植入程序以增強光阻層的抗蝕刻能力， 提昇光阻層與被餘刻層間餘刻選擇性。 隨著半導體製程技術發展，線寬及接觸窗的尺寸愈 愈小’微影方面為達到要求，於是須加入抗反射層’ (anti-reflection coating，ARC)並降低光阻厚度，以 到其所須之解析度。蝕刻方面因為無適當方式提昇光阻層 與抗反射層間之蝕刻選擇性’且光阻厚度降低，且製程上 之深寬比愈來愈大’於是造成臨界尺寸（critical dimension)損失嚴重及被蝕刻層條紋（striated)發生等 題。 。 上述傳統勉刻方法存有抗反射層與光阻層間的餘刻選 擇性並不大的潛在問題，並不利於尺寸縮小化元件的製 程β為了進一步了解其問題所在，以下即參照第丨A至〗c圖 之說明。首先，如第1A圖所示者’在一半導體基底1〇上， 形成一被蝕刻層1 2。之後，再形成一抗反射層丨4。接著， 以旋轉塗佈方法形成一光阻層16復蓋在抗反射層14表面 上’並以一微影成像程序定義出蝕刻圖案。 接下來，請參見第1B圏，利用上述光阻層16的圖案當 作罩幕，以活性離子蝕刻（R IE )程序蝕刻抗反射層1 4。其 中’由於抗反射層1 4與光阻層1 6間的蝕刻選擇性不大，因 此用來當作罩幕的光阻層16也會在飯刻過程中耗損，而成 為如圖中所示的構造1 6a。m3 5. Description of the invention (1) The present invention relates to the manufacture of semiconductor integrated circuits, and in particular to a method for improving the etching selectivity between a photoresist layer and an etched layer by using an oblique angle ion implantation procedure to enhance photoresistance. The anti-etching ability of the layer improves the selectivity between the photoresist layer and the remaining layer. With the development of semiconductor process technology, the smaller the line width and the size of the contact window are, the lithography needs to meet the requirements, so anti-reflection coating (ARC) must be added and the photoresist thickness must be reduced. The required resolution. In terms of etching, there is no proper way to improve the etching selectivity between the photoresist layer and the anti-reflection layer, and the thickness of the photoresist is reduced, and the aspect ratio in the process is getting larger and larger. Therefore, the critical dimension is severely lost and etched. Problems such as striation occur. . The above-mentioned conventional etching method has a potential problem that the remaining selectivity between the anti-reflection layer and the photoresist layer is not large, and is not conducive to the process of reducing the size of the element. In order to further understand the problem, the following is referred to Sections A to A. 〖C illustration. First, as shown in FIG. 1A, an etched layer 12 is formed on a semiconductor substrate 10. After that, an anti-reflection layer is formed. Next, a photoresist layer 16 is formed on the surface of the anti-reflection layer 14 by spin coating, and an etching pattern is defined by a lithography imaging program. Next, referring to Section 1B (i), the pattern of the photoresist layer 16 is used as a mask, and the anti-reflection layer 14 is etched by a reactive ion etching (R IE) procedure. Among them, since the etching selectivity between the anti-reflection layer 14 and the photoresist layer 16 is not large, the photoresist layer 16 used as a mask will also be consumed during the process of engraving and become as shown in the figure.的 结构 16 6a.
第4頁Page 4
__ 44¾¾ 五、發明說明（2) 其次，請參見第1C圖’再利用上述光阻層16a的圖案 當作罩幕’以活性離子蝕刻（RIE)程序蝕刻被蝕刻層丨2。 其中，由於被蝕刻層1 2與光阻層1 6間的蝕刻選擇性不大， 因此用來當作罩幕的光阻層16a在敍刻過程中幾乎完全耗 損’而被餘刻層12之餘刻圖案與原先所定義之圖案之臨界 尺寸有偏差。在以往由於元件的尺寸較大，因此尚可彌補 光阻層1 6抗蝕刻能力的不足，不致於影響元件的性質。然 而，隨著元件尺寸日益縮小化’光阻層〗6的厚度亦隨之減 小，漸漸地已不能提供足夠的抗蝕刻能力。 為了改善上述問題，在習知技術中有將第1A圖之餘刻 結構用烤盤預烤或紫外線預烤，但如此連帶也使得抗反射 廣硬化。若在被蝕刻層上多加幾層硬罩幕層，則會多出鍍 膜、钱刻及去除硬罩幕層等步驟，而增加了製程的複雜 度’導致生產效率的降低。是以，為了往後更細微尺寸之 積體電路的製程需要，實有必要謀求其他解決之道。 有鑑於此’本發明之一個目的，在於提供一種積體電 路的改良製程，其可增強光阻層的抗蝕刻能力，提昇光阻 層與被姓刻層間的蝕刻選擇性，以符合尺寸縮小化元件的 製程需求。 為達成上述之目的，本發明提出一種積體電路製程的 改良方法’其在蝕刻程序之前增加對光阻層施行一離子植 入程序’以增強光阻層的抗蝕刻能力，藉此可提昇光阻層 與被餘刻層間的蝕刻選擇性，即使當光阻層厚度隨元件尺 寸縮小化而減小時，仍可充分提供蝕刻罩幕的功能’而不__ 44¾¾ 5. Description of the invention (2) Secondly, please refer to FIG. 1C ′ and reuse the pattern of the photoresist layer 16 a as a mask ’to etch the etched layer 2 by the reactive ion etching (RIE) process. Among them, because the etching selectivity between the etched layer 12 and the photoresist layer 16 is not large, the photoresist layer 16a used as a mask is almost completely consumed during the engraving process, and is used by the remaining layer 12 The critical dimension of the remaining pattern is different from the previously defined pattern. In the past, due to the large size of the device, it can still make up for the lack of resistance to etching of the photoresist layer 16 and not affect the properties of the device. However, the thickness of the photoresist layer 6 has been reduced as the device size has been reduced, and it has gradually failed to provide sufficient etching resistance. In order to improve the above-mentioned problems, conventional techniques include pre-baking or UV pre-baking of the structure at the time of Fig. 1A, but this also makes the anti-reflection widely hardened. If a few more hard mask layers are added to the etched layer, there will be additional steps such as coating, money engraving, and removal of the hard mask layers, which increases the complexity of the process' and leads to a reduction in production efficiency. Therefore, in order to further process the integrated circuit of finer size, it is necessary to find other solutions. In view of this, an object of the present invention is to provide an improved process for an integrated circuit, which can enhance the anti-etching ability of the photoresist layer, and enhance the etching selectivity between the photoresist layer and the layer to be scribed to meet the reduction in size. Component process requirements. In order to achieve the above-mentioned object, the present invention proposes an improved integrated circuit manufacturing method 'which adds an ion implantation process to the photoresist layer before the etching process' to enhance the anti-etching ability of the photoresist layer, thereby improving the light The etching selectivity between the resist layer and the layer to be etched, even when the thickness of the photoresist layer decreases as the size of the device decreases, it can still fully provide the function of the etching mask.
五、發明說明（3) -- 會影響被姓刻層的餘刻效果^ 根據本發明的一個實施例，一種提昇光阻層與被蝕 層間蝕刻選擇性之方法，包括下列步驟：首先在—半導體 基底上形成一被蝕刻層，之後再形成一抗反射層。接著， 以旋轉塗佈方法形成一光阻層覆蓋在抗反射層表面上並 以一微影成像程序定義出蝕刻圖案。然後，對光阻層的圖 案施行一斜角度離子植入程序。再利用經離子植入處理 的光阻層圖案當作罩幕蝕刻抗反射層。接著再對光阻層的 圖案施行一斜角度離子植入程序。之後，再利用經離子植 入處理過的光阻層圖案當作罩幕蝕刻被蝕刻層。 為了讓本發明之上述和其他目的、特徵、及優點能更 明顯易僅’下文特舉若干較佳實施例’並配合所附圖式， 作詳細說明如下： 【圖式簡單說明】 第1 A至1C囷為根據習知技術之蝕刻製程的製造流程 剖面圖。 第2A至2C圖為根據本發明實施例之提昇光阻層與被姓 刻層間蚀刻選擇性的製造流程剖面圖。 [符號說明] 10、20〜半導體基底；12、22〜被蝕刻層；14、24〜抗 反射層；16、l6a、26~光阻層；28、28a〜硬化膜。 實施例 隨著元件尺寸縮小化的發展’微影成像程序的施行條 件也日益嚴苛’特別是在具有高反射性質的金屬層上方定 五、發明說明（4) 義導線圖案時，利用抗反射層（anti-reflection coating layer)來消除光學反射造成的干涉（interference)，進而 提昇微影成像精確度之改良製程已廣泛使用。以下配合第 2A至2C囷所作的說明，即係將本發明方法應用於含有抗反 射層之蝕刻結構的實施例。首先，在一半導體基底20上， 形成一被蝕刻層22，例如是一氮化物層、一氧化物層、或 一金屬層。之後，再形成一抗反射層24，例如是一有機聚 合物層。以形成如第2A圖所示之蝕刻結構。 接著’以旋轉塗佈方法形成一光阻層26覆蓋在抗反射 層24表面上，並以一微影成像程序定義出蝕刻圖案。然 後’對上述光阻層24的圖案施行一離子植入程序，此離子 植入程序是採用斜角度方式將離子植入到光阻層26上而不 打到抗反射層24，所使用之離子可以是硼、磷或砷等離 子’經由此離子植入後會在光阻層26之表面形成一硬化膜 28，此硬化膜28具有較佳之抗蝕刻能力。 請參見第2B围，利用上述經離子植入處理過的光阻層 26圊案當作罩幕’蝕刻抗反射層24，例如是使用含氣氣體 的活性離子蝕刻（r IE)程序，以形成所需的蝕刻圖案，其 中’因光阻層26表面之硬化膜28可提昇光阻與抗反射層間 的姓刻選擇性’因此可減少臨界尺寸（critical dimension)損失 ° 經由前述活性離子蝕刻程序，部分光阻硬化膜28會被 蝕刻掉。接著，請參見第2C圖，再一次地，對上述光阻層 24的圖案施行一斜角度離子植入程序，所使用之離子可以V. Description of the invention (3)-It will affect the effect of the last engraved layer ^ According to an embodiment of the present invention, a method for improving the etching selectivity between a photoresist layer and an etched layer includes the following steps: first in- An etched layer is formed on the semiconductor substrate, and then an anti-reflection layer is formed. Then, a photoresist layer is formed on the surface of the anti-reflection layer by a spin coating method, and an etching pattern is defined by a lithography imaging program. Then, an oblique angle ion implantation procedure is performed on the pattern of the photoresist layer. The photoresist layer pattern treated by ion implantation is used as a mask to etch the anti-reflection layer. Then, an oblique angle ion implantation procedure is performed on the pattern of the photoresist layer. After that, the photoresist layer pattern treated by ion implantation is used as a mask to etch the etched layer. In order to make the above and other objects, features, and advantages of the present invention more obvious and easy, only the following exemplified preferred embodiments and the accompanying drawings are described in detail as follows: [Schematic description of the drawings] Section 1 A 1C 囷 is a cross-sectional view of a manufacturing process of an etching process according to a conventional technique. Figures 2A to 2C are cross-sectional views of a manufacturing process for improving the etching selectivity between the photoresist layer and the layer to be etched according to an embodiment of the present invention. [Symbol description] 10, 20 to semiconductor substrate; 12, 22 to etched layer; 14, 24 to anti-reflection layer; 16, 16a, 26 to photoresist layer; 28, 28a to hardened film. Example With the development of the reduction in the size of components, the “implementation conditions of lithography imaging procedures are becoming increasingly severe”, especially above a metal layer with high reflection properties. 5. Description of the Invention (4) Use of anti-reflection when defining wire patterns An anti-reflection coating layer has been widely used to improve the lithography imaging accuracy by eliminating the interference caused by optical reflection. The following descriptions in conjunction with 2A to 2C are examples of applying the method of the present invention to an etched structure containing an anti-reflective layer. First, an etched layer 22 is formed on a semiconductor substrate 20, such as a nitride layer, an oxide layer, or a metal layer. After that, an anti-reflection layer 24 is formed, such as an organic polymer layer. To form an etched structure as shown in FIG. 2A. Next, a photoresist layer 26 is formed on the surface of the anti-reflection layer 24 by a spin coating method, and an etching pattern is defined by a lithography imaging program. Then, an ion implantation procedure is performed on the pattern of the photoresist layer 24. This ion implantation procedure uses an oblique angle method to implant ions on the photoresist layer 26 without hitting the antireflection layer 24. The ions used It can be boron, phosphorus, or arsenic plasma. After this ion implantation, a hardened film 28 is formed on the surface of the photoresist layer 26. The hardened film 28 has better resistance to etching. Please refer to Section 2B. The above-mentioned photoresist layer 26 treated with ion implantation is used as a mask to etch the anti-reflection layer 24. For example, a reactive ion etching (r IE) process using a gas is used to form The required etching pattern, where 'the hardened film 28 on the surface of the photoresist layer 26 can enhance the selectivity between the photoresist and the anti-reflection layer' can reduce the critical dimension loss. Through the aforementioned active ion etching process, Part of the photoresist hardened film 28 is etched away. Next, referring to FIG. 2C, once again, an oblique angle ion implantation process is performed on the pattern of the photoresist layer 24, and the ions used can be
4141® 5® 艺、· 五、發明說明（5) 是硼、磷或砷等離子，經由此離子植入後會在光阻層26之 表面再形成一硬化膜28a，此硬化膜28a亦具有較佳之抗姓 刻能力。之後，再利用上述經離子植入處理過的光阻層2 6 圖案當作罩幕’蝕刻被蝕刻層22 ’例如是使用含氯氣體的 活性離子触刻（R丨E )程序，以形成所需的蝕刻圖案，其 中’因光阻層26表面之硬化膜28a可提昇光阻與被蝕刻層 2 2間的蝕刻選擇性’因此可減少臨界尺寸（c r丨t丨c a 1 dimension)損失及被餘刻層條紋（striate(j)發生的情形。 本發明雖已藉較佳實施例的說明揭露如上，然其並非 用以限疋本發明’任何熟習此技藝者，在不脫離本發明之 精神和範圍内’當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。4141® 5® Art, · V. Description of the invention (5) It is boron, phosphorus or arsenic plasma. After this ion implantation, a hardened film 28a will be formed on the surface of the photoresist layer 26. This hardened film 28a also has Jia Zhi's ability to resist surnames. After that, the photoresist layer 2 6 pattern processed by the ion implantation is used as a mask to etch the etched layer 22 ′, for example, using a reactive ion etching (R 丨 E) process using a chlorine-containing gas to form the photoresist layer. The required etching pattern, in which 'the hardened film 28a on the surface of the photoresist layer 26 can improve the etching selectivity between the photoresist and the layer 2 to be etched', thereby reducing the critical dimension (cr 丨 t 丨 ca 1 dimension) loss and damage The occurrence of striation (j). Although the present invention has been disclosed above by the description of the preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art will not depart from the spirit of the present invention. "Within the scope" should be able to make a few changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
第8頁Page 8