KR100650902B1 - Semiconductor metal wiring and its manufacturing method - Google Patents

Semiconductor metal wiring and its manufacturing method Download PDF

Info

Publication number
KR100650902B1
KR100650902B1 KR1020030006327A KR20030006327A KR100650902B1 KR 100650902 B1 KR100650902 B1 KR 100650902B1 KR 1020030006327 A KR1020030006327 A KR 1020030006327A KR 20030006327 A KR20030006327 A KR 20030006327A KR 100650902 B1 KR100650902 B1 KR 100650902B1
Authority
KR
South Korea
Prior art keywords
etching
oxide
metal
metal wiring
manufacturing
Prior art date
Application number
KR1020030006327A
Other languages
Korean (ko)
Other versions
KR20040069786A (en
Inventor
박동훈
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020030006327A priority Critical patent/KR100650902B1/en
Publication of KR20040069786A publication Critical patent/KR20040069786A/en
Application granted granted Critical
Publication of KR100650902B1 publication Critical patent/KR100650902B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Abstract

본 발명은 종래의 이중 대머신(Dual Damascene) 기술에서 문제가 되는 것들 중에 제품의 수율이나 신뢰성에 치명적인 영향을 주는 포토 레지스트 프로파일 (Photo Resist Profile)의 불균일 및 잔류물(Residue)의 해결에 의한 제품의 수율 향상과 신뢰성 향상의 제공에 관한 것이다. The present invention is a product by solving the non-uniformity and residue of the Photo Resist Profile, which has a fatal effect on the yield or reliability of the product, among the problems of the conventional Dual Damascene technology. To improve yield and improve reliability.

본 발명의 반도체 금속 배선 제조방법은 금속관 유전체(IMD) 1을 화학 기계적 연마하는 제1공정; 상기 화학 기계적 연마된 IMD 위에 금속 패턴을 형성하는 제2공정; 산화물을 식각하는 제3공정; 산화물이 식각이 된 부분에 막질을 증착 및 화학 기계적 연마하는 제4공정; 비아 식각을 위해 산화물이 식각된 부분과 막질 위에 비아 패턴을 형성하는 제5공정; 막질을 건식 식각하고, 다시 산화물을 금속 아래부분까지 식각하는 제6공정 및 증착되어 있던 막질을 습식 식각을 이용하여 제거해 줌으로써 이중 다마신 구조를 형성하는 제7공정으로 이루어짐에 기술적 특징이 있다.A method of manufacturing a semiconductor metal wiring of the present invention includes a first step of chemical mechanical polishing the metal tube dielectric (IMD) 1; Forming a metal pattern on the chemical mechanically polished IMD; A third step of etching the oxide; A fourth step of depositing and chemical mechanical polishing the film quality on the portion where the oxide is etched; Forming a via pattern on the portion where the oxide is etched and the film for the via etching; There is a technical feature of the sixth step of dry etching the film quality, and then etching the oxide to the lower portion of the metal, and the seventh step of forming the double damascene structure by removing the deposited film quality by wet etching.

따라서, 본 발명의 반도체 금속 배선 및 그 제조방법은 금속 패턴 프로파일과 비아 홀내부의 포토 레지스트 잔류물을 제거할 수 있으므로 정확한 금속 패턴의 윤곽과 포토 레지스트 잔류물을 감소시켜 이로 인하여 발생할 수 있었던 현상에 의한 수율 및 신뢰성 저하를 막는 효과가 있다.Therefore, the semiconductor metal wiring of the present invention and the manufacturing method thereof can remove the metal pattern profile and the photoresist residue in the via hole, thereby reducing the contour of the metal pattern and the photoresist residue, thereby reducing the problem. There is an effect of preventing a decrease in yield and reliability.

반도체 금속 배선, 이중 대머신Semi-conductor metal wiring, double dama

Description

반도체 금속 배선 및 그 제조방법{Semiconductor metal wiring and its manufacturing method} Semiconductor metal wiring and its manufacturing method             

도 1은 종래기술의 반도체 금속 배선 제조방법1 is a method of manufacturing a semiconductor metal wiring of the prior art

도 2는 본 발명의 반도체 금속 배선 제조방법2 is a method of manufacturing a semiconductor metal wiring of the present invention

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

10: 금속 11: 금속관 유전체 110: metal 11: metal tube dielectric 1

12: 식각 방지용 층 13: 화학 기계적 연마된 금속관 유전체12: anti-etch layer 13: chemical mechanical polished metal tube dielectric

14: 금속 패턴 측면 15: 포토 레지스트 잔류물14 metal pattern side 15 photoresist residue

20: 금속 21: 금속관 유전체 120: metal 21: metal tube dielectric 1

22: 식각 방지용 층 23: 화학 기계적 연마된 금속관 유전체22: etch stop layer 23: chemical mechanical polished metal tube dielectric

24: 금속 패턴 25: 산화물이 식각된 부분24 metal pattern 25 oxide-etched portion

26: 막질 27: 비아 패턴26: film quality 27: via pattern

본 발명은 반도체 금속 배선 및 그 제조방법에 관한 것으로, 특히 종래의 이중 대머신(Dual Damascene) 기술에서 문제가 되는 것들 중에 제품의 수율이나 신뢰성에 치명적인 영향을 주는 포토 레지스트 프로파일(Photo Resist Profile)의 불균일 및 잔류물(Residue)을 해결하여 제품의 수율 향상과 신뢰성을 향상시키고자 함에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor metal wiring and a method of manufacturing the same, and more particularly, to the photoresist profile, which has a fatal effect on product yield and reliability, among those that are problematic in the conventional dual damascene technology. To solve the non-uniformity and residue (Residue) to improve the yield and reliability of the product.

종래에도 이중 대머신에 관한 반도체 금속 배선 제조방법이 있었는데, 도 1을 통하여 상세히 설명한다. 도 1a와 같이 금속(10)위에 금속관 유전체(Intermetal Dielectric, 이하 IMD) 1(11)을 증착하고, 금속 패터닝(Patterning) 후에 식각 시에 식각이 방지됨을 감지할 수 있는 식각 방지용 층(Etch Stopper Layer)(12)을 형성시킨다. 그 위에 화학 기계적 연마(Chemical Mechanical Polishing, 이하 CMP)된 IMD(13)를 증착하고, 도 1b와 같이 금속 패턴을 형성시켜 금속 아래부분까지 비아 식각(Via Etching)을 하여 홀을 형성하고, 다시 CMP된 IMD위에 금속 패턴 및 식각 방지용 층까지 식각을 진행하여 금속이 증착될 수 있는 영역을 확보하는 순서로 진행한다. Conventionally, there has been a method for manufacturing a semiconductor metal wiring for a double damascene, which will be described in detail with reference to FIG. 1. An etching stopper layer capable of depositing an intermetal dielectric (IMD) 1 (11) on the metal 10 as shown in FIG. 1A and detecting that etching is prevented during etching after metal patterning. 12). A chemical mechanical polishing (CMP) IMD 13 deposited thereon is deposited, and a metal pattern is formed as shown in FIG. 1B to via etching to the bottom of the metal to form holes, and then CMP. The etching proceeds to the metal pattern and the etch stop layer on the IMD in order to secure the area where the metal can be deposited.

그러나, 상기와 같은 종래의 반도체 금속 배선 제조방법은 금속 패터닝 공정시에 인접한 비아 홀(Via Hole)의 단차로 인하여 패터닝 완료 후에 도 1c와 같이 불균일한 금속 패턴 프로파일(14) 및 비아 홀 내부에 현상 시에 완전히 제거되지 않는 포토 레지스트 잔류물(15)이 생기는 문제점이 있다.However, in the conventional method of manufacturing a semiconductor metal wiring as described above, due to a step difference between adjacent via holes during a metal patterning process, a phenomenon occurs in a non-uniform metal pattern profile 14 and via holes as shown in FIG. 1C after patterning is completed. There is a problem that photoresist residues 15 are created that are not completely removed at the time.

특히, 대한민국 공개특허 제2000-0023003호는 반도체 기판의 표면 평탄화 처리 방법에 있어서 본 발명과 유사성을 보이고 있으나, 비아 홀 내부에 현상 시에 완전히 제거되지 않는 포토 레지스트 잔류물(15)이 남게 되는 것을 방지할 수 있는 방법이 제시되지 않고 있다.In particular, Korean Patent Laid-Open Publication No. 2000-0023003 shows a similarity to the present invention in the method of surface planarization of a semiconductor substrate, but the photoresist residue 15 which is not completely removed during development is left inside the via hole. There is no way to prevent it.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 종래의 이중 대머신 기술에서 문제가 되는 것들 중에 제품의 수율이나 신뢰성에 치명적인 영향을 주는 포토 레지스트 프로파일의 불균일 및 잔류물을 해결하여 제품의 수율 향상과 신뢰성 향상을 제공함에 본 발명의 목적이 있다. Accordingly, the present invention is to solve the problems of the prior art as described above, and to solve the non-uniformity and residue of the photoresist profile, which has a fatal effect on the yield or reliability of the product among those that are a problem in the conventional double damascene technology. It is an object of the present invention to provide improved product yield and improved reliability.

본 발명의 상기 목적은 종래의 이중 대머신 기술에서 문제가 되는 것들 중에 제품의 수율이나 신뢰성에 치명적인 영향을 주는 포토 레지스트 프로파일의 불균일 및 잔류물을 해결하여 제품의 수율 향상과 신뢰성 향상에 의해 달성된다. The above object of the present invention is achieved by improving the yield and reliability of the product by solving the non-uniformity and residues of the photoresist profile, which has a fatal effect on the yield or reliability of the product, among those problematic in the conventional dual damascene technology. .

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용 효과에 관한 자세한 사항은 바람직한 실시예를 도시하고 있는 도 2를 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the resulting effects thereof will be more clearly understood by the following detailed description with reference to FIG. 2, which shows a preferred embodiment.

종래의 이중 대머신 구조 형성 과정과는 달리, 본 발명에서는 도 2a와 같이 금속(20) 위에 IMD 1(21)을 증착하고, 금속 패터닝 후에 식각 시에 식각이 방지됨을 감지할 수 있는 식각 방지용 층(22)을 형성시킨다. 그 위에 CMP된 IMD(23)를 증착하고, 도 2b와 같이 그 위에 금속 패턴(24)을 형성하고, 도 2c와 같이 산화물을 식각한다. 이후에 산화물이 식각이 된 부분(25)에 도 2d와 같이 막질(26)을 증착 및 CMP하고, 비아 식각을 위해 도 2e와 같이 산화물이 식각된 부분(25)과 막질(26) 위에 비아 패턴(27)을 형성하여 도 2f와 같이 막질을 건식 식각(Dry Etching)하고, 다시 산화물을 금속 아래부분까지 식각한다. 비아 식각이 완료되면 도 2g와 같이 증착되어 있던 막질을 습식 식각(Wet Etching)으로 제거해 줌으로써 이중 대머신 구조를 형성하게 된다. 또한, 사용되는 모든 포토 레지스트 패턴 공정 시에 위상(Topology)이 없는 표면 상태에서 코팅(Coating)하게 되므로 단차가 없는 균일한 포토 레지스트 두께를 형성할 수 있고, 비아 홀 내부에는 포토 레지스트 패턴 공정을 거치지 않기 때문에 포토 레지스트가 남을 수 있는 여지를 미리 방지할 수 있다.       Unlike the conventional dual damascene structure forming process, in the present invention, as shown in FIG. 2A, IMD 1 (21) is deposited on the metal 20, and an etch preventing layer capable of detecting that etching is prevented during etching after metal patterning. (22) is formed. The CMP IMD 23 is deposited thereon, a metal pattern 24 is formed thereon as shown in FIG. 2B, and the oxide is etched as shown in FIG. 2C. Subsequently, the film layer 26 is deposited and CMP on the portion 25 where the oxide is etched, as shown in FIG. 2D, and the via pattern is formed on the layer 25 and the layer 26 where the oxide is etched, as shown in FIG. 2E, for via etching. (27) is formed to dry etch the film quality as shown in FIG. 2F, and the oxide is then etched down to the lower portion of the metal. When via etching is completed, the film structure deposited as shown in FIG. 2g is removed by wet etching to form a double damascene structure. In addition, since all the photoresist pattern processes are used, coating is performed in a surface state without a topology, so that a uniform photoresist thickness without a step can be formed, and a photoresist pattern process is not performed inside the via hole. In this case, it is possible to prevent the photoresist leaving room in advance.

따라서, 본 발명의 반도체 금속 배선 및 그 제조방법은 금속 패턴 프로파일과 비아 홀 내부의 포토 레지스트 잔류물을 제거할 수 있으므로 정확한 금속 패턴의 윤곽과 포토 레지스트 잔류물을 감소시켜 이로 인하여 발생할 수 있었던 현상에 의한 수율 및 신뢰성 저하를 막는 효과가 있다.Therefore, the semiconductor metal wiring of the present invention and the manufacturing method thereof can remove the metal pattern profile and the photoresist residues in the via holes, thereby reducing the contour of the metal pattern and the photoresist residues. There is an effect of preventing a decrease in yield and reliability.

Claims (5)

반도체 금속 배선 제조방법에 있어서,In the semiconductor metal wiring manufacturing method, 금속관 유전체(IMD) 1을 화학 기계적 연마하는 제1공정;Chemical mechanical polishing the metal tube dielectric (IMD) 1; 상기 화학 기계적 연마된 IMD 위에 금속 패턴을 형성하는 제2공정;Forming a metal pattern on the chemical mechanically polished IMD; 산화물을 식각하는 제3공정;A third step of etching the oxide; 산화물이 식각이 된 부분에 막질을 증착 및 화학 기계적 연마하는 제4공정;A fourth step of depositing and chemical mechanical polishing the film quality on the portion where the oxide is etched; 비아 식각을 위해 산화물이 식각된 부분과 막질 위에 비아 패턴을 형성하는 제5공정;Forming a via pattern on the portion where the oxide is etched and the film for the via etching; 막질을 건식 식각하고, 다시 산화물을 금속 아래부분까지 식각하는 제6공정; 및Dry etching the film quality, and etching the oxide to the lower portion of the metal; And 증착되어 있던 막질을 습식 식각을 이용하여 제거해 줌으로써 이중 다마신 구조를 형성하는 제7공정The seventh step of forming a double damascene structure by removing the deposited film by wet etching 으로 이루어짐을 특징으로 하는 반도체 금속 배선 제조방법.Method of manufacturing a semiconductor metal wiring, characterized in that consisting of. 제 1 항에 있어서, The method of claim 1, 상기 제2공정은 위상이 없는 표면 상태에서 코팅함을 특징으로 하는 반도체 금속 배선 제조방법The second process is a method for manufacturing a semiconductor metal wiring, characterized in that the coating in a surface state without a phase 제 1 항에 있어서, The method of claim 1, 상기 제5공정은 위상이 없는 표면 상태에서 코팅함을 특징으로 하는 반도체 금속 배선 제조방법The fifth process is a method of manufacturing a semiconductor metal wiring, characterized in that the coating in a surface state without a phase 삭제delete 제 1항 내지 제 3항 중의 어느 한 항의 방법으로 제조된 반도체 금속 배선.The semiconductor metal wiring manufactured by the method of any one of Claims 1-3.
KR1020030006327A 2003-01-30 2003-01-30 Semiconductor metal wiring and its manufacturing method KR100650902B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020030006327A KR100650902B1 (en) 2003-01-30 2003-01-30 Semiconductor metal wiring and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020030006327A KR100650902B1 (en) 2003-01-30 2003-01-30 Semiconductor metal wiring and its manufacturing method

Publications (2)

Publication Number Publication Date
KR20040069786A KR20040069786A (en) 2004-08-06
KR100650902B1 true KR100650902B1 (en) 2006-11-27

Family

ID=37358469

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020030006327A KR100650902B1 (en) 2003-01-30 2003-01-30 Semiconductor metal wiring and its manufacturing method

Country Status (1)

Country Link
KR (1) KR100650902B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604540B1 (en) * 2004-12-15 2006-07-24 동부일렉트로닉스 주식회사 Method for improving Damascence Process by stopper
US7435673B2 (en) 2005-09-28 2008-10-14 Samsung Electronics Co., Ltd. Methods of forming integrated circuit devices having metal interconnect structures therein

Also Published As

Publication number Publication date
KR20040069786A (en) 2004-08-06

Similar Documents

Publication Publication Date Title
KR100606532B1 (en) Method For Manufacturing Semiconductor Devices
KR100650902B1 (en) Semiconductor metal wiring and its manufacturing method
US6511916B1 (en) Method for removing the photoresist layer in the damascene process
US6613680B2 (en) Method of manufacturing a semiconductor device
KR100744803B1 (en) Method of manufacturing MIM capacitor of semiconductor device
TWI803645B (en) Method for planarizing semiconductor structure
KR100571406B1 (en) Method for manufacturing metal wiring of semiconductor device
KR100657746B1 (en) Method for Forming Via Holes In Semiconductor Device
KR100912958B1 (en) Method for fabricating fine pattern in semiconductor device
KR100379530B1 (en) method for forming dual damascene of semiconductor device
KR100800667B1 (en) Method for fabricating semiconductor device
KR100277869B1 (en) Method of forming an isolation region of a semiconductor device
JP3833603B2 (en) Manufacturing method of semiconductor device
KR100561524B1 (en) Method for fabricating shallow trench isolation
KR100685618B1 (en) Methoe for fabricating of semiconductor device
KR100456420B1 (en) Method of forming a copper wiring in a semiconductor device
JP2001332621A (en) Semiconductor device and method of manufacturing the same
KR100576438B1 (en) Semiconductor device fabrication method
KR100499396B1 (en) Method for manufacturing semiconductor device
KR100596279B1 (en) Method for forming the mim pattern of semiconductor device
KR100617044B1 (en) method for forming metal line of semiconductor device
KR100277935B1 (en) Wiring Formation Method of Semiconductor Device
KR100639002B1 (en) Method for improving the via hole defect of semiconductor device
KR100217907B1 (en) Process for forming interlayer insulator of semiconductor device
KR100876862B1 (en) Metal wiring formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
J201 Request for trial against refusal decision
E801 Decision on dismissal of amendment
B601 Maintenance of original decision after re-examination before a trial
J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20050607

Effective date: 20061019

S901 Examination by remand of revocation
GRNO Decision to grant (after opposition)
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111020

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20121026

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee