KR100639002B1 - Method for improving the via hole defect of semiconductor device - Google Patents

Method for improving the via hole defect of semiconductor device Download PDF

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KR100639002B1
KR100639002B1 KR1020040114629A KR20040114629A KR100639002B1 KR 100639002 B1 KR100639002 B1 KR 100639002B1 KR 1020040114629 A KR1020040114629 A KR 1020040114629A KR 20040114629 A KR20040114629 A KR 20040114629A KR 100639002 B1 KR100639002 B1 KR 100639002B1
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semiconductor substrate
via hole
film
etching
forming
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KR1020040114629A
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Korean (ko)
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KR20060075745A (en
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김운섭
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer

Abstract

본 발명은 반도체 소자의 비아 홀 결손 개선 방법에 관한 것으로, 보다 자세하게는 소정의 패턴이 형성된 반도체 기판 상에 금속막을 증착하는 단계; 상기 금속막 상부에 제1 식각 마스크를 형성하여 상기 금속막을 식각하는 단계; 상기 금속막이 식각된 반도체 기판을 용매 세정하는 단계; 용매로 세정된 상기 반도체 기판 상에 질화막을 증착하는 단계; 상기 질화막을 블랭킷 식각하는 단계; 상기 블랭킷 식각된 반도체 기판 상에 IMD막을 증착시키고, CMP 공정으로 평탄화하는 단계; 상기 평탄화된 반도체 기판 상에 제2 식각 마스크를 형성하고 식각하여 비아 홀을 형성하는 단계로 이루어짐에 기술적 특징이 있다.The present invention relates to a method for improving via hole defects in a semiconductor device, and more particularly, depositing a metal film on a semiconductor substrate on which a predetermined pattern is formed; Etching the metal layer by forming a first etching mask on the metal layer; Solvent cleaning the semiconductor substrate etched with the metal film; Depositing a nitride film on the semiconductor substrate washed with a solvent; Blanket etching the nitride film; Depositing an IMD film on the blanket etched semiconductor substrate and planarizing the same by a CMP process; Technical features include forming via holes by forming and etching a second etching mask on the planarized semiconductor substrate.

따라서, 본 발명의 반도체 소자의 비아 홀 결손 개선 방법은 금속과 비아 홀의 배열 오류(Miss-Align)를 방지하고, 비아 홀 결손(Defect)을 억제하여 소자의 생산 수율을 향상시키고, 절연막이 아닌 TiN을 사용하여 도전막을 형성하므로써, 비아의 저항 상승을 막는 효과가 있다.Accordingly, the method of improving via hole defects of the semiconductor device of the present invention prevents misalignment of metals and via holes, suppresses via hole defects, and improves the production yield of devices. By forming the conductive film using, the resistance of the via is prevented from rising.

비아 홀 결손, 블랭킷 식각, 측벽 스페이서, TiNVia Hole Missing, Blanket Etch, Sidewall Spacer, TiN

Description

반도체 소자의 비아 홀 결손 개선 방법{Method for improving the via hole defect of semiconductor device} Method for improving the via hole defect of semiconductor device             

도 1a 및 도 1b는 종래기술에 의한 반도체 소자의 비아 홀 형성 방법을 나타낸 단면도.1A and 1B are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to the prior art.

도 2a 및 도 2b는 본 발명에 의한 반도체 소자의 비아 홀 결손 개선 방법을 나타낸 단면도. 2A and 2B are cross-sectional views showing a method for improving via hole defects in a semiconductor device according to the present invention.

도 3a는 종래기술에 의한 반도체 반도체 소자의 비아 홀 형성시 발생하는 비아 홀 결손을 나타낸 사진.FIG. 3A is a photograph showing via hole defects occurring when via holes are formed in a semiconductor device according to the related art. FIG.

도 3b는 본 발명에 의한 반도체 반도체 소자의 비아 홀 형성시 정상적으로 형성되는 비아 홀을 나타낸 사진.Figure 3b is a photograph showing a via hole that is normally formed when forming the via hole of the semiconductor semiconductor device according to the present invention.

본 발명은 반도체 소자의 비아 홀(Via Hole) 결손(Defect) 개선 방법에 관한 것으로, 보다 자세하게는 소정의 패턴이 형성된 반도체 기판 상에 금속막을 증착하 는 단계; 상기 금속막 상부에 제1 식각 마스크를 형성하여 상기 금속막을 식각하는 단계; 상기 금속막이 식각된 반도체 기판을 용매 세정하는 단계; 용매로 세정된 상기 반도체 기판 상에 질화막을 증착하는 단계; 상기 질화막을 블랭킷 식각(Blanket Etch)하는 단계; 상기 블랭킷 식각된 반도체 기판 상에 금속층간 유전체막(Intermetal Dielectric, 이하 IMD)막을 증착시키고, 기계화학적연마(Chemical Mechanical Polishing, 이하 CMP) 공정으로 평탄화하는 단계; 및 상기 평탄화된 반도체 기판 상에 제2 식각 마스크를 형성하고 식각하여 비아 홀을 형성하는 단계로 이루어진 반도체 소자의 비아 홀 결손 개선 방법에 관한 것이다.The present invention relates to a method for improving via hole defects in a semiconductor device, and more particularly, depositing a metal film on a semiconductor substrate on which a predetermined pattern is formed; Etching the metal layer by forming a first etching mask on the metal layer; Solvent cleaning the semiconductor substrate etched with the metal film; Depositing a nitride film on the semiconductor substrate washed with a solvent; Blanket etching the nitride film; Depositing an intermetal dielectric (IMD) film on the blanket-etched semiconductor substrate and planarizing the same by a chemical mechanical polishing (CMP) process; And forming a via hole by forming and etching a second etching mask on the planarized semiconductor substrate.

도 1a 및 도 1b는 본 발명에 의한 반도체 소자의 비아 홀 결손 개선 방법을 나타낸 단면도이다. 1A and 1B are cross-sectional views illustrating a method for improving via hole defects in a semiconductor device according to the present invention.

먼저, 도 1a에서 보는 바와 같이 소정의 패턴이 형성된 반도체 기판(101)상에 금속막(102)을 증착하고, 제1 식각 마스크(103)를 형성하여 상기 금속막을 식각한다. 이어서, 상기 금속막이 식각된 반도체 기판을 용매로 세정한 다음, 기판상에 IMD막(104)을 증착시킨다. First, as shown in FIG. 1A, a metal film 102 is deposited on a semiconductor substrate 101 on which a predetermined pattern is formed, and a first etching mask 103 is formed to etch the metal film. Subsequently, the semiconductor substrate etched with the metal film is washed with a solvent, and then an IMD film 104 is deposited on the substrate.

다음, 도 2b에서 보는 바와 같이 상기 IMD막을 CMP 공정으로 평탄화시킨 다음, 상기 평탄화된 반도체 기판 상에 제2 식각 마스크(105)를 형성하고 식각하여 비아 홀을 형성한다. Next, as shown in FIG. 2B, the IMD layer is planarized by a CMP process, and then a second etching mask 105 is formed on the planarized semiconductor substrate and etched to form via holes.

그러나, 상기와 같은 종래의 반도체 소자의 비아 홀 형성 방법에서는 비아 홀 식각시 하부 금속과 오버랩 마진(Overlap Margin)이 적은 특정 패턴(Pattern)에서 비아 홀 결손(A)이 발생하여, 후속 공정에서 텅스텐 증착시 정상적으로 증착되 지 않기 때문에 금속간의 연결 고리(Contact) 역할을 하지 못하고, 배열 오류가 발생하여 비아의 저항을 상승시키는 문제점이 있었다. However, in the method of forming a via hole of a conventional semiconductor device as described above, via hole defects A occur in a specific pattern having a low overlap margin with a lower metal during via hole etching. Since it is not normally deposited at the time of deposition, there is a problem in that it does not act as a connection ring between metals and an array error occurs, thereby increasing the resistance of the via.

도 3a는 종래기술에 의한 반도체 반도체 소자의 비아 홀 형성시 발생하는 비아 홀 결손을 나타낸 사진이다. FIG. 3A is a photograph showing via hole defects occurring when a via hole is formed in a semiconductor device according to the related art. FIG.

따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 금속막 식각하고, 질화막을 증착한 후 블랭킷 식각을 실시하여 측벽 스페이서(Side Wall Spacer)를 형성하여 공정의 오버랩 마진(Overlap Margin)을 확보할 수 있으므로, 금속과 비아 홀의 배열 오류(Miss-Align)를 방지하고, 비아 홀 결손을 억제하여 소자의 생산 수율을 향상시키고, 절연막이 아닌 TiN을 사용하여 도전막을 형성하여 비아의 저항의 상승을 막는 효과가 있는 반도체 소자의 비아 홀 결손 개선 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, by etching the metal film, depositing the nitride film and then performing a blanket etching to form a side wall spacer (Side Wall Spacer) overlap margin of the process (Overlap Margin ), It is possible to prevent mis-alignment of metal and via holes, to suppress via hole defects, and to improve the yield of device production. It is an object of the present invention to provide a method for improving via hole defects in a semiconductor device, which has an effect of preventing a rise of the semiconductor device.

본 발명의 상기 목적은 소정의 패턴이 형성된 반도체 기판 상에 금속막을 증착하는 단계; 상기 금속막 상부에 제1 식각 마스크를 형성하여 상기 금속막을 식각하는 단계; 상기 금속막이 식각된 반도체 기판을 용매 세정하는 단계; 용매로 세정된 상기 반도체 기판 상에 질화막을 증착하는 단계; 상기 질화막을 블랭킷 식각하는 단계; 상기 블랭킷 식각된 반도체 기판 상에 IMD막을 증착시키고, CMP 공정으로 평탄화하는 단계; 및 상기 평탄화된 반도체 기판 상에 제2 식각 마스크를 형성하고 식각하여 비아 홀을 형성하는 단계로 이루어진 반도체 소자의 비아 홀 결손 개선 방법에 의해 달성된다.The object of the present invention is the step of depositing a metal film on a semiconductor substrate having a predetermined pattern; Etching the metal layer by forming a first etching mask on the metal layer; Solvent cleaning the semiconductor substrate etched with the metal film; Depositing a nitride film on the semiconductor substrate washed with a solvent; Blanket etching the nitride film; Depositing an IMD film on the blanket etched semiconductor substrate and planarizing the same by a CMP process; And forming a via hole by forming and etching a second etching mask on the planarized semiconductor substrate.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 및 도 2b는 본 발명에 의한 반도체 소자의 비아 홀 결손 개선 방법을 나타낸 단면도이다. 2A and 2B are cross-sectional views illustrating a method for improving via hole defects in a semiconductor device according to the present invention.

먼저, 도 2a는 질화막으로 이루어진 측벽 스페이서를 형성하는 단계이다. 도시된 바와 같이 소정의 패턴이 형성된 반도체 기판(201)상에 금속막(202)을 증착하고, 상기 금속막 상부에 제1 식각 마스크(203)를 형성하여 상기 금속막을 식각한다. 이 때, 상기 금속막은 구리막 또는 알루미늄막을 사용하는 것이 바람직하다. First, FIG. 2A is a step of forming a sidewall spacer made of a nitride film. As illustrated, a metal film 202 is deposited on the semiconductor substrate 201 having a predetermined pattern, and a first etching mask 203 is formed on the metal film to etch the metal film. At this time, the metal film is preferably a copper film or an aluminum film.

이어서, 상기 금속막이 식각된 반도체 기판을 용매로 세정하고, 용매로 세정된 상기 반도체 기판 상에 질화막(204)을 증착한 다음, 상기 질화막을 블랭킷 식각한다. 이 때, 상기 질화막은 도전막인 TiN을 사용하는 것이 바람직하며, 상기 블랭킷 식각된 질화막은 측벽 스페이서(Side Wall Spacer)(205)로 작용하여, 상기 비아 홀 형성시 결손을 억제한다. Subsequently, the semiconductor substrate etched with the metal film is cleaned with a solvent, a nitride film 204 is deposited on the semiconductor substrate washed with the solvent, and the nitride film is blanket-etched. In this case, the nitride layer is preferably TiN, which is a conductive layer. The blanket-etched nitride layer acts as a side wall spacer 205 to suppress defects when the via hole is formed.

다음, 도 2b는 비아 홀을 형성하는 단계이다. 도시된 바와 같이 상기 블랭킷 식각된 반도체 기판 상에 IMD막(206)을 증착시키고, CMP 공정으로 평탄화시킨 다음, 상기 평탄화된 반도체 기판 상에 제2 식각 마스크를 형성하고 식각하여 비아 홀을 형성한다. Next, FIG. 2B is a step of forming a via hole. As illustrated, an IMD layer 206 is deposited on the blanket etched semiconductor substrate, and planarized by a CMP process, and then a second etch mask is formed and etched on the planarized semiconductor substrate to form via holes.

도 2a (B)및 도 3b는 본 발명에 의한 반도체 반도체 소자의 비아 홀 형성시 정상적으로 형성되는 비아 홀을 나타낸 사진이다. 2A and 2B are photographs showing via holes that are normally formed when via holes are formed in a semiconductor semiconductor device according to the present invention.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시 예를 들어 도시하고 설명하였으나, 상기한 실시 예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 반도체 소자의 비아 홀 결손 개선 방법은 금속막을 식각하고, 질화막을 증착한 후 블랭킷 식각(Blanket Etch)을 실시하여 측벽 스페이서(Side Wall Spacer)를 형성하여 공정의 오버랩 마진(Overlap Margin)을 확보할 수 있으므로, 금속과 비아 홀의 배열 오류(Miss-Align)를 방지하고, 비아 홀 결손(Defect)을 억제하여 소자의 생산 수율을 향상시키고, 절연막이 아닌 TiN을 사용하여 도전막을 형성하여 비아의 저항의 상승을 막는 효과가 있다.Therefore, in the method for improving via hole defects of the semiconductor device according to the present invention, an overlap margin of a process is formed by etching a metal film, depositing a nitride film, and performing a blanket etching to form side wall spacers. ), It is possible to prevent mis-alignment of metal and via holes, to suppress via hole defects, to improve device production yield, and to form a conductive film using TiN rather than an insulating film. This is effective in preventing the increase in the resistance of the via.

Claims (4)

반도체 소자의 비아 홀 결손 개선 방법에 있어서,In the method for improving the via hole defect of a semiconductor device, 소정의 패턴이 형성된 반도체 기판 상에 금속막을 증착하는 단계;Depositing a metal film on a semiconductor substrate on which a predetermined pattern is formed; 상기 금속막 상부에 제1 식각 마스크를 이용하여 상기 금속막을 식각하여 상기 반도체 기판 상에 금속막 패턴을 형성하는 단계; Forming a metal layer pattern on the semiconductor substrate by etching the metal layer by using a first etching mask on the metal layer ; 상기 금속막 패턴이 형성된 반도체 기판을 용매 세정하는 단계;Solvent cleaning the semiconductor substrate on which the metal film pattern is formed ; 용매로 세정된 상기 반도체 기판 상에 도전성 질화막을 증착하는 단계;Depositing a conductive nitride film on the semiconductor substrate washed with a solvent; 상기 도전성 질화막을 블랭킷 식각하여 상기 금속막 패턴의 측벽에 도전성 스페이서를 형성하는 단계; Blanket etching the conductive nitride film to form a conductive spacer on a sidewall of the metal film pattern ; 상기 블랭킷 식각된 반도체 기판 상에 IMD막을 증착시키고, CMP 공정으로 평탄화하는 단계; 및Depositing an IMD film on the blanket etched semiconductor substrate and planarizing the same by a CMP process; And 상기 평탄화된 반도체 기판 상에 제2 식각 마스크를 형성하고 식각하여 비아 홀을 형성하는 단계Forming a via hole by forming and etching a second etching mask on the planarized semiconductor substrate 로 이루어짐을 특징으로 하는 반도체 소자의 비아 홀 결손 개선 방법.Via hole defect improvement method of the semiconductor device, characterized in that consisting of. 제 1 항에 있어서,The method of claim 1, 상기 금속막은 구리막 또는 알루미늄막인 것을 특징으로 하는 반도체 소자의 비아 홀 결손 개선 방법.And the metal film is a copper film or an aluminum film. 제 1 항에 있어서,The method of claim 1, 상기 도전성 질화막은 TiN인 것을 특징으로 하는 반도체 소자의 비아 홀 결손 개선 방법.The conductive nitride film is TiN, characterized in that via hole defect improvement method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 블랭킷 식각된 상기 도전성 질화막은 측벽 스페이서(Side Wall Spacer)로 작용하며, 상기 비아 홀 형성시 결손을 억제하는 것을 특징으로 하는 반도체 소자의 비아 홀 결손 개선 방법.The blanket-etched conductive nitride layer acts as a side wall spacer and suppresses defects when forming the via holes.
KR1020040114629A 2004-12-29 2004-12-29 Method for improving the via hole defect of semiconductor device KR100639002B1 (en)

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