KR101068149B1 - Method for forming landing plug of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a landing plug of a semiconductor device. The disclosed method includes forming a gate electrode with a hard mask film on a semiconductor substrate, depositing an interlayer insulating film on the substrate to cover the gate electrode, and etching the interlayer insulating film to several gates. Forming a landing plug contact that simultaneously exposes a portion of the substrate between the electrode and the gate electrode, subjecting the substrate to H2 plasma to remove the carbon component in the interlayer insulating film, and depositing a conductive film on the substrate to fill the landing plug contact And CMPing the interlayer insulating film and the conductive film to expose the hard mask film. According to the present invention, Pinocchio defects can be suppressed by reducing the carbon group of the interlayer insulating film through H2 plasma treatment, thereby reducing the etching by-products by carbon during the subsequent CMP process.

Description

Method for forming landing plug of semiconductor device

1A and 1B are cross-sectional views illustrating processes for forming a landing plug of a semiconductor device according to the related art.

2A to 2E are cross-sectional views of processes for describing a method for forming a landing plug of a semiconductor device according to an exemplary embodiment of the present invention.

Description of the Related Art [0002]

21: semiconductor substrate 22: gate electrode

22a: gate oxide film 22b: gate conductive film

22c: gate hard mask film 23: spacer nitride film

24: interlayer insulating film 25: landing plug contact hole

26: landing plug

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a landing plug contact of a semiconductor device.                         

In the conventional CMP process, a slurry is used to isolate the plug, thereby polishing the plug material and the word line, that is, the nitride film used as the hard mask layer of the gate, and the oxide film used as the planarization and gap fill material. When the plug material and the oxide film dished due to the difference in etching selectivity of the nitride film, the plug material and the oxide film caused a number of problems appear.

In particular, when the CMP polishing residue penetrates into the plug material and the oxide dish dishing area, the CMP polishing residue is not removed in a subsequent cleaning process, causing a bridge between landing plugs, thereby reducing the yield of the device.

Hereinafter, a method for forming a contact plug of a semiconductor device according to the related art will be described.

1A and 1B are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the prior art.

Referring to FIG. 1A, a plurality of gate electrodes 12 are formed on the semiconductor substrate 11. Here, it can be understood that the gate electrode is composed of a gate oxide film 12a, a gate conductive film 12b, and a gate hard mask film 12c. Then, gate spacers 13 are formed on both sides of the gate electrode 12.

Subsequently, an interlayer insulating film 14 is formed on the substrate 11 to cover the gate electrode 12, and CMP is planarized. Typically, the interlayer insulating film 14 is made of BPSG, which includes carbon.

Then, a portion of the interlayer insulating layer 14 and the hard mask layer 12c of the gate electrode is etched in a self-aligned contact (hereinafter referred to as SAC) method to define a contact hole 15 defining a region where a landing plug is to be formed. ).

Referring to FIG. 1B, a conductive material is embedded to fill the contact hole 15, and the landing plug 16 is formed between each gate electrode by CMP to insulate the conductive material from each other.

However, in the method of forming a landing plug according to the related art as described above, the CMP process for forming the landing plug simultaneously CMPs a nitride film, which is a hard mask film, and a poly film, which is a nitride film landing plug material, which is an interlayer insulating film. There is a problem that bridges between plugs, also known as Pinocchio defects, are generated due to by-products caused by carbon components included in the insulating film.

Accordingly, the present invention has been made to solve the problems according to the prior art as described above, in the process of forming a landing plug of the semiconductor device, a bridge between the landing plug, a semiconductor that can suppress the occurrence of pinocchio defects It is an object of the present invention to provide a method for forming a landing plug contact of a device.

In order to achieve the above object, the present invention, forming a gate electrode having a hard mask film on a semiconductor substrate; Depositing an interlayer insulating film on a substrate to cover the gate electrode; Etching the interlayer insulating film to form a landing plug contact hole simultaneously exposing several gate electrodes and a portion of the substrate between the gate electrodes; H2 plasma treatment to remove the carbon component in the interlayer insulating film; Depositing a conductive film on a substrate to fill the landing plug contact hole; And CMPing the interlayer insulating layer and the conductive layer to expose the hard mask layer.

Here, the H2 plasma treatment is performed by adding N2 gas.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a gate oxide film 22a, a gate conductive film 22b, a gate hard mask film 22c, and a diffuse reflection film (not shown) are sequentially formed on the semiconductor substrate 21. Then, a photoresist pattern (not shown) defining a region where the gate electrode is to be formed is formed on the diffuse reflection film, and the diffuse reflection film is etched using this as an etch barrier. Here, the diffuse reflection film is formed to a thickness of 300 ~ 1500Å.

Subsequently, the gate hard mask film, the gate conductive film, and the gate oxide film are etched using the photoresist film and the diffuse reflection film as an etch barrier to form a plurality of gate electrodes 22. At this time, it can be understood that the gate conductive film 22b is a dual structure of the poly film tungsten film. Here, the gate oxide film 22a is formed to a thickness of 30 ~ 150Å, the poly film and the tungsten silicide film is formed to a thickness of 500 ~ 1500Å, 500 ~ 2000Å, respectively, in the gate conductive film 22b, the gate hard mask The film 22c is formed to have a thickness of 1500 to 4000 mm 3.

Next, a spacer nitride film 23 is formed on both side surfaces of the gate electrode 22 and the substrate.

Referring to FIG. 2B, an interlayer insulating film 24 is formed on the substrate to cover the gate electrode 22. Subsequently, heat treatment is performed to cure the interlayer insulating film 24, and then the interlayer insulating film 24 is planarized through a CMP process.

Next, a photoresist film is coated on the interlayer insulating film 24, and the photoresist film is exposed and developed to form a photoresist pattern defining a region where a landing plug contact hole is to be formed. The interlayer insulating layer 24 is etched using the photoresist pattern as an etch barrier to form a landing plug contact hole 25 exposing a plurality of gates. Subsequently, the photoresist pattern is removed through a strip process.

At this time. The interlayer insulating film 24 may be made of any one of BPSG, BSG, and PSG. Here, when depositing BPSG with the interlayer insulating film 24, boron impurities are used in an amount of 3 to 6 wt%, phosphorous impurities are used in an amount of 3 to 6 wt%, and BSG is used. According to the use, the content of boron impurities is used in an amount of 5 to 20 wt%, and the content of phosphorus impurities is used in an amount of 5 to 25 wt% by using PSG.

Referring to FIG. 2C, a landing plug contact buffer oxide layer 23b is formed on the exposed gate electrode 22 and the spacer nitride layer 23 to a thickness of 500 to 3000 kV. Here, the landing plug contact buffer oxide layer 23b is thickly deposited on the exposed gate by depositing with a material and a method having poor step-coverage characteristics, and thinly deposited on the spacer nitride layer in the inter-gate region. This is to prevent the etching of the gate hard mask layer 22c on the gate when the spacer nitride layer 23 is removed.

The spacer nitride film 23 and the landing plug contact buffer oxide film 23b in the inter-gate region are then removed by etching back to expose the substrate in the region between the gate electrodes 22.

Subsequently, a light etch treatment (LET) is performed to recover the etch damage applied to the substrate in the etch back process. At this time, the LET treatment may be used by mixing NF3 and He and O2 gas, or mixed with CF4 and O2 gas.

Referring to FIG. 2D, an H 2 plasma treatment is performed on the entire surface of the substrate to reduce the carbon component included in the interlayer insulating film 24. At this time, it is preferable to add N2 gas when forming the H2 plasma.

Here, the carbon component of the interlayer insulating film generates a large amount of etching residues in the subsequent CMP process, which penetrates between dishing areas due to the CMP process, causing pinocchio defects, which also causes bit failing. Therefore, by performing the H2 plasma treatment, the Pinocchio defect can be prevented by reducing the carbon component.

Referring to FIG. 2E, a conductive material, preferably a poly film, is embedded to fill the contact hole 25, and the contact plug 26 is formed by CMP to insulate the conductive material.

Up to this point, the present invention uses the H2 plasma treatment in order to suppress bridges, also known as Pinocchio defects, caused by the nitride film of the hard mask film and the etching residue of carbon of the poly film and the interlayer insulating film in the CMP process for forming the contact plug. By minimizing the carbon component of the interlayer insulating film, pinocchio defects can be suppressed.

As described above, according to the present invention, by reducing the carbon group of the interlayer insulating film through the H2 plasma treatment, it is possible to suppress the Pinocchio defect by reducing the etching by-products by the carbon during the subsequent CMP process.

Therefore, the reliability of an element and an element process can be ensured and a yield can be improved.

While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not limited to the embodiments described above, but in the field to which the invention pertains without departing from the spirit of the invention as claimed in the claims. Any person with ordinary knowledge will be able to make various modifications.

Claims (2)

Forming a gate electrode having a hard mask film on the semiconductor substrate; Forming a spacer nitride film on both side surfaces of the gate electrode and the semiconductor substrate; Depositing an interlayer insulating film on a substrate to cover the gate electrode; Etching the interlayer insulating film to form a landing plug contact hole that simultaneously exposes several gate electrodes and portions of the spacer nitride film between the gate electrodes; Forming a buffer oxide film on the exposed gate electrode and spacer nitride film; Removing the buffer oxide layer and the spacer nitride layer in the region between the gate electrodes to expose the substrate in the region between the gate electrodes; H2 plasma treatment to remove the carbon component in the interlayer insulating film; Depositing a conductive film on a substrate to fill the landing plug contact hole; And And CMPing the interlayer insulating film and the conductive film so that the hard mask film is exposed. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, wherein the H 2 plasma treatment is performed by adding N 2 gas.

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