KR20090026619A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20090026619A
KR20090026619A KR1020070091712A KR20070091712A KR20090026619A KR 20090026619 A KR20090026619 A KR 20090026619A KR 1020070091712 A KR1020070091712 A KR 1020070091712A KR 20070091712 A KR20070091712 A KR 20070091712A KR 20090026619 A KR20090026619 A KR 20090026619A
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KR
South Korea
Prior art keywords
region
gate
semiconductor substrate
semiconductor device
dummy
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Application number
KR1020070091712A
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Korean (ko)
Inventor
김한내
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070091712A priority Critical patent/KR20090026619A/en
Publication of KR20090026619A publication Critical patent/KR20090026619A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor device and method of manufacturing the same is provided to prevent a short circuit at a dummy area even if gate is included by forming an insulation pattern instead of a landing plug on the source and drain area at the dummy area. A semiconductor device and method of manufacturing the same is comprised of the steps: forming the gate(310) on the each region of semiconductor substrate including the cell region and dummy region; forming the oxide(350) on the semiconductor substrate of both sides of the gate formed in the dummy region; forming a landing plug(360) on the semiconductor substrate of both sides of the gate formed at a cell region. The insulation pattern is composed of an oxide film and nitride film, and the land plug and insulation pattern are formed on the source/ drain region.

Description

Semiconductor device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a semiconductor device and a method for manufacturing the same, which can prevent the occurrence of a Saft Aligned Contact (SAC) failure due to a gate tilt phenomenon.

The design-rule decreases according to the high integration of semiconductor devices, and the landing plug is applied to the cell area through a self aligned contact process (SAC) for stable electrical connection between upper and lower patterns. It forms a plug.

The landing plug is formed on the source / drain region of the semiconductor substrate and serves as a current flow path between the source / drain region and the bit line and the capacitor formed on the landing plug.

In general, a dummy region in which a dummy pattern for protecting a cell pattern is formed is disposed outside the cell region adjacent to the peripheral circuit region.

Since the dummy region is located at the boundary between the cell region and the peripheral circuit region, when the landing plug of the cell region is formed, the landing plug is also formed in the dummy region.

On the other hand, as the integration of semiconductor devices becomes higher and higher, the gap between gates becomes narrower, and the height of the gates increases further. As a result, the inclination of the gate is increasing.

This gate tilt occurs in the cell region, but especially occurs in the dummy region. As shown in FIGS. 1 and 2, the gate tilt occurs in the dummy region. It generates a short phenomenon and causes a SAC fail phenomenon.

1 and 2 illustrate SAC fail caused by a gate tilt phenomenon in a dummy region.

As described above, the SAC fail phenomenon generated in the dummy region causes the gate voltage of the cell region to drop or increase to cause the cell region to fail.

It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can prevent a SAC fail phenomenon due to an electrical short in a dummy region even when a gate tilt phenomenon occurs.

The present invention provides a semiconductor substrate including a dummy region; A gate formed on a dummy region of the semiconductor substrate; And an insulating pattern formed on the semiconductor substrate on both sides of the gate.

Here, the insulating pattern includes a nitride film or an oxide film.

In addition, the present invention includes forming a gate on each region of a semiconductor substrate including a cell region and a dummy region; Forming an insulating pattern on the semiconductor substrate on both sides of the gate formed in the dummy region; and forming a landing plug on the semiconductor substrate on both sides of the gate formed in the cell region; provides a manufacturing method of a semiconductor device .

Here, the insulating pattern may be formed of a nitride film or an oxide film.

According to the present invention, an insulating pattern other than a landing plug is formed on the source / drain regions of the dummy region, so that an electrical short can be prevented in the dummy region even when a gate tilt occurs, thereby preventing SAC fail. have.

Therefore, the present invention can prevent the gate voltage from dropping or increasing in the cell region even if the gate tilt phenomenon occurs in the dummy region, and thus, the effect of preventing the fail phenomenon of the cell region can be obtained.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention is characterized in that an insulating pattern is formed in the landing plug formation region of the dummy region.

3 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. As shown in FIG. 310 and a source / drain region 330 are formed, and a landing plug 360 is formed on the source / drain region 330 of the cell region and is insulated on the source / drain region 330 of the dummy region. Pattern 350 is formed.

Unexplained reference numeral 320 denotes a gate spacer.

As such, the present invention forms an insulating pattern 350 made of an insulating material without forming a landing plug in the landing plug forming region of the dummy region.

Accordingly, in the present invention, even if a gate leaning phenomenon occurs in the dummy region, since an insulating pattern is formed in the dummy region instead of a landing plug, an electrical short phenomenon does not occur between the gate and the landing plug. Through this, the SAC fail phenomenon can be prevented.

Therefore, the present invention does not occur a phenomenon in which the gate voltage of the cell region falls or rises, so that the fail phenomenon of the cell region can be prevented.

In detail, FIGS. 4A to 4C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4A, a gate 310 including a gate insulating layer 311, a gate conductive layer 312, and a gate hard mask layer 313 on each region of the semiconductor substrate 300 partitioned into a cell region and a dummy region. To form.

Thereafter, gate spacers 320 formed of an insulating film are formed on both sidewalls of the gate, and then impurity ions are implanted into the semiconductor substrate 300 on which the gate spacers 320 are formed. The source / drain regions 330 are formed in the semiconductor substrate 300 on both sides of the gate 310 having the ().

Referring to FIG. 4B, after the interlayer insulating layer 340 is deposited to cover the gate 310 on the semiconductor substrate 300 on which the source / drain regions 330 are formed, the interlayer insulating layer 340 is chemically mechanically polished. (Chemical Mechanical Polishing; hereinafter referred to as "CMP") to planarize.

Then, the planarized interlayer insulating film 340 is etched to form a contact hole H exposing the source / drain regions 330 of each region, and then the interlayer insulating film 340 including the contact hole H. The photoresist pattern (not shown) exposing the contact hole (H) portion of the dummy region on the () is formed.

Next, an insulating material is formed to fill the contact hole H of the dummy region. The insulating material is formed of a nitride film or an oxide film.

Subsequently, the insulating material CMP is formed to form the insulating pattern 350 in the contact hole of the dummy region until the photoresist pattern is exposed, and then the photoresist pattern is removed.

Here, the present invention does not form a landing plug made of a conductive material on the source / drain regions 330 of the dummy region, but forms an insulating pattern 350 made of an insulating material.

Referring to FIG. 4C, after the conductive material is formed on the interlayer insulating layer 340 including the insulating pattern 350 to fill the contact hole H of the cell region, the interlayer insulating layer 340 is exposed. The conductive material is CMP to form a landing plug 360 in the contact hole H of the cell region.

As described above, according to the present invention, the insulating pattern 350 is formed in the landing plug region of the dummy region, so that the SAC fail phenomenon can be prevented even when the gate tilt phenomenon occurs as the semiconductor device is highly integrated.

Therefore, the present invention can prevent the gate voltage from dropping or increasing in the cell region even if the gate tilt phenomenon occurs in the dummy region, and thus, fail of the cell region can be prevented.

Subsequently, although not shown, a series of successive known processes are sequentially performed to manufacture a semiconductor device according to an embodiment of the present invention.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 and 2 are a cross-sectional view and a plan view showing a SAC fail phenomenon according to the prior art.

3 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

4A through 4C are cross-sectional views illustrating processes of forming a landing contact plug of a semiconductor device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

300: semiconductor substrate 310: gate

320: gate spacer 330: source / drain region

340: interlayer insulating film 350: insulating pattern

360: Landing plug H: Contact hole

Claims (4)

A semiconductor substrate including a dummy region; A gate formed on the dummy region of the semiconductor substrate; And An insulating pattern formed on the semiconductor substrate on both sides of the gate; A semiconductor device comprising a. The method of claim 1, The insulating pattern is a semiconductor device, characterized in that consisting of a nitride film or an oxide film. Forming a gate on each region of the semiconductor substrate including the cell region and the dummy region; Forming an insulating pattern on the semiconductor substrate on both sides of the gate formed in the dummy region; and Forming a landing plug on the semiconductor substrate on both sides of the gate formed in the cell region; Method of manufacturing a semiconductor device comprising a. The method of claim 3, wherein The insulating pattern is a semiconductor device manufacturing method, characterized in that formed by the nitride film or oxide film.
KR1020070091712A 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same KR20090026619A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070091712A KR20090026619A (en) 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070091712A KR20090026619A (en) 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same

Publications (1)

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KR20090026619A true KR20090026619A (en) 2009-03-13

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100945510B1 (en) * 2008-03-07 2010-03-09 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
CN102386098A (en) * 2010-09-02 2012-03-21 中芯国际集成电路制造(上海)有限公司 Metal oxide semiconductor (MOS) transistor and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100945510B1 (en) * 2008-03-07 2010-03-09 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
CN102386098A (en) * 2010-09-02 2012-03-21 中芯国际集成电路制造(上海)有限公司 Metal oxide semiconductor (MOS) transistor and forming method thereof

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