KR20090026620A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
KR20090026620A
KR20090026620A KR1020070091713A KR20070091713A KR20090026620A KR 20090026620 A KR20090026620 A KR 20090026620A KR 1020070091713 A KR1020070091713 A KR 1020070091713A KR 20070091713 A KR20070091713 A KR 20070091713A KR 20090026620 A KR20090026620 A KR 20090026620A
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KR
South Korea
Prior art keywords
gate
region
forming
spacer
semiconductor substrate
Prior art date
Application number
KR1020070091713A
Other languages
Korean (ko)
Inventor
김한내
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070091713A priority Critical patent/KR20090026620A/en
Publication of KR20090026620A publication Critical patent/KR20090026620A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

 The present invention discloses a semiconductor device and a method of manufacturing the same. The present invention includes a semiconductor substrate including a dummy region, a gate formed on the dummy region of the semiconductor substrate, and spacers formed on both sidewalls of the gate, wherein the spacers are adjacent to each other. It is formed to include.

Description

Semiconductor device and method of manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method, and more particularly, to a semiconductor device and a method for manufacturing the same, which can prevent the occurrence of a Saft Aligned Contact (SAC) failure due to a gate tilt phenomenon.

The design-rule decreases according to the high integration of semiconductor devices, and the landing plug is applied to the cell area through a self aligned contact process (SAC) for stable electrical connection between upper and lower patterns. It forms a plug.

The landing plug is formed on the source / drain region of the semiconductor substrate and serves as a current flow path between the source / drain region and the bit line and the capacitor formed on the landing plug.

In general, a dummy region in which a dummy pattern for protecting a cell pattern is formed is disposed outside the cell region adjacent to the peripheral circuit region.

Since the dummy region is located at the boundary between the cell region and the peripheral circuit region, when the landing plug of the cell region is formed, the landing plug is also formed in the dummy region.

On the other hand, as the integration of semiconductor devices becomes higher and higher, the gap between gates becomes narrower, and the height of the gates increases further. As a result, the inclination of the gate is increasing.

The gate tilt occurs in the cell region, but especially in the dummy region. The gate tilt occurs in the dummy region, which causes an electrical short between the landing plug and the gate, which causes a SAC fail. Let's do it.

As described above, the SAC fail phenomenon occurring in the dummy region causes the gate voltage of the cell region to drop or increase to cause the cell region to fail.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can prevent a SAC fail even when a gate tilt occurs in a dummy region.

The present invention provides a semiconductor substrate including a dummy region; A gate formed on the dummy region of the semiconductor substrate; And spacers formed on both sidewalls of the gate, wherein the spacers are formed such that spacers formed adjacent to each other are formed to be in contact with each other.

In addition, the present invention includes forming a gate on each region of a semiconductor substrate including a cell region and a dummy region; Forming spacers on both side walls of the gate of each region; Forming an interlayer insulating film on the semiconductor substrate on which the spacer is formed; Etching the interlayer insulating layer to form contact holes exposing portions of the semiconductor substrate on both sides of the gate formed in the cell region; And forming a landing plug in the contact hole of the cell region.

Here, the spacers of the dummy region may include forming spacers formed to be in contact with each other.

After forming the contact hole, and before forming a landing plug in the contact hole of the cell region, further comprising forming additional spacers on both side walls of the contact hole.

The spacer includes forming a USG film containing boron.

The present invention does not form a landing plug by thickly forming a gate spacer in the dummy region, and thus there is no landing plug that may make the gate electrically contact even when a gate tilt occurs, thereby preventing SAC fail. can do.

Therefore, the present invention can prevent the gate voltage from dropping or increasing in the cell region even if the gate tilt phenomenon occurs in the dummy region, and thus, the effect of preventing the fail phenomenon of the cell region can be obtained.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, the thickness of the spacer is maximally formed in the dummy area so that a space for the landing plug is formed in the dummy area.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention. As shown in the drawing, a spacer 120 is formed on a dummy area of a semiconductor substrate 100 including a dummy area. The provided gate 110 and the source / drain region 130 are formed. The gate spacers 120 formed in the dummy region are formed to have a maximum thickness so that the spacers formed adjacent to each other contact each other.

Unexplained reference numeral 140 denotes an interlayer insulating film, respectively.

As such, the present invention does not secure a space in which the landing plug is formed in the dummy region by forming the gate spacer 120 thickly in the dummy region.

Therefore, in the present invention, even when a gate leaning phenomenon occurs in the dummy region, since a landing plug is not formed in the dummy region, an electrical short between the gate and the landing plug does not occur in the dummy region. Through this, the SAC fail phenomenon can be prevented.

Therefore, the present invention does not cause the gate voltage of the cell region to drop or rise even when the gate tilt phenomenon occurs in the dummy region, and thus the fail phenomenon of the cell region can be prevented.

2A to 2C are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention, which will be described below with reference to the drawings.

Referring to FIG. 2A, a gate 110 including a gate insulating layer 111, a gate conductive layer 112, and a gate hard mask layer 113 on each region of the semiconductor substrate 100 partitioned into a cell region and a dummy region. To form.

Then, an insulating film for a spacer is deposited on the semiconductor substrate 100 including the gate 110 of each region. When depositing the insulating film for the spacer, a thick film is deposited on the dummy region.

Next, the spacer insulating layer is etched to form spacers 120 on both walls of the gate 110 in each region.

In this case, since a spacer insulating film is thickly deposited in the dummy region, the spacers 120 formed in the dummy region are formed to be in contact with each other.

Subsequently, impurity ions are implanted into the semiconductor substrate 100 on which the spacers 120 are formed to form source / drain regions 130 in the semiconductor substrate 100 on both sides of the gate 110 on which the spacers 120 are formed. .

Referring to FIG. 2B, after the interlayer insulating layer 140 is deposited on the semiconductor substrate 100 on which the source / drain regions 130 are formed to cover the gate 110, the interlayer insulating layer 140 is chemically mechanically polished. (Chemical Mechanical Polishing; hereinafter referred to as "CMP") to planarize.

Next, the planarized interlayer insulating layer 140 is etched to form a contact hole H exposing the source / drain regions 130 of the cell region. In this case, a contact hole is not formed in the dummy region due to the gate spacer 120 formed thickly.

Referring to FIG. 2C, an insulating layer for an additional spacer is formed on the interlayer insulating layer 140 on which the contact hole H is formed, and then the insulating layer is etched to etch the insulating layer. H) Form additional spacers 121 on both walls.

Thereafter, a conductive material is deposited on the interlayer insulating layer 140 so that the contact hole H where the spacer 121 is formed is filled, and then CMP the conductive material until the interlayer insulating layer 140 is exposed. The landing plug 150 is formed in the contact hole H of the cell region.

As described above, the present invention does not form the landing plug by forming the spacer 120 thickly in the dummy region, so that even if the gate tilt occurs, the gate and the landing plug are electrically shorted in the dummy region. Since this does not occur, it can prevent the SAC fail phenomenon.

Therefore, the present invention can prevent the gate voltage from dropping or increasing in the cell region even if the gate tilt phenomenon occurs in the dummy region, and thus, fail of the cell region can be prevented.

Subsequently, although not shown, a series of successive known processes are sequentially performed to manufacture a semiconductor device according to an embodiment of the present invention.

Hereinbefore, the present invention has been illustrated and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications and variations can be made.

1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

2A through 2C are cross-sectional views illustrating processes of forming a landing contact plug of a semiconductor device according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate 101: device isolation film

110: gate 111: gate insulating film

112: gate conductive film 113: gate hard mask film

120: gate spacer 130: source / drain region

140: interlayer insulating film 150: landing plug

H: contact hole

Claims (5)

A semiconductor substrate including a dummy region; A gate formed on the dummy region of the semiconductor substrate; And spacers formed on both sidewalls of the gate. The spacer is a semiconductor device, characterized in that the spacer formed adjacent to each other is formed so as to contact each other. Forming a gate on each region of the semiconductor substrate including the cell region and the dummy region; Forming spacers on both side walls of the gate of each region; Forming an interlayer insulating film on the semiconductor substrate on which the spacer is formed; Etching the interlayer insulating layer to form contact holes exposing portions of the semiconductor substrate on both sides of the gate formed in the cell region; And Forming a landing plug in the contact hole of the cell region; Method of manufacturing a semiconductor device comprising a. The method of claim 2, The spacer of the dummy region is formed so that the spacers formed adjacent to each other are in contact with each other. The method of claim 3, wherein And forming additional spacers on both side walls of the contact hole after the forming of the contact hole and before forming the landing plug in the contact hole of the cell region. The method of claim 4, wherein The spacer is a method of manufacturing a semiconductor device, characterized in that formed by the USG film containing boron.
KR1020070091713A 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same KR20090026620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070091713A KR20090026620A (en) 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070091713A KR20090026620A (en) 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
KR20090026620A true KR20090026620A (en) 2009-03-13

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KR1020070091713A KR20090026620A (en) 2007-09-10 2007-09-10 Semiconductor device and method of manufacturing the same

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386098A (en) * 2010-09-02 2012-03-21 中芯国际集成电路制造(上海)有限公司 Metal oxide semiconductor (MOS) transistor and forming method thereof
KR20160141052A (en) * 2015-05-27 2016-12-08 삼성전자주식회사 Method for manufacturing the Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102386098A (en) * 2010-09-02 2012-03-21 中芯国际集成电路制造(上海)有限公司 Metal oxide semiconductor (MOS) transistor and forming method thereof
KR20160141052A (en) * 2015-05-27 2016-12-08 삼성전자주식회사 Method for manufacturing the Semiconductor device

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