KR20070055880A - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can reduce the contact resistance of the material for filling the contact hole without increasing the DICD when forming the contact hole of the semiconductor device, the present invention is a substrate on which the first conductive film is formed Providing an insulating film, forming an insulating film on the first conductive film, etching the insulating film so that an upper portion of the first conductive film is recessed to a predetermined depth, and between the insulating film and the first conductive film. Performing an isotropic etching process using an etching selectivity to form a contact groove in the first conductive layer to have a width wider than the pattern width of the insulating layer, and forming a second conductive layer to fill the contact groove. It provides a method for manufacturing a semiconductor device comprising.

Bit line, contact resistance, contact hole, contact area, DICD.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a plan view illustrating a general DRAM cell.

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

   <Explanation of symbols for the main parts of the drawings>

10: substrate

11: gate insulating film

12: polysilicon film

13: tungsten silicide film

14: hard mask

15: wordline

16: gate spacer

17: first interlayer insulating film

18: landing plug

19: second interlayer insulating film

20: photoresist pattern

21: etching process

22: contact hole

23: nitride film

23a: contact hole spacer

24: etch back

25: Contact Home

25a: Bitline contact hole

26: bit line

27: hard mask pattern

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a DRAM cell.

1 is a plan view illustrating a general DRAM cell.

As shown in FIG. 1, a DRAM cell generally includes a transistor and a capacitor connected to a bit line (BL) and a word line, respectively. At this time, the source / drain of the transistor should be electrically connected to the bit line and the capacitor, respectively.

As such, a bit line contact is required to connect a source (or a drain) to a bit line, and a storage contact is connected to a storage node, which is a lower electrode of the capacitor, to connect a drain (or source) to a capacitor. This is necessary.

1, 'BC' represents a bit line contact hole for forming a bit line contact, 'SC' represents a storage contact hole for forming a storage contact, and 'A' represents an active region. Indicates.

On the other hand, in the DRAM cell, in order to lower the contact resistance, the contact area with the landing plug at the bottom of the bit line must be secured. Therefore, when forming the bit line contact hole BC, the bit line contact hole BC is formed. It is very important to secure the Bottom CD.

However, when the development inspection CD (DICD) is increased to secure the bottom area of the bit line contact hole BC, the top area of the bit line contact hole BC is also increased. As a result, an overlap-margin with the storage contact hole SC formed through a subsequent process is reduced, so that a bridge (B) area between the bit line contact hole BC and the storage contact hole SC is reduced. Will occur).

In addition, when the BOE (Buffered Oxide Etchant) solution is used during the cleaning process performed after the formation of the bit line contact hole BC, the top area of the bit line contact hole BC is further increased to further increase the probability of bridging. Done. In addition, even when the bottom area of the bit line contact hole BC continues to increase, the probability of damaging the hard mask as the overlap with the gate electrode hard mask at the bottom of the bit line contact hole BC increases. This further increases.

The present invention has been made to solve the above problems, to provide a method for manufacturing a semiconductor device that can reduce the contact resistance of the material to fill the contact hole without increasing the DICD when forming the contact hole of the semiconductor device have.

According to an aspect of the present invention for achieving the above object, providing a substrate with a first conductive film, forming an insulating film on the first conductive film, the upper portion of the first conductive film is a predetermined depth Etching the insulating layer so as to be recessed, and performing an isotropic etching process using an etching selectivity ratio between the insulating layer and the first conductive layer to contact the inside of the first conductive layer to have a width wider than the pattern width of the insulating layer. And forming a groove and forming a second conductive layer to fill the contact groove.

In addition, according to another aspect of the present invention for achieving the above object, providing a substrate having a plurality of conductive pattern layer, forming a contact plug between the conductive pattern layer, and comprises the contact plug Forming an insulating film on the entire structure, etching the insulating film so that the upper portion of the contact plug is recessed to a predetermined depth, and performing an isotropic etching process using an etching selectivity between the insulating film and the contact plug. And forming a contact groove in the contact plug to have a width wider than the pattern width of the insulating layer, and forming a metal wiring to fill the contact groove.

In addition, according to another aspect of the present invention for achieving the above object, providing a substrate having a word line formed, forming a landing plug between the word line, and the overall structure including the landing plug Forming an insulating film on the upper surface, etching the insulating film so that the upper portion of the landing plug is recessed to a predetermined depth, and performing an isotropic etching process using an etching selectivity between the insulating film and the landing plug. A method of manufacturing a semiconductor device includes forming a contact groove in the landing plug to have a width wider than a pattern width, and forming a bit line to fill the contact groove.

In the present invention, the isotropic etching process uses an etching gas having a higher etching selectivity with respect to the first conductive film (or the contact plug or the landing plug) than the insulating film, preferably using Cl ₂ or HBr gas. Do.

In addition, in the present invention, the contact groove is formed in the shape of a bulb.

The method may further include forming a spacer on an inner wall of the insulating layer after the insulating layer is etched so that the insulating layer is not etched during the isotropic etching process, wherein the spacer is a nitride-based material. It is desirable to form

According to the present invention described above, after etching the insulating film so that the conductive film is recessed to a predetermined depth in the insulating film formed on the conductive film, the pattern width of the insulating film in the conductive film through a chemical isotropic etching process using the etching selectivity between the insulating film and the conductive film By forming a contact groove with a wider width, a contact hole whose upper width is narrower than the bottom width can be formed without increasing the DICD. Thus, the contact resistance of the material filling the contact hole can be reduced without increasing the DICD.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 2A to 8A are cross-sectional views of the process of applying the embodiment of the present invention by cutting in the bit line BL direction shown in FIG. 1, and FIGS. 2 to 8B are bits. FIG. 7 is a cross-sectional view illustrating a process in which the embodiment of the present invention is applied by cutting in a word line direction perpendicular to the line BL.

First, as shown in FIG. 2, a semiconductor substrate 10 having a pretreatment cleaning process and an ion implantation process for adjusting a threshold voltage is provided. Here, the pretreatment washing process is performed with DHF (Diluted HF) and then SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or BOE (Buffer Oxide Etchant) and then SC-1. It may be performed sequentially.

Subsequently, a word line gate electrode 15 (hereinafter referred to as a word line) having a hard mask 14 on the top and gate spacers 16 on both sidewalls is formed on the substrate 10. For example, the gate insulating film 11, the polysilicon film 12, the tungsten silicide films 13 and WSi ₂ , and the hard mask 14 are sequentially formed on the substrate 10, and then formed through a photo process. The hard mask 14 is etched using a mask pattern (not shown). Then, the tungsten silicide layer 13, the polysilicon layer 12, and the gate insulating layer 11 are sequentially etched using the etched hard mask 14 to form a word line having the hard mask 14 thereon. 15).

Here, the gate spacers 16 are formed in accordance with known spacer formation techniques.

Subsequently, an interlayer insulating layer 17 (hereinafter, referred to as a first interlayer insulating layer) is formed on the substrate 10 including the word line 15. The first interlayer insulating film 17 is formed of an oxide film-based material. For example, the first interlayer insulating layer 17 may include an HDP (High Density Plasma) oxide film, a Boron Phosphorus Silicate Glass (BPSG) film, a Phosphorus Silicate Glass (PSG) film, a Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS) film, and Plasma Enhanced PECVD. Single layer film or lamination thereof using any one of Chemical Vapor Deposition (USG) film, USG (Un-doped Silicate Glass) film, Fluorinated Silicate Glass (FSG) film, Carbon Doped Oxide (CDO) film and Organic Silicate Glass (OSG) film It is formed into a laminated film.

Subsequently, a part of the first interlayer insulating film 17 is etched by performing a mask process and an etching process. Preferably, a portion of the first interlayer insulating layer 17 is etched to expose the substrate 10 between some word lines 15.

Next, a landing plug 18 is formed between the first interlayer insulating layer 17 to cover the exposed substrate 10. For example, the landing plug 18 is formed by depositing a polysilicon film as a conductive material.

Next, a chemical mechanical polishing (CMP) process is performed to planarize the first interlayer insulating layer 17 and the landing plug 18 until the upper portion of the word line 15 is exposed.

Subsequently, an interlayer insulating film 19 (hereinafter referred to as a second interlayer insulating film) is deposited over the entire structure including the landing plug 18. Here, the second interlayer insulating film 19 is formed of the same material as the first interlayer insulating film 17.

Subsequently, the photoresist pattern 20 is formed on the second interlayer insulating film 19 by performing a photo process. Here, the photoresist pattern 20 is to define a region where the bit line contact hole is to be formed, and has a structure that exposes a part of the region corresponding to the landing plug 18.

In particular, the photoresist pattern 20 may be formed by applying a reflow process to reduce the DICD of the photo process for forming the bit line contact holes.

Subsequently, as shown in FIG. 3, the second interlayer insulating layer may be etched using the photoresist pattern 20 as an etching mask so that the landing plug 18 is recessed to a predetermined depth. Etch (19). As a result, a contact hole 22 exposing a part of the landing plug 18 is formed in the second interlayer insulating layer 19.

Subsequently, as shown in FIG. 4, a strip process is performed to remove the photoresist pattern 20 (see FIG. 3). As a result, the second interlayer insulating layer 19 including the contact hole 22 is exposed.

Subsequently, as illustrated in FIG. 5, a nitride film-based material 23 (hereinafter, referred to as a nitride film) for forming a spacer along a step above the second interlayer insulating film 19 including the contact holes 22 (see FIG. 4). Deposit. Preferably, Si ₃ N ₄ is deposited which has excellent step coverage.

Next, as illustrated in FIG. 6, a dry etching process such as an etch-back 24 is performed to etch the nitride film 23 (see FIG. 5) to form an inner wall of the contact hole 22 (see FIG. 4). Contact hole spacers 23a are respectively formed in the grooves. Here, the contact hole spacers 23a are formed to prevent the second interlayer insulating layer 19 from being etched during the subsequent isotropic etching process.

Subsequently, as shown in FIG. 7, the bottom of the contact hole 22 (refer to FIG. 4) may be formed by performing an isotropic etching process, such as chemical dry etching (CDE), which gives no direction to the radical. The landing plug 18 is etched. Accordingly, in the landing plug 18 at the bottom of the contact hole 22, the light bulb Bulb may have a width W _{2 that} is wider than the width W ₁ of the contact hole 22, that is, the width between the second interlayer insulating layers 19. The contact groove 25 of the shape is formed.

In particular, in the chemically isotropic etching process, an etching gas having a high etching selectivity relative to the landing plug 18 is used, for example, Cl ₂ or HBr gas, compared to the second interlayer insulating film 19. That is, the landing plug 18 is etched by using a polysilicon film at the bottom of the contact hole 22 by applying an isotropic etching process using Cl ₂ or HBr gas having a higher etching selectivity to the polysilicon film than the oxide film. The bulbous contact grooves 25 are formed in 18. As a result, the bit line contact hole 25a having the upper width W ₁ smaller than the bottom width W ₂ is formed.

Accordingly, the contact resistance of the bit line may be reduced by increasing only the bottom area of the bit line contact hole 25a without increasing the DICD when forming the bit line contact hole 25a.

As a result, by selectively increasing only the width of the bottom portion while maintaining the upper width of the bit line contact hole 25a, the bit line contact hole 25a when the DICD is increased to reduce the contact resistance of the bit line as described above. As the upper width of the N) increases, the contact resistance of the bit line can be reduced while suppressing the occurrence of the bridge.

Subsequently, as illustrated in FIG. 8, the conductive material for the bit line is deposited on the second interlayer insulating layer so that the bit line contact hole 25a is filled, and then a mask process and an etching process are performed to form a predetermined hard mask pattern ( 27).

Subsequently, the bit line conductive material is etched using the hard mask pattern 27 to form the bit line 26 to fill the bit line contact holes 25a (see FIG. 7).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the insulating film is etched so that the conductive film is recessed to a predetermined depth in the insulating film formed on the conductive film, and then the chemically isotropic etching process using the etching selectivity between the insulating film and the conductive film is performed in the conductive film. By forming the contact grooves having a width wider than the pattern width of the insulating layer, a contact hole having an upper width smaller than the bottom width can be formed without increasing the development inspeciton CD (DICD).

Therefore, by selectively increasing only the bottom area of the contact hole, as the upper area is increased, the contact resistance of the material filling the contact hole may be reduced while suppressing bridges that may occur between neighboring contact holes.

Claims (18)

Providing a substrate on which a first conductive film is formed; Forming an insulating film on the first conductive film; Etching the insulating layer to recess the upper portion of the first conductive layer to a predetermined depth; Forming a contact groove in the first conductive layer to have a width wider than the pattern width of the insulating layer by performing an isotropic etching process using an etching selectivity between the insulating layer and the first conductive layer; And Forming a second conductive layer to fill the contact grooves Semiconductor device manufacturing method comprising a. The method of claim 1, The isotropic etching process uses an etching gas having an etching selectivity higher than that of the insulating layer with respect to the first conductive layer. The method of claim 2, The circular etching process is a semiconductor device manufacturing method using Cl ₂ or HBr gas. The method according to any one of claims 1 to 3, The contact groove is a semiconductor device manufacturing method to form a bulb shape. The method according to any one of claims 1 to 3, wherein after etching the insulating film, And forming a spacer on an inner wall of the insulating layer so that the insulating layer is not etched during the isotropic etching process. The method of claim 5, The spacer is a semiconductor device manufacturing method of forming a nitride film-based material. Providing a substrate on which a plurality of conductive pattern layers are formed; Forming a contact plug between the conductive pattern layers; Forming an insulating film on the entire structure including the contact plug; Etching the insulating film so that an upper portion of the contact plug is recessed to a predetermined depth; Forming a contact groove in the contact plug to have a width wider than the pattern width of the insulating film by performing an isotropic etching process using an etching selectivity between the insulating film and the contact plug; And Forming a metal wiring to fill the contact groove Semiconductor device manufacturing method comprising a. The method of claim 7, wherein The isotropic etching process is a semiconductor device manufacturing method using an etching gas having a higher etching selectivity for the contact plug than the insulating film. The method of claim 8, The circular etching process is a semiconductor device manufacturing method using Cl ₂ or HBr gas. The method according to any one of claims 7 to 9, The contact groove is a semiconductor device manufacturing method to form a bulb shape. The method according to any one of claims 7 to 9, wherein after etching the insulating film, And forming a spacer on an inner wall of the insulating layer so that the insulating layer is not etched during the isotropic etching process. The method of claim 11, The spacer is a semiconductor device manufacturing method of forming a nitride film-based material. Providing a substrate having a word line formed thereon; Forming a landing plug between the word lines; Forming an insulating film on the entire structure including the landing plug; Etching the insulating film so that an upper portion of the landing plug is recessed to a predetermined depth; Forming a contact groove in the landing plug to have a width wider than a pattern width of the insulating film by performing an isotropic etching process using an etching selectivity between the insulating film and the landing plug; And Forming a bit line to fill the contact groove Semiconductor device manufacturing method comprising a. The method of claim 13, The isotropic etching process uses an etching gas having an etching selectivity higher than that of the insulating film for the landing plug. The method of claim 14, The circular etching process is a semiconductor device manufacturing method using Cl ₂ or HBr gas. The method according to any one of claims 13 to 15, The contact groove is a semiconductor device manufacturing method to form a bulb shape. The method of claim 13, wherein after etching the insulating film, And forming a spacer on an inner wall of the insulating layer so that the insulating layer is not etched during the isotropic etching process. The method of claim 17, The spacer is a semiconductor device manufacturing method of forming a nitride film-based material.

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