KR20060131144A - Method for forming contact plug in semiconductor device - Google Patents

Abstract

A method for forming a contact plug in a semiconductor device is provided to perform stably a post-etch process by forming uniformly an etch-stop layer on a cell region and a peripheral region. A contact hole is formed by performing an etch process using a hard mask(115) on a first and second regions having different pattern density. The thickness of the hard mask on the first region is different from the thickness of the hard mask on the second region. A substrate(110) including the first and second regions is provided. A contact plug(119) is deposited to bury the contact hole by using a material different from the insulating layer. The contact plug is etched and the hard mask is removed. The insulating layer is recessed selectively by performing an etch process using etch selectivity.

Description

TECHNICAL FOR FORMING CONTACT PLUG IN SEMICONDUCTOR DEVICE

1A to 1E are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the related art.

Figure 2 is a SEM (Scanning Electron Microscope) photo of a semiconductor device manufactured by a method for forming a contact plug of a semiconductor device according to the prior art.

3A to 3H are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10, 110: semiconductor substrate 11, 111: first interlayer insulating film

12, 112: lower plug 13, 113: second interlayer insulating film

14, 114: bit lines 15, 115: hard mask

16, 116: third interlayer insulating film 17, 117: hard mask

17a, 117a: hard mask pattern 18, 118: contact hole

19: spacer 20, 119: storage node contact plug

122: etching stop film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact plug of a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device to which a hard mask scheme is applied.

Recently, more sophisticated process control is required in the manufacturing process of semiconductor devices due to the reduction of design rules due to the higher integration of semiconductor devices. In particular, in the case of DRAM, at 0.115 μm or less, between an upper wiring line and a bit line, between a landing plug formed under the upper wiring line and the bit line, or an active region (eg, a source or drain region) of a substrate. There is a growing interest in the process of forming a storage node contact plug for connecting between the capacitor and the capacitor.

In the DRAM node forming process, a hard mask scheme is used to secure an etching process margin as the integration degree of a semiconductor device increases. The hard mask scheme is a process of using a hard mask instead of a photoresist as an etching mask, and typically a hard silicon is used as the poly mask.

Hereinafter, a method of forming a storage contact plug of a semiconductor device using a hard mask scheme according to the related art and a problem thereof will be described with reference to FIGS. 1A to 1E.

First, as shown in FIG. 1A, the first interlayer insulating layer 11 is deposited on the semiconductor substrate 10, and then etched to form a landing plug 12 with a polysilicon film therein. Subsequently, a second interlayer insulating layer 13 is formed on the entire structure including the landing plug 12. Then, after forming the bit line 14 and the hard mask 15 on the second interlayer insulating film 13, spacers (not shown) are formed on both side walls of these (14, 15). Subsequently, a third interlayer insulating layer 16 is formed on the entire structure to cover the semiconductor structure layer including the spacer. Then, a hard mask 17 is deposited on the third interlayer insulating film 16 with a polysilicon film.

Subsequently, as shown in FIG. 1B, a mask process is performed on the hard mask 17 (see FIG. 1A) to form a photoresist pattern (not shown), followed by an etching process using the photoresist pattern as an etching mask. The hard mask 17 is etched. As a result, the hard mask pattern 17a is formed. Then, the strip process is performed to remove the photoresist pattern, and then the third and second interlayer insulating layers 16 and 13 are etched by performing an etching process using the hard mask pattern 17a as an etching mask. As a result, a contact hole 18 through which the landing plug 12 is exposed is formed. Then, a cleaning process is performed to remove residues generated during the process of forming the contact hole 18 and remaining on the inner wall and the bottom of the contact hole 18.

Subsequently, as shown in FIGS. 1C and 1D, a spacer 19 is formed of a nitride film on the inner wall of the contact hole 18 (see FIG. 1B). Then, the polysilicon layer 20 for the storage node contact plug is deposited on the entire structure to fill the contact hole 18. Thereafter, the entire surface etching process such as plasma etch back is performed to planarize the polysilicon layer 20. As a result, an isolated storage node contact plug 20 is formed in the contact hole 18.

However, in the method of forming a contact plug according to the related art, the cell region A adjacent to the peripheral circuit region based on the interface between the cell region and the peripheral circuit region during the etching and cleaning of the contact hole 18 performed in FIG. In addition, the hard mask pattern 17a formed in the peripheral circuit region B adjacent to the cell region exhibits a large difference (approximately 200 s to 600 s) from each other in thickness. That is, as shown in FIG. 1B, the hard mask pattern 17a formed in the cell region A is etched more than the hard mask pattern 17a formed in the peripheral circuit region B, thereby remaining thin. This is due to the pattern density difference between the cell region A and the peripheral circuit region B, because the cell region A has a higher pattern density than the peripheral circuit region B.

The difference in thickness of the hard mask pattern 17a remaining in the two regions A and B is maintained during the subsequent process, and as a result, as shown in FIG. 1D, the etching target during the removal process of the hard mask pattern 17a is performed. When the target is aligned with the removal of the hard mask pattern 17a formed in the peripheral circuit region B, the storage node contact plug 20 is excessively lost in the cell region A. FIG. Accordingly, as shown in FIG. 1E, an etch stop layer 21 for forming subsequent storage nodes is further deposited inside the contact hole 18 (see FIG. 1B). That is, as illustrated in FIG. 1E, the deposition thickness T1 of the region where the contact hole 18 is formed is thicker than the deposition thickness T2 of the peripheral circuit region B. As a result, a plurality of interlayer insulating films are deposited in a subsequent process, and an etching margin due to an increase in etching depth is reduced during the etching process for forming the storage node pattern, so that the contact hole for the storage node is not opened as shown in FIG. 2. Does not cause problems.

Accordingly, the present invention has been proposed to solve the above problems of the prior art, the thickness of the hard mask remaining between the cell region and the peripheral circuit region after forming the contact hole in the process of forming a contact plug of a semiconductor device using a hard mask scheme. After the deposition of a plurality of interlayer insulating films to be deposited and the subsequent poor deposition of the storage node contact plug caused by the difference, and then to reduce the etching margins due to the increase in the etching depth during the etching process to form the storage node pattern It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device capable of preventing a deep contact failure.

In accordance with an aspect of the present invention, a contact hole in which a lower conductive layer is exposed in an insulating layer is formed by performing an etching process using a hard mask on first and second regions having different pattern densities. Forming a substrate having the hard mask remaining on the first and second regions with different thicknesses, depositing a contact plug with a different material from the insulating layer to fill the contact hole; Selectively removing the hard mask to etch the contact plug so as to be isolated inside the contact hole, and performing an etching process using an etching selectivity with the contact plug to selectively form the insulating layer to have the same height as the contact plug. It provides a method for forming a contact plug of a semiconductor device comprising the step of recessing.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

3A to 3G are cross-sectional views illustrating a method of forming a contact plug of a DRAM device in order to explain a method of forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention. Here, the region 'A' represents a cell region adjacent to the peripheral circuit region, and the region 'B' represents a peripheral circuit region adjacent to the cell region.

First, as shown in FIG. 3A, a first interlayer insulating layer 111 is deposited on the semiconductor substrate 110. In this case, the first interlayer insulating layer 111 is formed of an oxide-based material. For example, HDP (High Density Plasma) oxide film, BPSG (Boron Phosphorus Silicate Glass) film, PSG (Phosphorus Silicate Glass) film, PETEOS (Plasma Enhanced Tetra Ethyle Ortho Silicate) film, USG (Un-doped Silicate Glass) film, FSG (FSG) film It is formed from a single layer film made of any one of a fluorinated Silicate glass (CDO) film, a carbon doped oxide (CDO) film, and an organosilicate glass (OSG) film, or they are formed as a laminated film in which at least two or more layers are laminated.

Subsequently, the landing plug 112 using the polysilicon film is used as the lower conductive layer so as to be connected to the active region of the semiconductor substrate 110 inside the first interlayer insulating film 111 by performing a mask process, an etching process, a deposition process, and a planarization process. Form. In this case, the landing plug 112 is electrically connected to a junction region formed in the substrate 110, for example, a source and a drain region.

Subsequently, a second interlayer insulating layer 113 is deposited on the entire structure including the landing plug 112. In this case, the second interlayer insulating layer 113 is formed of the same material as the first interlayer insulating layer 111. However, in the thickness, it can adjust suitably according to a design rule.

Subsequently, the second interlayer insulating film 113 may be planarized by performing a chemical mechanical polishing (CMP) process.

Subsequently, a bit line 114 and a hard mask 115 are formed on the second interlayer insulating layer 113. At this time, the bit line 114 is formed of, for example, a polysilicon film and a metal layer or a polysilicon film and a metal silicide layer. Here, the metal layer is tungsten, and the metal silicide layer is a tungsten silicide layer. Meanwhile, the hard mask 115 is formed of a nitride film-based material.

Subsequently, spacers (not shown) may be formed on both sidewalls of the hard mask 115 and the conductive layer 114. In this case, the spacer may be formed of a nitride film or an oxide film-based material.

A third interlayer insulating film 116 is then deposited over the entire structure to cover the resulting product including the spacers. In this case, the third interlayer insulating layer 116 is formed of the same material as the first interlayer insulating layer 111. However, in the thickness, it can adjust suitably according to a design rule.

Subsequently, the CMP process may be performed to planarize the third interlayer insulating layer 116.

Subsequently, a hard mask 117 is deposited on the planarized third interlayer insulating layer 116. In this case, the hard mask 117 is formed of a material having a relatively high etching selectivity with respect to the oxide film constituting the third interlayer insulating film 116, but preferably a polysilicon film. In addition, the hard mask 117 may be formed of tungsten (W) in consideration of an etching selectivity with a subsequent storage node contact plug 119 (see FIG. 3C). When the storage node contact plug 119 is formed of a polysilicon film of the same material as the hard mask 117, the storage node contact plug 119 exposed during the hard mask pattern 117a (see FIG. 3B) is removed. This is because the loss of. In order to prevent this, the hard mask 117 may be formed of a material different from that of the storage node contact plug 119.

Subsequently, as shown in FIG. 3B, a photoresist pattern (not shown) is formed on the hard mask 117, and then the hard mask 117 is etched by performing an etching process using the photoresist pattern. As a result, the hard mask pattern 117a on which the third interlayer insulating layer 116 is exposed is formed.

Subsequently, after the strip process is performed to remove the photoresist pattern, an etching process using the hard mask pattern 117a as an etching mask is performed to etch the third interlayer insulating layer 116 and the second interlayer insulating layer 113. As a result, a contact hole 118 through which a part of the landing plug 112 is exposed is formed.

Subsequently, in order to remove residues such as polymers generated during the formation of the contact hole 118 and remain on the inner wall and the bottom of the contact hole 118, buffered oxide etchant (HF) or BOE (Buffered Oxide Etchant, HF). And NH ₄ F mixed solution) is carried out using a solution.

Meanwhile, the hard mask pattern 117a is recessed to some extent by the photoresist pattern strip process, the etching process for forming the contact hole 118 and the subsequent cleaning process which are not described. Is done. At this time, the degree of recess is different between the cell region A and the peripheral circuit region B. In the cell region A having a high pattern density, the recess degree is larger than the peripheral circuit region B. . That is, 'T2> T1'.

Subsequently, as shown in FIG. 3C, a spacer (not shown) may be formed on the inner wall of the contact hole 118. In this case, the spacer is formed of a nitride film-based material such as a SiN film. Here, the spacer is misaligned due to the limitation of the mask process during the formation of the contact hole 118 (refer to FIG. 2B). As a result, the bit line 114 is exposed to the contact hole 118. ) And the storage node contact plug 119 are prevented from being electrically connected.

Subsequently, the storage node contact plug 119 is deposited to fill the contact hole 118. In this case, the storage node contact plug 119 may be formed of a material having a high etching selectivity with respect to an oxide film constituting the third interlayer insulating layer 116, for example, a polysilicon film.

3D and 3E, the plasma etchback process 120 is performed to isolate the storage node contact plug 119 inside the contact hole 118 (see FIG. 3B). In this case, the plasma etch back process 120 increases the etching selectivity with the third interlayer insulating layer 116 to selectively remove only the hard mask pattern 117a. For example, only the polysilicon film is selectively removed in consideration of the etching selectivity between the polysilicon film oxide films.

Meanwhile, as described above, the hard mask 117 is formed of tungsten in order to minimize the loss of the storage node contact plug 119 during the plasma etchback process 120. In this case, the plasma etchback process 120 may be tungsten. In consideration of the etching selectivity between the oxide and the oxide film, only tungsten is selectively removed within a range of minimizing the loss of the oxide film.

Subsequently, as illustrated in FIG. 3F, an etching process 121 is performed to selectively recess the third interlayer insulating layer 116. In this case, the etching process 121 is performed until the same height as the upper height of the third interlayer insulating layer 116 and the storage node contact plug 119. The etching process 121 may be performed by a wet etching process or a dry etching process in consideration of an etching selectivity between the storage node contact plug 119 and the third interlayer insulating layer 116. The etching process 121 may be performed using the storage node contact plug 119 as an etch stop layer.

Next, as illustrated in FIG. 3G, an etch stop layer 122 is deposited to cover the third interlayer insulating layer 116 and the storage node contact plug 119. The etch stop layer 122 has the same height in the cell region A and the peripheral circuit region B because the third interlayer insulating layer 116 and the storage node contact plug 119 are already flattened to the same height in FIG. 3F. Is deposited. That is, 'T3 = T4 = T5'.

Subsequently, although not shown, a plurality of fourth interlayer insulating layers are deposited on the etch stop layer 122 and then etched to form contact holes for storage nodes in which the storage nodes are formed.

The subsequent process is a general process to form a storage node, a dielectric film and an upper electrode to complete the capacitor.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the process of forming a contact plug of a semiconductor device using a hard mask scheme, after forming a contact hole for a storage node contact plug using a hard mask, a plasma etch back process is performed to perform the contact. By forming an isolated storage node contact plug inside the hole, the hard mask is removed, and then the interlayer insulating film is selectively etched to recess and planarize the interlayer insulating film to the same height as the storage node contact plug to planarize. Since it is evenly deposited on the cell region and the peripheral circuit region, an etching process for depositing a plurality of interlayer insulating films and forming a predetermined electrode pattern may be stably performed in a later step.

Claims (7)

An etching process using a hard mask is performed on the first and second regions having different pattern densities to form a contact hole in which a lower conductive layer is exposed in the insulating layer, and the hard mask is formed on the first and second regions. Providing a substrate remaining at different thicknesses; Depositing a contact plug with a material different from that of the insulating layer to fill the contact hole; Removing the hard mask while simultaneously etching the contact plug so as to be isolated inside the contact hole; And Selectively recessing the insulating layer to have the same height as the contact plug by performing an etching process using an etching selectivity with the contact plug; Contact plug forming method of a semiconductor device comprising a. The method of claim 1, And the hard mask is formed of the same material as the contact plug. The method according to claim 1 or 2, And the hard mask is formed of a polysilicon film. The method of claim 1, And the hard mask is formed of a material different from that of the contact plug. The method according to claim 1 or 4, The hard mask is a contact plug forming method of a semiconductor device made of tungsten. The method according to any one of claims 1, 2 and 4, The etching process is a method of forming a contact plug of a semiconductor device using the contact plug as an etch stop layer. The method of claim 1, And depositing an etch stop layer to selectively cover the insulating layer and the contact plug after selectively recessing the insulating layer.

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