KR100895374B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent the loss of a bit line hard mask in an upper part of the bit line by performing the wet etching using an etch selection ratio between a nitride layer and an oxide layer. A first interlayer insulating layer(115) is formed in an upper part of a semiconductor substrate(100) including a gate electrode(105) and a landing plug contact(110). The first interlayer insulating film and a bit line pattern(120) are successively formed in the semiconductor substrate. The bit line spacer is formed in both sides of the bit line pattern. A second interlayer insulating layer(130) and a third interlayer insulating layer(140) are formed in the overall upper part including the bit line pattern. A bit line hard mask layer(119) in the upper part of the bit line pattern is exposed by performing a planarization etching process. The hard mask layer and a photosensitive film are formed on the planarized semiconductor substrate. The hard mask layer pattern is formed by etching the hard mask layer. The trench is formed by etching a third interlayer insulating layer. A spacer(155a) is formed in the extended trench side wall by performing a front etching process. A storage electrode contact plug(165) which exposes the bit line hard mask layer is formed by etching the hard mask layer pattern and a polysilicon layer.

Description

Method for manufacturing a semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

100 semiconductor substrate 105 gate pattern

110 landing plug contact 115 first interlayer insulating film

117: barrier metal layer 118: bit line electrode layer

119: bit line hard mask layer 120: bit line pattern

125: bit line spacer 130: second interlayer insulating film

140: third interlayer insulating film 145: hard mask layer pattern

150 trench 155 spacer layer

155a: spacer 160: storage electrode contact hole

165: storage electrode contact plug

The present invention relates to a method of manufacturing a semiconductor device, and to performing a wet etching process using a difference in etching selectivity between the nitride film and the oxide film when forming the storage electrode contact hole, to prevent loss of the bit line hard mask layer on the top of the bit line. In this way, the thickness of the bit line hard mask layer can be reduced, thereby forming a bit line having a vertical profile, thereby improving a device characteristic.

Although not shown, a method of manufacturing a semiconductor device according to the related art will be described. An interlayer insulating layer is formed on a semiconductor substrate provided with a landing plug contact and a bit line.

Next, a hard mask layer pattern defining a storage electrode region is formed on the interlayer insulating layer, and the trench is formed by partially etching the interlayer insulating layer using the hard mask layer pattern as an etching mask.

In this case, the trench forming process is performed by dry etching.

Next, after the trench bottom is extended, spacers are formed on both sides of the trench.

The interlayer insulating layer left under the spacer is further etched to form a storage electrode contact hole exposing the landing plug contact.

In this case, the storage electrode contact hole forming process is performed by dry etching, and since the dry etching has a low difference in etching selectivity between the oxide film and the nitride film, the nitride hardmask layer on the upper end of the bit line is lost even if the self alignment contact (SAC) process is performed. Loss occurs.

In the method of manufacturing a semiconductor device according to the related art described above, a line type storage electrode contact plug separates nodes between nodes through a CMP process after contact formation, thereby causing loss of a bit line hard mask layer. ) Will occur.

Therefore, the thickness of the bit line hard mask layer needs to be thick, which causes an aspect ratio to increase, thereby preventing the profile of the bit line from being vertically formed.

In order to solve the above problem, the wet etching using the difference in the etching selectivity between the nitride film and the oxide film is performed when the storage electrode contact hole is formed, thereby preventing the loss of the bit line hard mask layer on the upper part of the bit line. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a hard mask layer thickness can be reduced, thereby forming a vertical profile bit line and improving the device.

Method for manufacturing a semiconductor device according to the present invention

Forming an interlayer insulating film on the semiconductor substrate including the landing plug contact and the bit line;

Performing a planarization process until the bit line is exposed;

Forming a hard mask layer pattern defining a storage electrode contact region on the interlayer insulating layer;

Forming a trench by etching the interlayer insulating layer using the hard mask layer pattern as a mask;

Expanding the trench bottom;

Forming spacers on sidewalls of the extended trenches;

Further etching the interlayer insulating layer using the hard mask layer pattern as a mask to form a storage electrode contact hole exposing the landing plug contact;

The interlayer insulating film is formed of a stacked structure of SOD and HDP oxide film,

The process of expanding the trench bottom may be performed by isotropic etching,

The process of expanding the trench bottom may be performed such that the SOD oxide layer is exposed.

The spacer is formed of a nitride film,

Forming the spacer

Forming a nitride film on the entire surface including the extended trench and then performing an etch-back process to leave the nitride film on the extended trench sidewall;

The storage electrode contact hole forming process may be performed by anisotropic etching,

The anisotropic etching is performed using a BOE solution,

Forming a spacer on the sidewall of the storage electrode contact hole using any one selected from a nitride film, a USG oxide film, and a combination thereof;

Removing the hard mask layer pattern;

Forming a polysilicon layer on the whole including the storage electrode contact hole;

And etching the hard mask layer pattern and the polysilicon layer to form a storage electrode contact to expose the bit line and the interlayer insulating layer.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a first interlayer insulating layer 115 is formed on a semiconductor substrate 100 including a gate electrode 105 and a landing plug contact 110, and a bit line is formed on the first interlayer insulating layer 115. The pattern 120 is formed.

Here, the bit line pattern 120 may be formed in a stacked structure of the bit line barrier metal layer 117, the bit line conductive layer 118, and the bit line hard mask layer 119.

In addition, the bit line barrier metal layer 117 is formed of titanium (Ti) and titanium nitride (TiN), the bit line electrode layer 118 is formed of a tungsten (W) layer, and the bit line hard mask layer 119 is formed of a nitride film. It is preferable to form.

Next, the bit line spacers 125 are formed on both sides of the bit line pattern 120, and then the second interlayer insulating layer 130 and the third interlayer insulating layer 140 are formed on the entire portion including the bit line pattern 120. do.

Here, the second interlayer insulating film 130 is a spin on dielectric (SOD) oxide film, and preferably formed by a coating method.

In addition, the third interlayer insulating layer 140 may be formed of an HDP oxide layer having a different etching selectivity from the SOD oxide layer.

Next, the planarization etching process is performed until the bit line hard mask layer 119 on the bit line pattern 120 is exposed.

Referring to FIG. 1B, a hard mask layer and a photoresist layer are formed on the planarized semiconductor substrate 100.

Next, a photoresist pattern (not shown) defining a storage electrode contact region is formed by performing an exposure and development process on the photoresist.

Next, the hard mask layer is etched using the photoresist pattern (not shown) as a mask to form a hard mask layer pattern 145, and then the photoresist pattern (not shown) is removed.

Referring to FIGS. 1C and 1D, the trench 150 is formed by etching the third interlayer insulating layer 140 using the hard mask layer pattern 145 as a mask.

Next, the bottom of the trench 150 is extended to expose a part of the second interlayer insulating film 130.

In this case, in the process of expanding the bottom of the trench 150, it is preferable to perform a wet isotropic etching so that the bottom of the trench 150 is expanded in the form of a bulb.

Referring to FIGS. 1E and 1F, a spacer layer 155 having a predetermined thickness is formed on an entire upper portion of the extended trench 150.

Here, the spacer layer 155 may be formed of a nitride film made of the same material as the hard mask layer pattern 145.

Next, a nitride layer is left on the extended sidewall of the trench to form a spacer 155a by performing an entire surface etching process.

In this case, the upper side of the second interlayer insulating layer 130 is partially etched by the front surface etching process.

Referring to FIG. 1G, the storage electrode exposing the landing plug contact 110 by etching the second interlayer insulating layer 130 and the first interlayer insulating layer 115 using the hard mask layer pattern 145 and the spacer 155a as a mask. The contact hole 160 is formed.

In this case, the storage electrode contact hole 160 may be a wet anisotropic etching process.

At this time, since the wet etching has a larger difference in etching selectivity between the oxide film and the nitride film than the conventional dry etching process, the bit line hard mask during the etching of the SOD oxide film, which is the second interlayer insulating film 130, is performed. Loss of the nitride film, which is the layer 119, may be reduced.

Referring to FIG. 1H, spacers (not shown) for storage electrodes are formed on sidewalls of the storage electrode contact holes 160.

In this case, the storage electrode spacer (not shown) is preferably formed using any one selected from a nitride film, a USG oxide film, and a combination thereof.

Next, the polysilicon layer is formed on the entire surface including the storage electrode contact hole 160 and then the etch-back process is performed to expose the hard mask layer pattern 145.

Next, the hard mask layer pattern 145 and the polysilicon layer are etched by a CMP process to form the storage electrode contact plug 165 exposing the bit line hard mask layer 119.

The method of manufacturing a semiconductor device according to the present invention prevents the loss of the bit line hard mask layer on the upper part of the bit line by performing wet etching using the difference in etching selectivity between the nitride layer and the oxide layer when forming the storage electrode contact hole. As a result, the thickness of the bit line hard mask layer can be reduced, thereby forming a vertical bit line, thereby improving the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

Forming an interlayer insulating film on the semiconductor substrate having a landing plug contact; Forming a bit line on the interlayer insulating film, and forming an SOD film and an HDP oxide film on the bit line and the interlayer insulating film; Performing a planarization process until the bit line is exposed; Forming a hard mask layer pattern defining a storage electrode contact region on the HDP oxide layer; Forming a trench by etching the HDP oxide layer using the hard mask layer pattern as a mask; Expanding the trench bottom; Forming a spacer on sidewalls of the extended trench; And Forming a storage electrode contact hole exposing the landing plug contact by etching the SOD oxide layer and the interlayer insulating layer using the hard mask layer pattern and the spacer as a mask; Method of manufacturing a semiconductor device comprising a. delete The method of claim 1, The process of expanding the bottom of the trench is a method of manufacturing a semiconductor device, characterized in that for proceeding isotropic etching. The method of claim 3, wherein The process of expanding the trench bottom is performed to expose the SOD oxide film. The method of claim 1, And the spacer is formed of a nitride film. The method of claim 1, Forming the spacer And forming a nitride film on the entire surface including the extended trench and performing an etch-back process to leave the nitride film on the extended sidewall of the trench. The method of claim 1, And the storage electrode contact hole forming process is performed by anisotropic etching. The method of claim 7, wherein The anisotropic etching is a method of manufacturing a semiconductor device, characterized in that performed using a BOE solution. The method of claim 1, And forming a spacer on the sidewall of the storage electrode contact hole using any one selected from a nitride film, a USG oxide film, and a combination thereof. The method of claim 1, Forming a polysilicon layer on the entirety including the storage electrode contact hole; And And etching the hard mask layer pattern and the polysilicon layer to form a storage electrode contact to expose the bit line and the HDP oxide layer.

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