KR20070074175A - Method for manufacturing storagenode contact in semiconductor device - Google Patents

Abstract

A method for forming a storage node contact of a semiconductor device is provided to perform stably in-situ processing of hard mask etching and storage node contact etching and to simplify forming processes by using a nitride based hard mask instead of a polysilicon layer. A first insulating layer is formed on a predetermined structure with a landing plug contact(34). A bit line pattern composed of a bit line conductive layer and a bit line hard mask is formed on the first insulating layer. A second insulating layer is formed on the resultant structure in order to fill a gap between bit line patterns. The second insulating layer is planarized until the bit line pattern is exposed to the outside. A hard mask(39a) made of a nitride based material is formed on the second insulating layer. The hard mask is made of SRON, Si3N4 or SiON.

Description

METHODS FOR MANUFACTURING STORAGENODE CONTACT IN SEMICONDUCTOR DEVICE}

1A to 1C illustrate a method of forming a storage node contact using a line type self-aligned contact etching according to the prior art.

2A and 2B are SEM photographs showing a bitline profile according to the prior art.

3A to 3F illustrate a method of manufacturing a storage node contact according to an embodiment of the present invention.

4A and 4B are SEM photographs showing a bit line profile according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

30: gate conductive layer 31: gate hard mask

32: gate spacer 33: first interlayer insulating film

34: landing plug contact 35: second interlayer insulating film

36: bit line conductive layer 37: bit line hard mask

38: third interlayer insulating film 39a: hard mask polysilicon pattern

41: primary opening 42: protective film

43: etching stop film 44: secondary opening

45: storage node contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a storage node contact using a line type self aligned contact etch.

When applying 80nm technology using Line type Self Aligned Contact, storage node contact and storage node can be patterned with KrF photoresist, and SNC KO (Key Open) etching process can be omitted. The technology has a savings of 36.7 billion won / year based on 3FAB of capacity.

1A to 1C illustrate a method of forming a storage node contact using a line type self-aligned contact etching according to the related art.

As shown in FIG. 1A, a first interlayer insulating film is formed on a gate pattern having a gate conductive layer 10, a gate hard mask 11, and a gate spacer 12. After forming (13), the first interlayer insulating film 13 is planarized through CMP (Chemical Mechanical Polishing).

Subsequently, the first interlayer insulating film between the gate patterns is selectively etched, and a landing plug contact 14 is formed thereon.

Subsequently, a second interlayer insulating film 15 is deposited on the entire surface including the landing plug contact 14.

Subsequently, a bitline pattern having a form intersecting the gate pattern is formed on a predetermined surface of the second interlayer insulating film 15. In this case, the bit line pattern forms a bit line pattern stacked in the order of the bit line conductive layer 16 and the bit line hard mask 17.

Subsequently, the third interlayer insulating film 18 is deposited on the entire surface by using an HDP (High Density Plasma) oxide film until the gap between the bit line patterns is filled, and then planarized through CMP to the top of the bit line pattern.

Subsequently, a hard mask polysilicon 19 is deposited on the planarized third interlayer insulating layer 18, and then a line type contact mask 20 is formed.

As shown in FIG. 1B, the hard mask polysilicon 19 is etched using the contact mask 20 as an etch barrier layer to form a line type hard mask polysilicon pattern 19a, and then the contact mask 20 is formed. Remove

Subsequently, the hard mask polysilicon pattern 19a is first partially etched with the etch barrier layer to form the primary opening 21, and the wet etching is continuously performed to expand the width of the primary opening 21. .

Subsequently, an etch stop layer 22 for spacer reinforcement purposes is formed.

Subsequently, the third interlayer insulating film 18 and the first interlayer insulating film 15 under the primary opening are etched to form a secondary opening 23. Here, the secondary opening 23 exposes the landing plug contact 14 and is smaller than the primary opening 21 because the secondary opening 23 exposes the landing plug contact 14 and is etched using the line type hard mask polysilicon pattern 19a.

The primary opening 21 and the secondary opening 23 become storage node contact holes.

As illustrated in FIG. 1C, polysilicon is deposited until the storage node contact hole including the first opening 21 and the second opening 23 is filled, and then a front etching process without a mask, such as an etch back, is performed. Proceeding to form a storage node contact 24 is buried in the storage node contact hole.

However, the conventional line-type self-aligned contact etching process has the following problems.

Figure 2a is a photograph showing a bit line profile according to the prior art, Figure 2b is a photograph showing a bit line damage according to the prior art.

Poor steep bitline profile

The bit line process has been applied to the lesson process (Lessen process) to continuously reduce the Final Inspection Critical Dimension (FICD) compared to the mask critical dimension (hereinafter referred to as CD) by the requirements of the previous device.

This is the process of artificially reducing the CD by using the etching solution. In the device of 80 nm or less, the bit line hard mask nitride film is very weak in profile and has a narrow spire profile at the upper part than the lower part (see FIG. 2A). . Such a spire profile is further deteriorated by the etching process (sputtering) during the HDP deposition process during the HDP gap fill process, which is the third interlayer insulating film, and becomes sharp, and in a severe case, the phenomenon occurs.

) 프로파일② Asymmetrical spacer formation and irregularities (

) profile

) 프로파일을 갖게 된다(도 2b 참조). 여기서, 스페이서라 함은 스토리지노드콘택 식각후에 잔류하는 제3층간절연막의 잔류형태를 의미한다.Proceeding along the basic process flow of the line-type self-aligned contact (SAC) process, left and right symmetrical spacers are found due to the influence (bending and thinning) of the bit line profile mentioned in step 1). In addition, due to the poor bit line profile, the bit line pattern has irregularities due to its resistance to self-aligned contact (SAC) etching recipes.

) Have a profile (see FIG. 2B). Here, the spacer refers to the remaining form of the third interlayer dielectric layer remaining after the storage node contact etching.

In the case of asymmetric spacers, the bit line side walls are extremely fragile due to deterioration of the oxide spacers, making them vulnerable to SAC fail, and in the case of the uneven profile, the margins of the separation process of the subsequent LPP (Landing Plug Poly) CMP process (residual nitride film) And CD).

③ insufficient spacer thickness

Ensuring the proper thickness of the oxide spacer is very important for preventing SAC fail and reducing the capacitance value of the bit line. However, as a result of experiments, the thickness of the oxide spacer does not increase significantly even if the deposition thickness of the nitride film is increased. The reason for this is that since the profile is inclined, a large amount of etching is performed on the nitride film, and thus it is determined that the spacer as much as desired is not secured.

④ Process increase and defects caused by using poly hard mask

Increasing the KO (Key Open) process and using the poly hard mask by using a poly hard mask has a problem that it is difficult to proceed in-situ process during the hard mask etching process. In addition, there is a difficulty in the actual mass production process due to reduced yield due to the problem of flow defects occurring in the wet cleaning process.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and has the following objects.

First, the present invention provides a method for forming a storage node contact of a semiconductor device capable of in-situ etching by omitting the KO process by changing the polyhard mask, which is a SAC problem, to a nitride film-based material during the line type storage node contact forming process. Its purpose is to.

Another object of the present invention is to provide a method for forming a storage node contact of a semiconductor device capable of securing a stable bit line spacer forming process by depositing a capping layer on an upper portion of a bit line during a storage node contact process.

According to an aspect of the present invention, there is provided a method of forming a first insulating layer on a structure having a landing plug contact, and forming a bit line conductive layer and a bit line hard mask on a predetermined surface of the first insulating layer. Forming a stacked bit line pattern in a sequence; forming a second insulating film on the entire surface until the bit line pattern is filled; and planarizing the second insulating film until an upper portion of the bit line pattern is exposed. Depositing a hard mask using a nitride based material on the second insulating layer, forming a hard mask pattern by etching the hard mask, and forming the hard mask pattern as an etch barrier layer. Forming a first opening by partially etching the second insulating layer in the same chamber in-situ with a mask pattern forming process; Extending a width of the primary opening, forming a protective film for changing the upper profile of the bit line pattern exposed by the primary opening into a rectangular profile, forming a spacer on the protective film; Forming a secondary opening by performing spacer etching on the spacer until the surface of the landing plug contact is exposed, and forming a storage node contact embedded in the storage node contact hole formed of the first and second openings. It provides a method for forming a storage node contact of a semiconductor device comprising a.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

3A to 3F are cross-sectional views illustrating a method of forming a storage node contact of a semiconductor device according to an embodiment of the present invention. The left side of the figure is a diagram cut in the direction crossing the bit line pattern, and the right side is a figure cut in the direction parallel to the bit line pattern. Hereinafter, the cross-sectional views of the process in two directions are shown together for detailed description.

First, as shown in FIG. 3A, a first interlayer insulating film 33 is formed on a gate pattern having the gate conductive layer 30, the gate hard mask 31, and the gate spacer 32, and then the first interlayer. The insulating film 33 is planarized through CMP.

Subsequently, the first interlayer insulating film 33 between the gate patterns is selectively etched, and a landing plug contact 34 is formed thereon.

Subsequently, a second interlayer insulating film 35 is deposited on the entire surface including the landing plug contact 34.

Subsequently, a bit line pattern having a shape intersecting with the gate pattern is formed on a predetermined surface of the second interlayer insulating film 35. At this time, the bit line pattern is stacked in the order of the bit line conductive layer 36 and the bit line hard mask 37, the bit line conductive layer 36 is a single material or a plurality of materials selected from W, Ti, WN or WSi. The bit line hard mask 37 is formed of SiON or SiN.

Subsequently, the third interlayer insulating film 38 is deposited on the entire surface of the bit line pattern by using an HDP (High Density Plasma) oxide film to fill the gap between the bit line patterns, and then planarized through CMP to the upper part of the bit line pattern.

Subsequently, the hard mask 39 is formed of a nitride film such as Si ₃ N ₄ and SiO _N having a high etching selectivity with SRON (Silicon Rich Oxinitride) or an oxide film on the planarized third interlayer insulating film 38. A contact mask 40 of (Line type) is formed.

As shown in FIG. 3B, the hard mask 39 is etched using the contact mask 40 as an etch barrier layer using an etching chamber for dielectric to form a line type hard mask pattern 39a. Afterwards, the hard mask pattern 39a is partially etched into the etch barrier layer in-situ to form a primary opening 41, and a wet etch is continuously performed. The width of the difference opening 41 is expanded.

The etch recipe for forming the hard mask pattern 39a includes a fluorine source gas such as a pressure of 10 to 100 mTorr, a power of 100 to 2000 W, a CxFy of 1 to 100 sccm, and a CxHyFz of 1 to 100 sccm. , 1 to 100 sccm O ₂ , 1 to 100 sccm N ₂ , 1 to 1000 sccm Ar reaction gas is used. Here, x, y, z are natural numbers or rational numbers including a decimal point. In addition, during the first partial etching, the etching process proceeds to an etching condition having a selectivity to the nitride film. In the wet etching process of expanding the width of the primary opening 41, the etching condition is a hydrofluoric acid solution of 20: 1 to 300: 1, that is, BOE (Buffered Oxide Etchant) or DHF (Dilute HF).

Thereafter, the contact mask 40 is removed.

Subsequently, as shown in FIG. 3C, the passivation layer 42 is formed on the entire surface including the primary opening 41 having a widened width. In this case, the passivation layer 42 may be deposited to an appropriate thickness on the bit line pattern. Preferably, the passivation layer 42 is formed of an oxide layer or a nitride layer. Preferably, the film is formed using a USG (Undoped Silicate Glrass) film at a thickness of 1000 mW or less, preferably 400 to 900 mW. The USG film is an oxide film having poor step coverage. When the USG film is deposited, a USG film having a large thickness is deposited on the bit line pattern to correct the profile. That is, the profile of the bit line hard mask 37 has a thin upper profile and a thick trapezoidal profile at the bottom, while depositing the protective layer 42 becomes a rectangular profile due to the protective effect. In other words, the protective film 42 is introduced for the purpose of profile correction.

On the other hand, the protective film 42 may be formed of a nitride film material having a weak step coverage.

As shown in FIG. 3D, a nitride film spacer 43 for the purpose of reinforcing the spacers on the sidewalls of the bit line patterns is formed on the entire surface including the protective film 42 to a thickness of 50 to 500 mW. Here, the nitride film spacer 43 is made of SiON or SiN.

As shown in FIG. 3E, the SNC spacer is etched to open the secondary opening 44. At this time, the loss of the bit line hard mask 37 is greatly reduced due to the passivation layer 42 deposited on the bit line pattern. That is, the protective film 42 functions as a sacrificial film.

The secondary openings 44 may etch the third interlayer insulating film 38 and the second interlayer insulating film 35 under the first opening 41 while etching the spacers of the nitride film spacer 43. 44). Here, the secondary opening 44 exposes the landing plug contact 34, and when the secondary opening 44 is formed, the protective layer 42 is etched in situ at the same time as the etching of the interlayer insulating layers. The spacers 43 remain on the sidewalls of the bit line hard mask 37 in the form of contact spacers.

The primary opening 41 and the secondary opening 44 become storage node contact holes, and an etching process for forming the primary opening 41 is referred to as 'primary storage node contact etching', and the secondary opening 44 ) The etching process for forming is called 'secondary storage node contact etching'.

As a result of the secondary storage node contact etching, the upper profile of the bit line pattern is a rectangular profile (see 'X'). As such, the stable oxide film thickness (see 'Y') can be secured by changing the stable profile of the rectangular profile X by changing the spire profile of the bit line hard mask. The oxide spacer thickness Y is further increased by the capping film 42 thickness.

) 프로파일이 발생하지 않는다. 이로써, 후속 CMP 공정시 이웃한 스토리지노드콘택간 분리 CD가 크게 증가한다.In addition, the etch loss of the bit line hard mask is prevented by the passivation layer 42, and thus the unevenness (formation) generated after the first and second storage node contact etching is performed.

) Profile does not occur. This greatly increases the separation CD between neighboring storage node contacts in subsequent CMP processes.

As shown in FIG. 3F, polysilicon is deposited until the storage node contact hole including the primary opening 41 and the secondary opening 44 is filled, and then etched back to storage embedded in the storage node contact hole. The node contact 45 is formed. At this time, the hard mask pattern 39a is polished and removed.

In the case of applying the storage node contact forming method of the semiconductor device according to the exemplary embodiment described above, the bit line profiles are as shown in FIGS. 4A and 4B. Here, FIG. 4A is a view corresponding to FIG. 2A, which is a profile after forming the passivation layer 42, and FIG. 4B is a view corresponding to FIG. 2B, illustrating a profile after SNC spacer etching.

As shown in FIGS. 4A and 4B, not only the loss of the bit line is improved as compared with FIGS. 2A and 2B, but the sidewall spacers are secured to a sufficient thickness on both sidewalls of the bit line.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, in the present invention, a hard mask etching process and an SNC etching process can be performed in-situ in an insulating film etching chamber by applying a nitride film-based hard mask instead of a polysilicon film, and a key open mask ) Forming process and etching process can be omitted.

Second, in the present invention, an oxide film spacer is stably implemented by forming a rectangular profile on an upper portion of the bit line pattern by applying a protective film having a poor coating on the upper portion of the bit line pattern.

In addition, due to the effect of the protective film, the loss of the bit line hard mask during the subsequent nitride spacer and the second storage node contact etching process is greatly reduced.

In addition, the uneven profile generated in the upper part of the bit line after the etching process for forming the storage node contact hole is greatly improved, and the process margin is greatly increased during the subsequent CMP process.

In addition, the left and right asymmetric spacers have improved the spacer disappearance phenomenon found in some bit line patterns, and it is possible to increase the residual thickness of the bit line hard mask of the bit line pattern to secure the storage node contact separation margin. .

In addition, by securing the profile of the upper part of the bit line pattern as a stable rectangular profile, sufficient separation CD can be obtained during the CMP process of the storage node contact.

Claims (9)

Forming a first insulating layer on the structure of the landing plug contact; Forming a bit line pattern stacked in the order of the bit line conductive layer and the bit line hard mask on a predetermined surface of the first insulating layer; Forming a second insulating film over the entire surface until the bit line pattern is filled; Planarizing the second insulating layer until an upper portion of the bit line pattern is exposed; Depositing a hard mask on the second insulating layer by using a nitride film-based material; Etching the hard mask to form a hard mask pattern; Forming a first opening by first etching the second insulating layer in the same chamber in-situ with the hard mask pattern forming process using the hard mask pattern as an etch barrier layer; Expanding the width of the primary opening in the chamber; Forming a protective film for converting the upper profile of the bit line pattern exposed by the primary opening into a rectangular profile; Forming a spacer on the passivation layer; Forming a secondary opening by performing spacer etching on the spacer until the surface of the landing plug contact is exposed; And Forming a storage node contact embedded in the storage node contact hole formed by the first and second openings; Storage node contact forming method of a semiconductor device comprising a. The method of claim 1, The hard mask is a storage node contact forming method of a semiconductor device, characterized in that formed by SRON film, Si ₃ N ₄ or SiON film. The method of claim 2, The forming of the hard mask pattern may include using a fluorine-based source gas such as CxFy or CxHyFz, and an O ₂ , N ₂ or Ar reaction gas. Here, x, y, z are natural or rational numbers. The method of claim 3, The amount of inflow of CxFy, CxHyFz is 1 ~ 100sccm, the inflow of O ₂ , N ₂ is 1 ~ 100sccm, the inflow of Ar is 1 ~ 1000sccm characterized in that the storage node contact forming method of the semiconductor device. The method of claim 4, wherein Forming the hard mask is a method of forming a storage node contact of a semiconductor device, characterized in that the pressure of 10 ~ 100mTorr, 100 ~ 2000W power. The method according to any one of claims 1 to 5, Forming the protective film, And forming an oxide film or nitride film-based material having a poor coating property such that a rectangular profile appears on the bit line pattern. The method of claim 6, The protective film is a storage node contact forming method of a semiconductor device, characterized in that formed by the USG film. The method of claim 7, wherein The protective film is a storage node contact forming method of a semiconductor device, characterized in that formed in the thickness of 500 ~ 900Å. The method of claim 8, The hard mask is formed by SRON.

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