KR20070073441A - Method for manufacturing storagenode contact in semiconductor device - Google Patents

Abstract

A method for forming a storage node contact of a semiconductor device is provided to minimize the damage of a bit line hard mask due to an etching process by forming previously a buffer oxide layer on a bit line pattern. A second insulating layer(33) is formed on a first insulating layer(31) with a landing plug contact(32). A bit line pattern composed of a bit line conductive layer and a bit line hard mask sequentially stacked with each other is formed on the second insulating layer. A third insulating layer is formed on the resultant structure until a gap between bit line patterns is completely filled. The third insulating layer is planarized until the bit line pattern is exposed to the outside. A first hole is formed on the resultant structure by performing a first etching process on the second insulating layer. A lateral portion of the contact hole is expanded. A buffer oxide layer(41) is formed on the resultant structure in order to cover the bit line pattern. A second hole for exposing the landing plug contact to the outside is formed on the resultant structure by using a second etching process.

Description

METHODS FOR MANUFACTURING STORAGENODE CONTACT IN SEMICONDUCTOR DEVICE}

Figure 1a is a photograph showing a bit line profile according to the prior art,

Figure 1b is a photograph showing a bit line damage according to the prior art,

2A to 2E illustrate a method of forming a storage node contact according to an embodiment of the present invention;

3 is a photograph showing a profile of a bit line pattern according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31: first interlayer insulating film 32: landing plug contact

33: second interlayer insulating film 34: Ti / TiN

35 bit line tungsten film 36 bit line hard mask nitride film

37: bit liner 38: third interlayer insulating film

39: storage node contact mask 40: primary hole

41: buffer oxide film 42: secondary hole

43: Storage Node Contact

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for forming a storage node contact plug of a semiconductor device.

As semiconductor devices are highly integrated, in the case of storage node contact plugs of 80 nm technology or less, contacts are formed in a hole type using ArF photoresist.

However, when the storage node contact is formed as a hole type, since the storage node contact plug is embedded in the hole type storage node contact hole, the open area of the top portion of the storage node contact plug is small, so that the overlay margin with the subsequent storage node is insufficient. There is a problem in that to form a pad polysilicon.

In addition, the ArF photoresist is applied during the etching process to form the hole-type storage node contact hole. In this case, there is a problem in that mass productivity is lowered due to an increase in maintenance cost due to expensive equipment.

In addition, the bit line hard mask nitride layer thickness is increased to reduce the bit line size due to device shrink during the storage node contact etching and to secure the SAC margin during the CMP process. However, increasing the bit line hard mask nitride film thickness causes a problem that the bit line profile becomes thin or bent due to an increase in the aspect ratio (see FIG. 1A) .A polymer barrier is not formed on the bit dry hard mask nitride film during etching of the storage node contact. As a result, self-aligned contact etching is not performed, resulting in excessive bit line hard mask nitride film loss (see FIG. 1B).

Figure 1a is a picture showing a bit line profile according to the prior art, Figure 1b is a picture showing a bit line damage according to the prior art, the prior art is a weak bit line profile, the etching loss of the bit line hard mask nitride film It can be seen that the increase.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of forming a storage node contact of a semiconductor device capable of preventing self-aligned contact failure caused by a weak profile of a bit line pattern. have.

According to another aspect of the present invention, there is provided a method of forming a storage node contact, the method including forming a second insulating layer on an upper portion of a structure in which a landing plug contact is formed in a first insulating layer, and forming a bit line conductive layer on a predetermined surface of the second insulating layer. Forming a stacked bit line pattern in the order of a bit line hard mask, forming a third insulating layer on the entire surface until the bit line patterns are filled, and forming the third insulating layer until the upper portion of the bit line pattern is exposed. Planarization, partially etching the second insulating layer to form a primary hole, extending side surfaces of the primary hole, and forming an upper portion of the bit line pattern exposed by the primary hole in which the side surface is extended. Forming a covering buffer oxide layer, performing secondary etching until the surface of the landing plug contact is exposed, and forming secondary holes; and 1,2 And forming a storage node contact embedded in the storage node contact hole made of a hole, wherein the buffer oxide layer has a thickness at an upper side and an edge of the bit line pattern thicker than a thickness at the remaining sidewall portion. Characterized in that the step coverage is formed of a weak material.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2E illustrate a method of forming a storage node contact according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, after the second interlayer dielectric layer 33 is formed on the structure in which the landing plug contact 32 is formed in the first interlayer dielectric layer 31, the Ti / I layer is formed on the second interlayer dielectric layer 33. A plurality of bit line patterns stacked in the order of the TiN 34, the bit line tungsten film 35, and the bit line hard mask nitride film 36 are formed. Here, the Ti / TiN 34 laminated in the order of Ti and TiN is formed to have a thickness of 100 kV to 1000 kV, and the bit line tungsten film 35 is formed to have a thickness of 300 kV to 1000 kV and a bitline hardmask nitride film. , 36) is formed to a thickness of 1500Å to 3500Å.

The etching process for forming the bit line pattern is divided into a bit line hard mask nitride film etching process and a bit line tungsten film / Ti / TiN etching process. First, the etching process of the bit line hard mask nitride film 36 is CF ₄ / CHF ₃ /. Using a mixed gas of O ₂ / Ar, a power of 300 W to 1000 W is applied in a pressure range of 20 mT to 70 mT. The bit line tungsten film 35 and the Ti / TiN 34 are etched using a mixed gas of SF ₆ / BCl ₃ / N ₂ / Cl ₂ , and a power of 300 W to 1000 W is applied in a pressure range of 20 mT to 70 mT. Proceed by

Subsequently, a bit line facer nitride film is deposited on the entire surface including the bit line pattern to have a thickness of 50 μs to 150 μm, followed by bit liner etching to form bit line spacers 37 in contact with both sidewalls of the bit line pattern.

Subsequently, a third interlayer insulating film 38 is deposited on the entire surface until the bit line patterns are filled. At this time, the third interlayer insulating film 38 is formed of an oxide film deposited using a high density plasma method, and has a thickness of 4000 kPa to 10,000 kPa. Accordingly, the third interlayer insulating film 38 is formed with a predetermined thickness on the bit line pattern while filling the bit line pattern.

Subsequently, chemical mechanical polishing (hereinafter, referred to as 'ILD CMP') on the third interlayer insulating film 38 is performed to planarize the third interlayer insulating film 38. At this time, the chemical mechanical polishing of the third interlayer insulating film 38 proceeds by stopping the polishing in the bit line hard mask nitride film 36.

As shown in FIG. 2B, a KrF photoresist is applied to the entire surface of the chemical mechanical polishing-completed structure and patterned by exposure and development to form a storage node contact mask 39.

In this case, the storage node contact mask 39 is a line type mask for opening a portion where the storage node contact hole is to be formed, and the storage node contact mask 39 is a line type mask formed in a direction crossing the bit line pattern. .

Subsequently, the storage node contact etching is performed by using the storage node contact mask 39. In this case, the storage node contact etching primarily performs partial etching. For example, when the third interlayer insulating film 38 is etched to open the landing plug contact 32 between the bit line patterns, the bit line tungsten film 35 is not etched until the landing plug contact 32 is completely exposed. The etching is performed only up to a part of the sidewall of the bit line hard mask nitride layer 36.

As described above, the primary storage node contact etching process performed by partial etching is performed by using dry etching and wet etching.

First, in the primary storage node contact etching, dry etching is performed at a power of 1000 W to 2000 W at a pressure of 15 to 50 mT, CF ₄ , C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , CHF ₃ , CH ₂ F ₂ , The gas selected from the group consisting of Ar, O ₂ , CO, and N ₂ is used to proceed to a 1000 kPa to 2000 kPa target using a mixed gas of at least two kinds of gases.

Subsequently, the wet etching is performed by using a hydrofluoric acid (HF) solution or a BOE solution after stripping the storage node contact mask. The wet etching using the hydrofluoric acid-containing solution is mainly performed by side etching since the side etching occurs. The side surface of the primary hole 40 of the storage node contact hole is extended. Thus, the primary hole 40 is formed by extending the side through the wet etching.

As described above, in the primary storage node contact etching process, which is performed by partial etching, the primary hole formed through the primary storage node contact etching is performed by mixing dry etching and wet etching at the last, and thus wet etching is performed last. 40) Extend the sides.

Here, the primary hole 40 becomes an entrance area of the storage node contact hole, thereby increasing the open area of the top portion of the storage node contact plug embedded in the storage node contact hole, thereby securing alignment margin when forming the subsequent storage node. Can be.

As shown in FIG. 2C, a buffer oxide film 41 is formed on the entire surface including the primary hole 40 with side surfaces thereof. Here, the buffer oxide film 41 is to be deposited to an appropriate thickness on the upper part of the bit line pattern. Preferably, the buffer oxide film 41 is deposited by PECVD. The loss of the line hard mask nitride film 36 is minimized.

As the buffer oxide film 41 is deposited by PECVD, an oxide film having poor step coverage is deposited, that is, a large thickness is deposited on the upper and corners of the bit line pattern, and a relatively thin thickness is deposited on the remaining sidewalls. . Lateral deposition is less than 20%.

As such, the etching profile may be secured during the subsequent self-aligned contact (SAC) process by reinforcing the weak profile of the bit line pattern with the buffer oxide film 41 having weak step coverage.

As shown in FIG. 2D, the storage node contact etching and the secondary storage node contact etching are performed again using a sledge node contact mask (not shown). In this case, the primary storage node contact etching was performed by partial etching using dry etching and wet etching, but the secondary storage node contact etching was performed by using dry etching until the upper portion of the landing plug contact 32 was completely exposed. The interlayer insulating layers 38 and 33 under the hole 40 are etched to open the secondary hole 42 of the storage node contact hole. Here, the secondary hole 42 is formed by dry etching, and the dry etching is performed at a power of 1000 W to 2000 W at a pressure of 15 to 50 mT, C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , and CH ₂ F ₂ , Ar, O ₂ , CO and N ₂ to proceed using a mixed gas of at least two gases selected from the group consisting of.

The above-described primary hole 40 and the secondary hole 42 form a storage node contact hole, and the storage node contact hole has a form of the primary hole 40 whose inlet side is extended by primary storage node contact etching. The remaining area under the inlet is in the form of a secondary hole 42 having a smaller line width than the primary hole 40.

As shown in FIG. 2E, the storage node contact mask is stripped and cleaned, an insulating layer (nitride layer) for the storage node contact spacer is deposited on the front surface, and the spacer is etched (using an etch back) to form the storage node contact hole. A storage node contact spacer (not shown) is formed in contact with both side walls.

Subsequently, the plug polysilicon layer is deposited until the storage node contact hole is filled, and then the CMP (hereinafter referred to as 'SNC CMP') is performed until the upper surface of the bit line hard mask nitride layer 36 is exposed to the storage node contact plug. The separation of 43 is completed.

3 is a photograph showing a profile of a bit line pattern according to an exemplary embodiment of the present invention, and it can be seen that the loss of the bit line hard mask nitride film is small.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the buffer oxide layer is further deposited on the bit line pattern to reinforce the weak profile of the bit line pattern, thereby minimizing the etch loss of the bit line hard mask nitride layer, thereby preventing the self-aligned contact process from failing. There is.

In addition, the present invention forms a storage node contact hole with a wide entrance using a line type storage node contact mask, and increases the open area with a subsequent storage node by forming a storage node contact plug therein without forming pad polysilicon. This can increase the overlay margin with the storage node.

In addition, the present invention has the effect of reducing the cost by forming a storage node contact mask of the line type to form a storage node contact mask only with KrF photoresist without applying a separate storage node contact hard mask by forming a line type storage node contact mask.

Claims (6)

Forming a second insulating layer on the structure in which the landing plug contact is formed in the first insulating layer; Forming a bit line pattern stacked on the predetermined surface of the second insulating layer in the order of the bit line conductive layer and the bit line hard mask; Forming a third insulating film over the entire surface until filling the bit line patterns; Planarizing the third insulating layer until an upper portion of the bit line pattern is exposed; Partially etching the second insulating layer to form first holes; Expanding the side of the primary hole; Forming a buffer oxide layer covering an upper portion of the bit line pattern exposed by the primary hole in which the side surface is extended; Performing secondary etching until the surface of the landing plug contact is exposed to form secondary holes; And Forming a storage node contact embedded in the storage node contact hole formed of the first and second holes; Storage node contact forming method of a semiconductor device comprising a. The method of claim 1, Forming the buffer oxide film, And forming a material having a weak step coverage such that the thickness at the top and the edge of the bit line pattern is thicker than the thickness at the remaining sidewalls. The method of claim 2, The buffer oxide film is a storage node contact forming method of a semiconductor device, characterized in that formed by PECVD. The method of claim 3, The buffer oxide film is formed to a thickness of 500 ~ 1000 GPa storage node contact method for a semiconductor device. The method of claim 1, The first and second etching, the storage node contact forming method of a semiconductor device, characterized in that using a line type storage node contact mask as an etching barrier. The method of claim 5, The storage node contact mask is formed of KrF photoresist, characterized in that the storage node contact plug formation method of a semiconductor device.

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