KR100875674B1 - Method for fabricating semiconductor device prevented capacitor leakage - Google Patents

Abstract

The method for fabricating semiconductor device is provided to prevent the sharp profile which is a cause of the leakage source by securing enough the rounded bottom profile of the open area for bottom electrode. The method for fabricating the semiconductor device comprises as follows. A step is for forming the etching barrier film(24) at the upper part of the substrate(21) in which the contact plug(23) is formed. A step is for forming the insulating layer(25) on the etch barrier film. A step is for forming the open area by etching the insulating layer. A step is for etching the etching barrier film under the open area.

Description

Semiconductor device manufacturing method to prevent capacitor leakage {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE PREVENTED CAPACITOR LEAKAGE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a three-dimensional capacitor.

In general, there is a method of preventing a loss of charge accumulated in a capacitor in order to prevent power loss in a DRAM. A method of preventing a loss of charge includes a method of periodically refreshing a charge to secure characteristics. Another method is to increase the amount of charge accumulated by the capacitor, thereby increasing the refresh time and preventing power loss due to the refresh.

In order to increase the amount of charge accumulated by the capacitor, a method of increasing the amount of charge that can be accumulated by changing a dielectric film having a high dielectric constant such as a zirconium oxide film in a hafnium oxide film is used.

In addition, as a method of increasing the amount of charge accumulated by increasing the effective surface area, there is a method of forming a capacitor structure in a three-dimensional structure such as a concave and cylinder structure.

1A and 1B are schematic views illustrating a capacitor manufacturing method according to the prior art. And, Figure 2a is a photograph showing a sharp profile of the lower electrode according to the prior art, Figure 2b is a photograph showing a void according to the prior art.

Referring to FIG. 1A, a first insulating layer 12 is formed on a substrate 11 and a contact plug 13 penetrating the first insulating layer 12 is formed. Thereafter, the etching barrier layer 14 and the second insulating layer 15 are stacked on the first insulating layer 12, and the second insulating layer 15 and the etching barrier layer 14 are sequentially etched to form the contact plug 13. To form an open region 16 exposing the opening.

As shown in FIG. 1B, after depositing a conductive film on the second insulating layer 12 having the open region 16, a lower electrode 17 may be formed in the open region by performing a lower electrode separation process such as front etching. do.

In a subsequent step, the dielectric film and the upper electrode are formed after the removal of the second insulating film 12 to form a cylinder, and the dielectric film and the upper electrode are formed while the second insulating film 12 is left to have a concave structure. .

As described above, in the prior art, the process of forming the open area is essentially performed for the concave structure or the cylinder structure.

However, in the related art, when the aspect ratio of the open area increases, a change in profile occurs according to the depth of the open area. That is, it is inevitable that a cuspidal phenomenon in which the line width becomes smaller at the lower portion than the upper portion is formed at the time of forming the open region.

As such, when a sharp open area is formed, not only the bottom profile becomes sharp during the deposition of the conductive film to be used as a subsequent lower electrode (see 'A' in FIG. 2A), but in severe cases, the conductive film is open. It is not deposited at the bottom of the (Void) causes the void (see 'B' of Figure 2b). In addition, even when deposited at the bottom, there is a problem that the lower electrode having a sharp profile acts as a leakage source during subsequent deposition of the dielectric film.

The present invention has been made to solve the above problems of the prior art, and to provide a method of manufacturing a capacitor that can prevent the sharp profile of the open area that causes the leakage source during the subsequent lower electrode and dielectric film deposition have.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming an etching barrier film on the substrate on which the contact plug is formed; Forming an insulating film on the etching barrier film; Etching the insulating film to form an open region; Etching the etching barrier layer under the open area; And forming a lower electrode in the open region, wherein etching the etch barrier layer controls a ratio of bottom power and top power while simultaneously adjusting pressure so that a chemical isotropic etch is performed. The etching of the etching barrier layer may include applying bottom power and top power at least six times larger than the bottom power, wherein the bottom power is 50. It is characterized by using ~ 100W, the top power is 600 ~ 800W, the pressure is characterized by using a pressure of 20 ~ 50mTorr, the etching barrier film is characterized in that using a silicon nitride film. .

The present invention can secure a wide round bottom profile of the open region in which the lower electrode is to be formed by chemically isotropic etching while controlling pressure and power (a ratio of bottom power and top power) during etching of the etching barrier film. Accordingly, there is an effect that can prevent the sharp profile that causes the leakage source during the subsequent deposition of the lower electrode and the dielectric film.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, a first insulating layer 22 is formed on the substrate 21. In this case, the first insulating layer 22 may be an oxide layer, and the landing plug contact may be previously formed on the substrate 21. Although not shown, a process such as a word line or a bit line may be performed between the substrate 21 and the first insulating layer 22.

Subsequently, the first insulating layer 22 is etched to form a contact hole, and then a contact plug 23 embedded in the contact hole is formed. In this case, the contact plug 23 is a storage node contact plug.

For example, the contact plug may be formed by depositing a polysilicon layer, forming a chemical mechanical polishing (CMP) process, and an etch back process after forming the contact hole. In addition, a laminated film of a titanium film Ti and a titanium nitride film TiN may be formed on the surface of the contact plug.

Subsequently, the etching barrier film 24 and the second insulating film 25 are stacked on the first insulating film 22. In this case, the etching barrier film 24 is a nitride film and the second insulating film 25 is an oxide film. Preferably, the second insulating film 25 is at least one selected from PE-TEOS, BPSG, PSG, or USG, and the etching barrier film 24 is a silicon nitride film (Si ₃ N ₄ ).

As shown in FIG. 3B, after forming the polysilicon film 26 as a hard mask film on the second insulating film 25, an SN mask (shown through a known photolithography process on the polysilicon film 26) is shown. The polysilicon film 26 is etched. At this time, the etching of the polysilicon film 25 is selected for the second insulating film 25 which is an oxide film material below by using HBr or Cl ₂ gas alone or by using a mixed gas of HBr / Cl ₂ / O ₂ . Increase rain

Thereafter, the second insulating layer 25 is etched to form the open region 26 by using the polysilicon layer 26 as an etch barrier so that the etching is stopped on the etch barrier layer 24. At this time, the etching of the second insulating layer 25 is a dry etching method, the selectivity to the etching barrier layer 24, the second insulating layer 25 is an oxide material and the nitride film material under the second insulating layer 25. To increase this, a mixture of CHF ₃ and C ₄ F ₈ can be used.

As shown in FIG. 3C, the remaining polysilicon layer 26 is removed through an etchback process. At this time, by using HBr or Cl ₂ gas alone or by using a mixed gas of HBr / Cl ₂ / O ₂ , the selectivity is increased with respect to the second insulating film 25 which is an oxide film material.

Subsequently, after the etch back process of the polysilicon film, the etching barrier film 24 remaining at the bottom of the open region 27 is etched in-situ to expose the surface of the contact plug 23. At this time, in order to increase the selectivity with respect to the contact plug 23 and the second insulating film 25, C _x F _y- based gas and oxygen gas containing carbon (C) and fluorine (F) are used as an etching gas. In addition, the etching of the etching barrier layer 24 proceeds as follows so as to secure a chemical isotropic etch characteristic in which the profile of the bottom portion of the open area 27 is wide (reference numeral '27B').

First, the etching of the etching barrier layer 24 is plasma etching, and as the plasma etching apparatus for this, an inductively coupled plasma (ICP), an electron cyclotron resonance (ECR), a microwave (microwave), or a capacitively coupled plasma (CCP) may be used. Can be.

In addition, while adjusting the pressure so that the chemical isotropic etching is performed, the ratio of bottom power and top power is controlled. For example, the etching of the etching barrier layer may be performed by applying bottom power and top power at least six times larger than bottom power.

Preferably, the pressure is 20-50 mTorr, the top power (or source power) is 600-800 W, and the bottom power (or bias power) is 50-100 W. In addition, the etching gas uses a mixed gas of a C ₂ F ₆ gas and an oxygen (O ₂ ) gas. In addition, the etching time is 40 seconds.

When the etching barrier layer 24 formed of the silicon nitride layer is etched under the above conditions, the bottom portion of the open area 27 has a rounded profile 27B. On the other hand, reference numeral 27A is a profile of the bottom portion of the open area according to the prior art it can be seen that the closer to the contact plug becomes narrower and sharper. As will be described later, the reason why the profile 27B is wider than in the prior art is that the chemical isotropic etching proceeds by reducing the bottom power while increasing the pressure and the top power.

As shown in FIG. 3D, the lower electrode 28 is formed in the open area by depositing and etching the conductive film to be used as the lower electrode on the front surface including the open area. Here, the lower electrode 28 includes a titanium nitride film (TiN) and has a round profile with a wide bottom portion of the open area, so that a sharp profile is not generated when the titanium nitride film is deposited.

Subsequently, the dielectric film 29 and the upper electrode 30 are sequentially formed on the lower electrode 28. Here, the dielectric film 29 uses a ZAZ (ZrO ₂ / Al ₂ O ₃ / ZrO ₂ ) structure to secure the capacitance.

Figure 4 is a photograph showing the result after the capacitor manufacturing according to an embodiment of the present invention. The result of FIG. 4 is the result after using the etching conditions of the above-mentioned etching barrier film.

Hereinafter, a description will be given with reference to FIGS. 4 and 2A. On the other hand, the result of FIG. 2A shows a case where the pressure in the etching of the etching barrier film is 5 mTorr, the top power is 400W, the bottom power is 250W, and the etching gas C ₂ F ₆ / O ₂ is performed. This recipe is called comparative recipe.

The result shown in FIG. 4 is a case where the pressure is 50mTorr, the top power is 600W, and the bottom power is 100W.

In the embodiment of the present invention, it can be seen that pressure, top power and bottom power are different from each other in comparison recipe. That is, the recipe according to the embodiment of the present invention can be seen that the pressure and the top power is larger, the bottom power is smaller than the comparative recipe. As such, if the bottom power is made smaller while the pressure and the top power are larger than the comparative recipe, the chemical isotropic etching characteristic (refer to reference numeral 'C') in which the etching profile is rounded as a whole is shown. In other words, when the pressure is increased and the bottom power is reduced, the chemical isotropic etching characteristic is increased by more chemical etching species than the physical etching species reaching the bottom of the open area.

As a result, an effect of widening the profile of the bottom portion of the open region is obtained by the chemical isotropic etching characteristic, it is possible to prevent the sharp profile is generated during the deposition of the subsequent lower electrode and the dielectric film.

As described above, by adjusting the etching conditions of the etching barrier film, it is possible to adjust the profile of the bottom portion of the open area in a round shape, thereby suppressing the generation of the sharp profile as shown in FIG. It is possible to eliminate leakage sources that may occur when the dielectric film is deposited.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1a and 1b schematically show a method of manufacturing a capacitor according to the prior art.

Figure 2a is a photograph showing a pointed profile of the lower electrode according to the prior art.

Figure 2b is a photograph showing the voids according to the prior art.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Figure 4 is a photograph showing the result after the capacitor manufacturing according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 first insulating film

23: contact plug 24: etching barrier film

25: second insulating film 26: polysilicon film

27: open area 28: lower electrode

29 dielectric layer 30 upper electrode

Claims (10)

delete Forming an etching barrier layer on the substrate on which the contact plug is formed; Forming an insulating film on the etching barrier film; Etching the insulating film to form an open region; Etching the etching barrier layer under the open area; And Forming a lower electrode in the open region; The etching of the etch barrier layer may include adjusting a pressure such that a chemical isotropic etch is performed while controlling a ratio of bottom power and top power. The method of claim 2, The etching of the etching barrier layer may include: A method of manufacturing a semiconductor device proceeding while applying bottom power and Top power at least six times larger than the bottom power. The method according to claim 2 or 3, The bottom power is a semiconductor device manufacturing method using 50 ~ 100W. The method according to claim 2 or 3, The top power is a semiconductor device manufacturing method using 600 ~ 800W. The method of claim 2, The pressure is a semiconductor device manufacturing method using a pressure of 20 to 50mTorr. The method of claim 2, The etching barrier film is a semiconductor device manufacturing method using a silicon nitride film. The method of claim 7, wherein The etching of the etching barrier layer may include: A method of manufacturing a semiconductor device that proceeds using a mixture of C ₂ F ₆ and O ₂ . The method of claim 2, The forming of the open region may be performed using a polysilicon layer as a hard mask, and the polysilicon layer may be removed by etching back the in-situ layer before etching the etching barrier layer. The method of claim 2, The insulating film includes a semiconductor device manufacturing method.

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