KR100844982B1 - Method of fabrication capacitor - Google Patents

Abstract

The present invention is to provide a method of manufacturing a capacitor suitable for suppressing the bridge between devices and to increase the capacitance, the present invention is to form an interlayer insulating film on a semiconductor substrate, the semiconductor substrate through the interlayer insulating film Forming a contact connected to the contact; forming a separation oxide having a vertical dopant concentration gradient on a front surface of the contact including the contact; forming a primary opening to expose the contact by plasma etching the separation oxide; Further etching the secondary opening to form a secondary opening having a sidewall slope according to the dopant concentration gradient, and forming a lower electrode in the secondary opening.

Capacitor, Separation Oxide, Concentration Gradient, Dopant, Silicon Oxide, Gradient, BOE

Description

Method of manufacturing a capacitor {Method of fabrication capacitor}             

1A to 1B are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art;

2A to 2D are cross-sectional views illustrating a method of manufacturing a concave capacitor according to an embodiment of the present invention;

3 is a view showing a concentration profile of the separated oxide according to the vertical height,

4 is a view comparing the etching rate of the silicon oxide film according to the ratio of NH ₄ F in the BOE,

5A to 5C are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 interlayer insulating film

23: contact 24: etch stop

25: separation oxide 26a: secondary opening

27: lower electrode

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.

Increasing integration in semiconductor devices including DRAM increases electrode surface area with HSG (Hemispherical Silicon Grain) using 3D structural change or limited microstructure of polycrystalline polysilicon thin film to increase capacitance in order to increase capacitance. Or a method of replacing with a high dielectric material having a high dielectric constant.

In particular, the development of high-k dielectric materials requires a lot of time and effort because of the development of the film formation method and securing characteristics such as thickness reduction and increase of step coverage for application to highly integrated devices having a three-dimensional structure. It is necessary.

Accordingly, the surface area of the capacitor is increased by applying the selective metastable polysilicon (SMPS) process to increase the surface area of the thin film by selectively uneven the surface of the silicon thin film used as an electrode by using the microstructure of the polycrystalline polysilicon thin film. As the integration degree increases, the thickness of the dielectric film gradually decreases, whereas the leakage current increases due to the local stepping failure of the dielectric film formed on the electrode having the surface irregularities of the electrode. There is a problem that deterioration acts as a cause of deterioration and failure of device characteristics.                         

Therefore, the recent capacitor solves the problem caused by leakage current by using a tantalum oxide film (Ta ₂ O ₅ ) with a higher dielectric constant than a typical ONO and NO dielectric film in a cylinder or trench type lower electrode. Doing.

However, in order to increase the degree of integration in a small area, a three-dimensional structure having an aspect ratio of 10 or more is required, but limitations in forming a part where the electrode is formed by reducing the area between the capacitor and the lower plug and dry etching It has been difficult to form a cylindrical pattern, and to solve this problem, a method of forming a wetted separation oxide between capacitors into a double material having a difference in wet etching rates has been proposed.

1A to 1B are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.

As shown in FIG. 1A, after forming the interlayer insulating film 12 on the semiconductor substrate 11 on which the transistor including the source / drain regions is formed, the interlayer insulating film 12 is etched to contact the semiconductor substrate 11. Form a hole. At this time, the portion exposed after the formation of the contact hole is the source / drain region of the transistor.

Next, a contact plug 13 for electrically connecting the lower electrode of the capacitor and the source / drain region of the transistor is buried in the contact hole, and then the isolation oxides 14a and 14b, which are separators between the capacitors, are formed on the interlayer insulating film 12. ). Here, the separation oxides 14a and 14b are stacked on the lower oxide 14a and the upper oxide 14b having different wet etching rates, and the lower oxide 14a has a faster wet etching rate than the upper oxide 14b.                         

Next, a photoresist film is applied on the upper oxide 14b and patterned by exposure and development to form a photoresist pattern (not shown) defining a capacitor region. Then, the photoresist pattern is etched with an upper oxide 14b and a lower oxide. Dry etch 14a to form an opening 15 defining a capacitor region exposing the contact plug 13.

Next, before the lower electrode is formed, pre-cleaning is performed, but wet cleaning is performed. At this time, since the lower oxide 14a and the upper oxide 14b have different wet etching speeds, in particular, the wet etching speed of the lower oxide film 14a is faster, the bottom of the opening 15 is wider than the inlet.

As shown in FIG. 1B, the lower electrode conductive film is deposited on the entire surface including the pre-cleaned opening 15, and the conductive film is selectively removed to leave the lower electrode 16 only in the opening 15.

However, in the above-described prior art, the double separation oxides 14a and 14b having different wet etching rate characteristics have interfaces, which induce a capillary phenomenon in the pre-cleaning wet etching process before the lower electrode 16 is formed. As a result, a fine bridge 17 between the lower electrodes 16 may be caused, and such a bridge may have a fatal effect on device characteristics.

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method of manufacturing a capacitor suitable for suppressing the occurrence of bridges between devices and increasing the capacitance.

A method of manufacturing a capacitor of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate, through the interlayer insulating film to form a contact connected to the semiconductor substrate, perpendicular to the front surface including the contact Depositing a separation oxide having a dopant concentration gradient, plasma etching the separation oxide to form a primary opening exposing the contact, and further etching the primary opening to incline the sidewalls according to the dopant concentration gradient Forming a secondary opening having a secondary opening, and forming a lower electrode in the secondary opening, wherein the separation oxide has a dopant concentration at an initial deposition stage and a deposition completion stage lower than a dopant concentration during deposition. In the forming of the secondary opening, the etching rate may vary according to the dopant concentration gradient. It is characterized by using a solution or gas having.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a method of manufacturing a concave capacitor according to a first embodiment of the present invention.                     

As shown in FIG. 2A, after forming the interlayer insulating film 22 on the semiconductor substrate 21 on which transistors (not shown) including the source / drain regions are formed, the interlayer insulating film 22 is etched to etch the semiconductor substrate 21. To form a contact hole.

Next, a contact plug 23 for electrically connecting the lower electrode of the capacitor and the source / drain region is buried in the contact hole, and then the separation film, which is a separator between the etch stop film 24 and the capacitor, is formed on the interlayer insulating film 22. Oxide 25 is formed. Here, the etch stop film 24 uses a silicon nitride film, and the separation oxide 25 is a single layer having a concentration gradient X of the dopant according to the vertical height d. That is, at the initial stage of deposition, it has a low dopant concentration (minimum; min.) But at a certain thickness has a high dopant concentration (maximum; max.), And as the thickness increases, the dopant concentration decreases again.

3 shows the concentration profile of the separated oxide according to the vertical height, having the lowest dopant concentration at the beginning of deposition, and gradually increasing the dopant concentration as the deposition thickness is increased, but the dopant concentration is again increased above a certain thickness (2500Å). Decreases. That is, the concentrations of the initial deposition and the completion stage of deposition are lower than the dopant concentration during the deposition process.

Referring again to FIG. 2A, the formation of the separation oxide 25 having the dopant concentration gradient X is deposited by varying the dopant concentration by chemical vapor deposition (CVD), and the dopant concentration gradually decreases as the deposition proceeds. To lose. At this time, the interface should be proceeded in-situ so as not to generate an interface due to a change in concentration, and when the concentration difference with the etch stop layer 24 under the separation oxide 25 becomes large, the separation oxide 25 is etched. Since wet etchant penetrates quickly through the interface of the stop layer 24, the lowest dopant concentration (min.) Is set at the beginning of deposition.

As the doped silicon oxide film (doped SiO ₂ ) as the separation oxide 25, the doped silicon oxide film is deposited using a chemical vapor deposition apparatus (CVD) in the form of a conveyor. In this case, the dopant concentration can be adjusted for each injector, and as the deposition proceeds, there is a movement between the injectors.

In conventional low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) devices, a dopant ramp up / down process is added or a dopant source is added to prevent sudden concentration changes between processes having different concentrations. Adjust the flow rate of the gas so that concentration gradients occur gradually.

Meanwhile, as the separation oxide 25, one selected from a doped silicon oxide film composed of BPSG, BSG, and PSG, or a combination of at least two of them is used.

As shown in FIG. 2B, through the series of lithography and etching processes, the separation oxide 25 is etched to stop the etching in the etch stop layer 24, and the etch stop layer 24 is subsequently etched to form a contact plug ( A primary opening 26 is formed to expose 23. For example, after the photoresist is coated on the separation oxide 25, patterning is performed by exposure and development to form a photoresist pattern defining a region in which the lower electrode is to be formed. The etch stop layer 24 is then etched to form a primary opening 26 that defines the region where the capacitor is to be formed.

At this time, etching of the separation oxide 25 is performed through a dry etching process, for example, using a gas such as carbon fluoride, carbon chloride, carbon halide, and the like, and has a strong straightness. Plasma etching method is used. Accordingly, the selectivity between the photoresist pattern and the separation oxide 25 is secured, but the selectivity according to the dopant concentration of the separation oxide 25 is not secured, so that the primary opening 26 does not exhibit sidewall inclination according to the dopant concentration.

As illustrated in FIG. 2C, the primary opening 26 is additionally etched with an etchant having an etching rate difference according to the dopant concentration gradient of the separation oxide 25 to have a sidewall slope according to the concentration gradient. The difference opening 26a is formed. At this time, the additional etching is wet etching using a solution containing fluorine (F) ions such as HF solution, BOE or dry etching using a gas containing HF.

As such, when fluorine-containing solution or HF gas is used, the etching rate is different depending on the concentration of the dopant in the separation oxide 25, unlike the plasma etching process when forming the primary opening 26.

For example, in the case of using BOE (Buffered Oxide Etchant), a mixture of HF and NH ₄ F, the etch selectivity of the doped silicon oxide film and the undoped silicon oxide film can be adjusted according to the ratio of NH ₄ F. The inclination can be adjusted according to the degree of integration of the device.

4 is a view comparing the etching rate (etch rate) of the silicon oxide film according to the concentration (wt%) of NH ₄ F in the BOE.

Referring to FIG. 4, the thermal oxide film, which is an undoped silicon oxide film, has a small change in etching rate according to the concentration ratio of NH ₄ F, whereas the etch rate change of BPSG and TEOS, which is a doped silicon oxide film, has a large change in concentration ratio of NH ₄ F.

In addition, the etching rate of BPSG and TEOS is greater than that of the thermal oxide layer.

In addition, when the concentration ratio of NH ₄ F in the BOE is smaller, the etching rate is higher, and when the concentration ratio of NH ₄ F is higher, the etching rate is lower, and the NH ₄ F concentration ratio is lower (lower NH _4). In F), the etching rate difference between the oxide films is very large, but when the NH ₄ F concentration ratio is high (high NH ₄ F), the etching rate difference between the oxide films is small.

On the other hand, the additional etching process using a solution containing fluorine may be combined into a pre-cleaning process performed before the conductive film deposition for the lower electrode, or may be separately performed before the pre-cleaning process.

In addition, the separation oxide 25 remaining after the additional etching remains at a minimum width for isolation between neighboring lower electrodes, and preferably maintains a width t of 50 kPa or more.

As shown in FIG. 2D, after pre-cleaning, the lower electrode conductive film is deposited on the entire surface including the secondary openings 26a, and the conductive film is selectively removed to remove the lower electrode 27 only in the secondary openings 26a. ) Is left.

For example, the lower electrode 27 is formed by first depositing a conductive film for the lower electrode and then etching back or chemical mechanical polishing the conductive film until the surface of the separation oxide is exposed.

The concave capacitor is formed through a series of processes as described above.

5A to 5C are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to a second embodiment of the present invention.

As shown in FIG. 5A, after forming the interlayer insulating film 32 on the semiconductor substrate 31 on which transistors (not shown) including source / drain regions are formed, the interlayer insulating film 32 is etched to etch the semiconductor substrate 31. To form a contact hole.

Next, a contact plug 33 for electrically connecting the lower electrode of the capacitor and the source / drain region is buried in the contact hole, and then the separation film, which is a separator between the etch stop film 34 and the capacitor, is formed on the interlayer insulating film 32. Oxide 35 is formed. Here, the etch stop layer 34 uses a silicon nitride layer, and the separation oxide 35 is a single layer having a concentration gradient X of the dopant according to the vertical height d. In other words, it has a low dopant concentration (min.) At the beginning of the deposition, but has a high dopant concentration (max.) At a certain thickness, and as the thickness increases, the dopant concentration decreases again. That is, the concentrations of the initial deposition and the completion stage of deposition are lower than the dopant concentration during the deposition process.

On the other hand, using the doped silicon oxide film (doped SiO ₂ ) as the separation oxide 35, the doped silicon oxide film is deposited using a chemical vapor deposition apparatus (CVD) in the form of a conveyor. In this case, the dopant concentration can be adjusted for each injector, and as the deposition progresses, there is a movement between the injectors, which is suitable for the gradual change in concentration.

In conventional low pressure chemical vapor deposition (LPCVD) or plasma chemical vapor deposition (PECVD) devices, a dopant ramp-up / down process is added or a flow rate of the dopant source gas is adjusted so that abrupt concentration changes do not occur between processes having different concentrations. The concentration gradient occurs gradually.

On the other hand, as the separation oxide 35, one selected from a doped silicon oxide film composed of BPSG, BSG, and PSG, or a combination of at least two or more of them is used.

Next, the separation oxide 35 is etched to stop the etching in the etch stop layer 34 through a series of lithography and etching processes, and the etch stop layer 34 is subsequently etched to expose the contact plug 33. The primary opening 36 is formed. For example, after the photoresist is coated on the separation oxide 35, patterning is performed by exposure and development to form a photoresist pattern defining a region where the lower electrode is to be formed, and the photoresist pattern is etched by etching the separation oxide 35 using an etching mask. As a result, the etch stop film 34 is etched to form a primary opening 36a.

At this time, the etching of the separation oxide 35 is performed through a dry etching process, for example, using a gas such as carbon fluoride, carbon chloride, carbon halide, and the like, and has a strong straightness. Plasma etching method is used. Therefore, the selectivity between the photoresist pattern and the separation oxide is secured, but the selectivity according to the dopant concentration of the separation oxide is not secured, so that the primary opening 36a does not exhibit the sidewall slope according to the dopant concentration.

Next, the primary opening 36a is further etched to form a secondary opening 36b having a sidewall slope according to the concentration gradient. In this case, the additional etching is performed using a solution containing fluorine ions such as HF solution or BOE or a gas containing fluorine such as HF gas.

As such, when the fluorine-containing solution or HF gas is used, the etching rate is different depending on the concentration of the dopant in the separation oxide 35, unlike the plasma etching process when the primary opening 36a is formed.

Meanwhile, the additional etching process may be combined with a pre-cleaning process performed before the deposition of the conductive film for the lower electrode, or may be separately performed before the pre-cleaning process.

The separation oxide 35 remaining after the additional etching remains at a minimum width for isolation between neighboring lower electrodes, and preferably maintains a width t of 100 kPa or more.

As shown in FIG. 5B, after pre-cleaning, the lower electrode conductive film is deposited on the entire surface including the secondary opening 36b, and the conductive film is selectively removed to remove the lower electrode 37 only in the secondary opening 36b. ) Is left.

For example, the lower electrode 37 is formed by first depositing a conductive film for the lower electrode and then etching back or chemical mechanical polishing the conductive film until the surface of the separation oxide is exposed.

As shown in FIG. 5C, the cylindrical capacitor is completed by removing the separation oxide 35 using a solution containing fluorine ions or HF gas.

In the first and second embodiments described above, the occurrence of bridges is prevented by suppressing the interfacial generation in the separation oxide and the interfacial formation between the separation oxide and the etch stop layer, and the surface area of the capacitor is increased by forming the lower electrode having sidewall slope. By adjusting the dopant concentration gradient of the separation oxide, vertical etching profiles such as bowing or slopes at the time of opening formation can be suppressed.

In the above-described embodiment, the vertical etching profile is formed when the primary opening 26 is formed, but it is known that the bottom has a narrower profile than the inlet after the etching process. Even so, the sidewall slope of the secondary opening 26a appears in accordance with the concentration gradient of the dopant.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of improving the electrical characteristics of the capacitor and the device by suppressing the occurrence of the fine bridge between the capacitor.

In addition, by forming a lower electrode having sidewall slopes, it is possible to increase the surface area of the capacitor and to improve the vertical etching profile generated when forming the capacitor pattern by adjusting the dopant concentration gradient of the separation oxide.

Claims (12)

Forming an interlayer insulating film on the semiconductor substrate; Forming a contact penetrating the interlayer insulating film and connected to the semiconductor substrate; Depositing a separation oxide having a vertical dopant concentration gradient on the front surface including the contact; Plasma etching the separation oxide to form a primary opening exposing the contact; Further etching the primary opening to form a secondary opening having a sidewall slope according to the dopant concentration gradient; And Forming a lower electrode in the secondary opening, The separation oxide is a capacitor manufacturing method, characterized in that the dopant concentration of the initial deposition and the deposition completion step is lower than the dopant concentration during the deposition process. The method of claim 1, Forming a secondary opening having the sidewall slope, Method for producing a capacitor, characterized in that using a solution or gas having a different etching rate according to the dopant concentration gradient of the separation oxide. The method of claim 2, The solution is a method of manufacturing a capacitor, characterized in that using the HF solution or BOE. The method of claim 2, Wherein the gas comprises HF gas. The method of claim 1, After forming the lower electrode, Removing the separation oxide; And Sequentially forming a dielectric film and an upper electrode on the lower electrode Method for producing a capacitor, characterized in that it further comprises. The method of claim 5, Removing the separation oxide, A method for producing a capacitor, comprising using a solution containing fluorine ions or HF gas. The method of claim 1, After forming the lower electrode, And sequentially forming a dielectric film and an upper electrode on the lower electrode. delete The method of claim 1, In the step of forming the separation oxide, The dopant concentration at the beginning of the formation of the separation oxide is a low concentration so as to suppress the formation of the interface between the interlayer insulating film and the separation oxide. The method of claim 1, The separation oxide is a method of producing a capacitor, characterized in that at least two or more of these selected from the doped silicon oxide film consisting of BPSG, BSG and PSG combined. The method of claim 1, Forming the secondary opening, A method of manufacturing a capacitor, characterized in that it is performed simultaneously with the pre-cleaning step performed before forming the lower electrode. The method of claim 1, After forming the secondary opening, Capacitor manufacturing method further comprising the step of pre-cleaning before forming the lower electrode.

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