KR20020030481A - Method of fabricating a capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to increase capacitance, by making the inside of a lower electrode made of undoped amorphous silicon and by forming the lower electrode of a jar type so that a dielectric layer formation portion is increased. CONSTITUTION: An impurity diffusion region is formed on a semiconductor substrate(20). A lower electrode formation region is defined in the substrate. The first insulation layer(21) is formed on the substrate. A conductive plug(22) penetrating the first insulation layer and adjacent to the impurity diffusion region is formed on the substrate. An etch stop layer(23) and the first sacrificial layer are sequentially formed on the conductive plug and the first insulation layer. The second sacrificial layer is made of a material of which the etch selectivity regarding the first sacrificial layer is high. A predetermined depth of the second sacrificial layer, the first sacrificial layer and the etch stop layer in the lower electrode formation portion is removed to form an opening exposing a predetermined portion of the first insulation layer. A predetermined portion of the first sacrificial layer is removed to extend the space of the opening. The first amorphous silicon layer(26) and the second amorphous silicon layer(27) are stacked in the opening to form a lower electrode pattern. The second and first sacrificial layers are removed. A protrusion is formed on the exposed lower electrode pattern. A dielectric layer and an upper electrode are formed on the lower electrode pattern.

Description

Method of fabricating a capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In particular, the lower electrode pattern is formed in a stacked structure of doped polysilicon and undoped amorphous silicon to differentiate the hemispherical silicon grains and form the lower electrode in a jar shape. The present invention relates to a method of manufacturing a capacitor lower electrode of a semiconductor device, which prevents the formation of an upper point of an upper electrode, prevents a short circuit between adjacent lower electrodes, and maximizes an effective surface area.

As the semiconductor devices are highly integrated, the area occupied by the capacitor also decreases as the size of the cell decreases. Therefore, the surface of the lower electrode is irregularly formed to secure the required capacitance.

However, when the pattern of the lower electrode is formed in a cylinder form or a crown structure, the upper form of the lower electrode becomes sharp.

In the capacitor manufacturing process of the prior art, a method of forming a lower electrode having a cylinder or crown structure is etched back after depositing a conductive layer to form a lower electrode pattern, and then a sacrificial layer oxide film is removed by wet etching. At this time, the upper portion of the lower electrode pattern has a sharp pointed shape due to the etch back.

In order to secure the required surface area of the lower electrode, protrusions are formed on the surface of the lower electrode using hemisphere silicon grain (HSG).

In other words, one time HSG process is performed to form surface area enhanced silicon (hereinafter referred to as SAES).

The SAES process is used as a general process to increase the surface area of the lower electrode. The key to this process is to maximize the density and grain size of the SAES while maintaining the electrical characteristics of the capacitor to obtain the maximum capacitance.

However, in the case of maximizing the size of the silicon grain, the silicon grains formed on the peaks of the lower electrode are vulnerable to physical stress, so the recessed portion is formed in the lower part of the cylinder shape in the subsequent process such as cleaning before doping and dielectric film deposition. It may be separated from the electrode pattern, resulting in a decrease in capacitance and shorting neighboring devices.

1A to 1E are cross-sectional views of a capacitor lower electrode manufacturing process of a semiconductor device according to the prior art.

Referring to FIG. 1A, after forming an impurity diffusion region (not shown) doped with a high concentration of N-type impurities such as acene or phosphorus (P) on a P-type semiconductor substrate 10, After forming an oxide film on the first insulating layer 11 by applying a photoresist (not shown) on it, and removing a predetermined portion of the first insulating layer by a photolithography method A contact hole exposing the impurity diffusion region is formed.

After removing the photoresist pattern, chemical vapor deposition (hereinafter, CVD) of the first polycrystalline silicon layer doped with impurity P ions to the first conductive layer on the first insulating layer 11 to sufficiently fill the contact hole is performed. Deposition).

Then, a contact plug 12 for filling a contact hole is formed by performing an etch back or CMP process on the first polysilicon layer.

Next, a nitride film is deposited on the upper surface of the first insulating layer 11 including the exposed surface of the plug 12 by the etching stop layer 13 by chemical vapor deposition (CVD).

Referring to FIG. 1B, an oxide film 14 is formed by CVD on a etch stop layer 13 made of a nitride film using a first sacrificial film 14.

After the photoresist is applied on the first sacrificial layer 14, a photoresist pattern (not shown) is formed to expose a portion where the lower electrode of the capacitor is to be formed.

Next, the first sacrificial layer and the etch stop layer of the portion that are not protected by the photoresist pattern are sequentially removed to form an opening for exposing the upper surface of the plug 12 to provide a space for forming the lower electrode.

Then, the photoresist pattern is removed.

Referring to FIG. 1C, the lower electrode pattern serving as a storage electrode is formed on the exposed surface of the remaining first sacrificial layer 14 by including the exposed surface of the side surface and the lower surface of the opening, that is, the plug 12. It is formed by depositing α-silicon layer 15, which is amorphous silicon. In this case, the α-silicon layer is formed of amorphous silicon doped with impurities in order to have conductivity, and has a predetermined thickness such that a stable lower electrode pattern can be formed without completely filling the opening.

Then, the second sacrificial layer 16 is deposited to sufficiently fill the opening in which the α-silicon layer 15 is formed with an insulating layer having an etching selectivity similar to that of the first sacrificial layer 14 so as to leave the lower electrode pattern in the opening. To form.

In this case, the second sacrificial film 16 is formed by thickly depositing an oxide film such as SOG (Silicon On Glass), BPSG (Boro Phospho Silicate Glass), or PSG (Phospho Silicate Glass).

Next, the first sacrificial layer 16 is formed only on the open portion of the second sacrificial layer 16 to expose the surface of the α-silicon layer 15 formed on the first sacrificial layer 14 by performing an etch back process. Is left. In this case, the remaining first sacrificial layer 16 serves to protect the lower electrode pattern forming portion from etching during the etching of the lower electrode pattern forming on the α-silicon layer 15.

Referring to FIG. 1D, an α-silicon layer on the upper surface of the first sacrificial layer 14 is subjected to an etch back process using the remaining second sacrificial layer 16 as an etching mask. Then, the lower electrode pattern 15 is formed. At this time, the upper edge of the formed lower electrode pattern 15 is etched by the etch back process, which is thinner than the remaining lower electrode pattern, which is vulnerable to physical stress.

Referring to FIG. 1E, the remaining first and second sacrificial layer films are removed by wet etching to expose the lower electrode pattern 15.

Then, in order to form a surface area expansion silicon (SAES) that extends the surface area of the lower electrode pattern 15, a hemispherical silicon grain (HSG) 17, which is a protrusion 17, is formed on the surface of the lower electrode pattern 15. In this case, the hemispherical silicon grains 17 are formed by flowing SiH ₄ gas on the exposed surface of the lower electrode pattern 170.

However, the protrusion 17 formed at the peak portion of the lower electrode pattern 15 which is vulnerable to physical stress may be unstable and may easily be separated from the lower electrode pattern 15.

Then, in order to prevent the depletion phenomenon, if necessary, after removing the natural oxide film formed on the lower electrode surface, additional impurity ion implantation is performed on the lower electrode pattern 15 and the protrusion 17. This is advantageous as the incubation time for crystallization in terms of HSG formation is longer, and further doping is necessary because the incubation time is long, the deposition temperature of the silicon layer must be low or the doping concentration must be low.

Subsequently, although not shown, a dielectric film is formed by depositing Ta ₂ O ₅ having excellent dielectric constant on the surfaces of the final lower electrodes 15 and 17, and then performing post-treatment on the dielectric film in an oxygen atmosphere to improve the characteristics of the dielectric film. Make it good This is to form a molecular formula consisting of Ta ₂ O ₅ in order to obtain a dielectric constant value of an ideal dielectric film since the dielectric film is generally composed of Ta ₂ O _5-x .

A capacitor is manufactured by depositing a TiN layer on the surface of the dielectric film to form a metal plate electrode as an upper electrode.

However, in the above-described conventional capacitor manufacturing method, the silicon grains which are separated from the SAES formed in the cylindrical lower electrode pattern are easily separated from the lower electrode pattern due to the external physical impact. There is a problem of reducing the yield of the device by causing a short circuit (bridge phenomenon) between the cylinders, and there is a disadvantage in improving the refresh characteristics because there is a limit in the surface area increase because the cylinder portion of the lower electrode is simply formed in a flat shape.

Accordingly, an object of the present invention is to form a lower electrode pattern of a capacitor used for DRAM of a semiconductor device in a stacked structure of doped polysilicon and undoped amorphous silicon to differentiate the formation of hemispherical silicon grains and to form the lower electrode in a jar form. The present invention provides a method for fabricating a capacitor lower electrode of a semiconductor device, which prevents the formation of peaks on the lower electrode, prevents short circuits with neighboring lower electrodes, and maximizes an effective surface area.

For the above-mentioned object, the capacitor manufacturing method of the semiconductor device according to the present invention is characterized in that an impurity diffusion region is formed, a lower electrode formation portion is defined, a first insulating layer is formed, penetrates the first insulating layer and contacts the impurity diffusion region. Sequentially forming an etch stop layer and a first sacrificial layer on the plug and the first insulating layer of the semiconductor substrate on which the conductive plug is formed, and forming a second sacrificial layer made of a material having a high etching selectivity with the first sacrificial layer; Removing the second sacrificial layer, the first sacrificial layer, and the etch stop layer at a predetermined depth to form an opening exposing a predetermined portion of the first insulating layer including the plug surface; Removing the predetermined portion of the first sacrificial layer to expand the space of the opening, and sequentially applying the inner surface of the opening to the inner surface of the opening; Forming a lower electrode pattern comprising a undoped first amorphous silicon layer and a doped second amorphous silicon layer, removing the second sacrificial layer and the first sacrificial layer, and exposing the exposed lower electrode And forming a protrusion on the surface of the pattern, and sequentially forming a dielectric film and an upper electrode on the lower electrode pattern including the protrusion.

1A to 1E are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views of a capacitor manufacturing process of a semiconductor device according to the present invention.

According to the present invention, since the size of a cell becomes smaller as the device size is down-sized in a capacitor used in a semiconductor memory device or the like, the lower portion of a simple cylindrical or cylinder structure is used to increase the capacitance of the capacitor to improve the refresh characteristics of the device. Instead of the electrode, the side profile forms a jar-shaped lower electrode having irregularities.

In addition, the present invention forms a layer of amorphous silicon composed of doped amorphous silicon and undoped amorphous silicon for the selective deposition of hemispherical silicon grains for maximizing the surface area, so that the grain size is large inside the lower electrode pattern. Grains are formed and relatively small silicon grains are formed on the outer wall to prevent electrical shorts between adjacent lower electrodes.

In addition, the present invention suppresses the formation of hemispherical silicon grains by doping the undoped amorphous silicon portion of the upper peak portion of the lower electrode pattern made of amorphous silicon with a phosphorus (P) ion or the like to escape from the lower electrode pattern. The electrical short between the lower electrodes due to the silicon grains is prevented.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views of a capacitor lower electrode manufacturing process of a semiconductor device according to the present invention.

Referring to FIG. 2A, after the impurity diffusion region (not shown) is formed on the p-type silicon substrate 20, which is a semiconductor substrate, the dopant diffusion regions doped with n-type impurities such as acene or phosphorus (P) are highly doped. After forming an oxide film on the semiconductor substrate 20 with the first insulating layer 21 and applying a photoresist (not shown) thereon, a predetermined portion of the first insulating layer is formed by photolithography. Is removed to form a contact hole exposing the impurity diffusion region.

After removing the photoresist pattern, a polycrystalline silicon layer doped with impurity P ions as a first conductive layer on the first insulating layer 21 to sufficiently fill the contact hole is called chemical vapor deposition (hereinafter, referred to as CVD). ) Is deposited by the method.

Then, an etch back or CMP process is performed on the polysilicon layer to form a contact plug 22 filling the contact hole.

Next, a nitride film is deposited on the upper surface of the first insulating layer 21 including the exposed surface of the plug 22 by an etching stop layer 23 by chemical vapor deposition (CVD).

Referring to FIG. 2B, the oxide film 24 is formed by CVD on the etch stop layer 23 made of the nitride film with the first sacrificial film 24.

In addition, a second sacrificial layer 25 is formed on the first sacrificial layer 24 by using an insulating material having a large etching selectivity with the first sacrificial layer. In this case, the second sacrificial film 25 is formed by depositing an oxide film and a nitride film having a large visual selectivity by CVD.

After the photoresist is applied on the second sacrificial layer 25, a photoresist pattern (not shown) is formed to expose a portion where the lower electrode of the capacitor is to be formed.

Next, the second and first sacrificial layers and the etch stop layer of the portion not protected by the photoresist pattern are sequentially removed to provide a space for forming the lower electrode, and at the same time, to form an opening exposing the upper surface of the plug 22. do.

Then, the photoresist pattern is removed.

Referring to FIG. 2C, the inner space of the opening is expanded by removing the surface of the first sacrificial film 24 exposed by the opening by a predetermined thickness. In this case, since the second sacrificial layer 25 and the etch stop layer 23 are both formed of a nitride layer and the first sacrificial layer 24 is formed of an oxide layer, when the wet etching is performed in the opening to expand the inner space of the opening, The exposed portion of the sacrificial layer 24 is removed by a predetermined thickness.

Thus, the final shape of the opening will have a jar-shaped profile.

Referring to FIG. 2D, a first amorphous layer for forming a lower electrode pattern, which is a storage electrode, is formed on the remaining second sacrificial layer 25 including the exposed surface of the plug 22 and including side and bottom surfaces of the opening. The silicon layer 26 is formed by vapor deposition. In this case, the first amorphous silicon layer 26 may be formed by chemical vapor deposition of amorphous silicon doped with impurities such as phosphorus (P) ions to have conductivity, and may form a stable lower electrode pattern without completely filling the openings. It is assumed to have a predetermined thickness. Therefore, since the first amorphous silicon layer 26 is doped with an impurity, the size of the silicon grains is small when the hemispherical silicon grains are formed in a subsequent process.

Next, a second amorphous silicon layer 27 which is not doped with impurities is formed on the first amorphous silicon layer 26 including the inside of the opening to a thickness not filling the opening. In this case, since the second amorphous silicon layer 27 is formed by chemical vapor deposition and not doped with impurity ions, the grain size of silicon is largely formed in a subsequent process for forming hemispherical silicon grains.

Then, the third sacrificial film 28 is formed on the second amorphous silicon layer 27 with a thickness sufficiently filling the openings. In this case, the third sacrificial film is formed by depositing an oxide film or the like.

Thereafter, the third sacrificial layer 28 is etched back so as to expose the surface of the second amorphous silicon layer 27 positioned on the second sacrificial layer 25 to expose the third sacrificial layer 28 only in the opening.

In addition, the exposed portion of the second amorphous silicon layer 27 positioned at the opening of the opening may be doped by ion implantation using phosphorus ions or the like.

Referring to FIG. 2E, the surface of the second sacrificial layer 25 is exposed by etching back the second amorphous silicon layer and the first amorphous silicon layer. Therefore, the second amorphous silicon layer 27 and the first amorphous silicon layer 26 remain only inside the opening.

Then, the remaining third sacrificial film remaining in the open portion is removed at a wet time to expose the surface of the second amorphous silicon layer 27 in the opening.

Referring to FIG. 2F, impurity ions such as phosphorous ions are implanted onto the substrate in order to dope an end portion of the second undoped second silicon layer remaining at the opening of the opening. Therefore, the portion 270 located at the opening of the opening of the second amorphous silicon 270 is doped with phosphorus ions to suppress the growth of silicon grains in a subsequent process for forming hemispherical silicon grains.

In addition, as described above, local ion implantation into the second amorphous silicon layer may be performed before removing the third sacrificial layer to prevent doping of the second amorphous silicon layer 27 located at the bottom of the opening.

Referring to FIG. 2G, the surfaces of the second amorphous silicon layer 27 and the first amorphous silicon layer 26 positioned on the etch stop layer 23 may be removed by sequentially removing the second sacrificial layer and the first sacrificial layer. Expose At this time, removal of the sacrificial layers is performed by wet etching.

Accordingly, the dielectric film forming portion of the lower electrode pattern including the remaining second amorphous silicon layer 27 and the first amorphous silicon layer 26 is exposed.

Then, first and second hemispherical silicon grains 280 and 281, which are protrusions 17, are formed on the surface of the lower electrode pattern to form a surface area expansion silicon (SAES) that extends the surface area of the lower electrode pattern. In this case, the first and second hemispherical silicon grains 280 and 281 are formed by flowing SiH ₄ gas through the control of process conditions such as temperature and pressure on the exposed lower electrode patterns. The first hemispherical silicon grain 280 is formed on the surface of the second amorphous silicon layer 27 which is not doped with impurities, so that the grain size is large, and the second hemispherical silicon grain 281 is the first amorphous silicon layer doped with impurities (26) and a portion of the second amorphous silicon layer 270, and the grain size is smaller than the size of the first hemispherical silicon grain 280, thereby preventing the bridge phenomenon between the lower electrodes.

Subsequently, although not shown, additional doping and heat treatment may be performed on the final lower electrodes 26, 27, 270, 280, and 281, and Ta ₂ O ₅ , which has a high dielectric constant, may be deposited on the surface of the lower electrode. After the formation, the post-treatment process is performed on the dielectric film in an oxygen atmosphere to improve the characteristics of the dielectric film. This is to form a molecular formula consisting of Ta ₂ O ₅ in order to obtain a dielectric constant value of an ideal dielectric film since Ta ₂ O ₅ is generally composed of Ta ₂ O _5-x .

A capacitor is fabricated by depositing a conductive layer such as TiN on the surface of the dielectric film to form a metal plate electrode as an upper electrode.

Therefore, the present invention increases the capacitance of the capacitor by increasing the dielectric film formation area by forming the inside of the lower electrode with undoped amorphous silicon to increase the hemispherical silicon grain size and to form the shape of the lower electrode in the form of a jar. Since the outer wall and the upper end of the lower electrode are formed of doped amorphous silicon, the hemispherical silicon grain size is made small, thereby preventing the electrical short circuit of the lower electrodes due to the bridge effect.

Claims (5)

On the plug and the first insulating layer of the semiconductor substrate, an impurity diffusion region is formed, a lower electrode formation portion is defined, a first insulating layer is formed, and a conductive plug is formed through the first insulating layer and in contact with the impurity diffusion region. Sequentially forming an etch stop layer and a first sacrificial layer, Forming a second sacrificial layer made of a material having a high etching selectivity with the first sacrificial layer; Removing the second sacrificial layer, the first sacrificial layer, and the etch stop layer on the lower electrode forming portion to a predetermined depth to form an opening exposing a predetermined portion of the first insulating layer including the plug surface; Removing a predetermined portion of the first sacrificial layer to expand a space of the opening; Forming a lower electrode pattern comprising a undoped first amorphous silicon layer and a doped second amorphous silicon layer sequentially stacked on an inner surface of the opening; Removing the second sacrificial layer and the first sacrificial layer; Forming a protrusion on the exposed surface of the lower electrode pattern; And forming a dielectric film and an upper electrode on the lower electrode pattern including the protrusion in order. The method according to claim 1, And doping a portion of the first amorphous silicon layer located at the inlet of the opening. The method according to claim 1, The first and second sacrificial layers are formed of a material having a large etching selectivity with each other. The method according to claim 1, And the etch stop layer and the first sacrificial layer are formed of a material having a large etch selectivity. The method according to claim 1, And further doping the protrusions and the lower electrode patterns.