KR20010064326A - Method for forming MOS transistor in semiconductor device - Google Patents
Method for forming MOS transistor in semiconductor device Download PDFInfo
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- KR20010064326A KR20010064326A KR1019990064494A KR19990064494A KR20010064326A KR 20010064326 A KR20010064326 A KR 20010064326A KR 1019990064494 A KR1019990064494 A KR 1019990064494A KR 19990064494 A KR19990064494 A KR 19990064494A KR 20010064326 A KR20010064326 A KR 20010064326A
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- film
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- gate electrode
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- contact plug
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims abstract description 12
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 239000002019 doping agent Substances 0.000 claims abstract description 6
- 239000011810 insulating material Substances 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 9
- 238000007517 polishing process Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 반도체장치의 제조 방법에 관한 것으로서, 특히 고집적 반도체장치에서 N+ 이온 주입과 콘택 플러그 제조 공정을 단순화하는 반도체장치의 모스트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS transistor of a semiconductor device that simplifies the process of manufacturing N + ion implantation and contact plug in a highly integrated semiconductor device.
최근의 반도체 장치는 디바이스가 고집적화됨에 따라 메모리, 예컨대 DRAM(Dynamic Random Access Memory) 셀 크기가 점점 감소되면서 워드 라인과 커패시터 콘택, 비트라인과 커패시터 콘택의 마진이 점점 작아져 커패시터 콘택을 더욱 작게 형성해야만 한다.In recent years, as semiconductor devices become more integrated, memory, for example, dynamic random access memory (DRAM) cell sizes are gradually decreasing, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller and smaller, so that capacitor contacts must be made smaller. do.
또한, 다수의 배선층 또는 콘택홀 사이의 미스얼라인 마진(mis-align margin)이 점점 줄어들고 있다. 더욱이, 반도체 메모리셀과 같이 디자인 룰(design rule)에 여유가 없고 같은 형태의 패턴이 반복되는 경우, 콘택홀을 자기정렬(self-align) 방식으로 형성함으로써 메모리셀의 면적을 축소시키는 방법이 연구/개발되고 있다. 이러한 자기정렬 방식은 주변구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및 식각방법등에 의해 다양한 크기의 콘택홀을 마스크 사용없이 얻을 수 있기 때문에 고집적화에 의해 미소화되는 반도체장치의 실현에 적합한 방법으로 사용된다.In addition, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. It is being developed. This self-alignment method forms contact holes using the steps of the surrounding structure. The contact holes of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material on which the contact holes are to be formed, and the etching method. Therefore, it is used as a method suitable for realization of a semiconductor device which is miniaturized by high integration.
하지만, 종래 자기정렬 콘택 플러그 제조 방법은 주로 게이트전극 상측 부위의 스페이서(spacer) 및 캐핑(capping)용 절연물질로 질화막을 이용할 경우 층간 절연막의 콘택홀 식각시 게이트전극간 공간 마진이 부족하고 식각 배리어로 사용되는 질화막이 충분히 배리어 역할을 하지 못해서 캐핑막 및 스페이서가 과도 식각되는 경우가 종종 있었다. 이러한 과도 식각으로 인한 손실 부위는 이후 비트라인 또는 플러그 콘택과 워드 라인(게이트전극)과의 쇼트를 유발할 뿐만 아니라 스토리지전극 콘택과 비트라인의 쇼트를 유발하는 문제점이 있었다.However, in the conventional self-aligned contact plug manufacturing method, when the nitride film is used as an insulating material for spacers and cappings on the upper portion of the gate electrode, the space margin between the gate electrodes is insufficient when the contact hole is etched in the interlayer insulating film, and the etching barrier is insufficient. Since the nitride film used as a barrier does not sufficiently serve as a barrier, the capping film and the spacer are often overetched. The loss region due to the excessive etching not only causes a short between the bit line or the plug contact and the word line (gate electrode), but also causes a short between the storage electrode contact and the bit line.
본 발명의 목적은 소오스/드레인 이온 주입을 생략하고 직접 스페이서 공간에 직접 고농도 도전체막을 형성하여 콘택 플러그를 형성함으로써 고집적 반도체장치에서 미세 콘택홀 식각으로 인한 손상을 줄임과 동시에 제조 공정의 단순화를 이룰 수 있는 반도체장치의 모스트랜지스터 제조방법을 제공하는데 있다.An object of the present invention is to omit source / drain ion implantation and to form a contact plug by directly forming a high concentration conductor film directly in a spacer space, thereby reducing damage due to fine contact hole etching and simplifying a manufacturing process in a highly integrated semiconductor device. The present invention provides a method for manufacturing a morph transistor of a semiconductor device.
도 1 내지 도 4는 본 발명에 따라 소오스/드레인 영역과 콘택플러그를 동시에 형성할 수 있는 반도체장치의 모스트랜지스터 제조 과정을 나타낸 공정 순서도이다.1 to 4 are process flowcharts illustrating a process of fabricating a MOS transistor of a semiconductor device capable of simultaneously forming a source / drain region and a contact plug according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 반도체기판 12 : 게이트산화막10 semiconductor substrate 12 gate oxide film
14 : 게이트 도전체 16,18 : 캐핑막14 gate conductor 16,18 capping film
20 : LDD 영역 22 : 스페이서20: LDD region 22: spacer
24 : 콘택 플러그 26 : 층간 절연막24 contact plug 26 interlayer insulating film
상기 목적을 달성하기 위하여 본 발명은 모스 트랜지스터 제조방법에 있어서, 반도체 기판에 필드산화막을 형성하는 단계와, 기판 상부에 게이트산화막을 형성하는 단계와, 게이트산화막 상부에 도전체 및 절연체의 캐핑막을 순차 증착하고 이를 패터닝하여 게이트전극을 형성하는 단계와, 게이트전극 에지 하부에 드러난 기판내에 도전형 불순물이 저농도로 주입된 LDD 영역을 형성하는 단계와, 게이트전극 측면에 절연물질의 스페이서를 형성하는 단계와, 기판 전면에 고농도 도전체막을 두껍게 증착하고 게이트전극의 캐핑막이 노출될 때까지 화학적기계적연마해서 LDD 영역과 접하는 콘택플러그를 형성하는 단계와, 스페이서 주변의 고농도 도전체막을 소정 부분을 제거하는 단계와, 기판 전면에 층간절연막을 형성하는 단계를 포함하되, 콘택플러그의 도펀트가 LDD 영역으로 확산되어 소오스/드레인 영역이 형성되는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of manufacturing a MOS transistor, comprising: forming a field oxide film on a semiconductor substrate, forming a gate oxide film on the substrate, and a capping film of a conductor and an insulator on the gate oxide film Forming a gate electrode by depositing and patterning the same, forming an LDD region in which a conductive impurity is injected at a low concentration in a substrate exposed under the edge of the gate electrode, and forming a spacer of an insulating material on the side of the gate electrode; Depositing a thick conductive film on the entire surface of the substrate and forming a contact plug in contact with the LDD region by chemical mechanical polishing until the capping film of the gate electrode is exposed, and removing a predetermined portion of the high concentration conductive film around the spacer; Forming an interlayer insulating film on the entire surface of the substrate; The dopant is diffused into the LDD region is characterized in that the source / drain region is formed.
본 발명에 따르면, N형 모스트랜지스터 제조 공정시 소오스/드레인 이온 주입을 생략하고 스페이서 사이의 개구부에 직접 고농도 도전체막(증착 또는 SEG 공정 이용)을 형성하여 콘택 플러그를 형성하고 이후 콘택 플러그의 도펀트가 LDD 영역으로 배출 확산(out-diffusion)되어 소오스/드레인 영역을 형성함으로써 미세 콘택홀 식각으로 인한 손상을 줄여 콘택면의 접촉 저항을 높이고 소자 사이의 쇼트를 방지함과 동시에 제조 공정의 단순화를 이룰 수 있다.According to the present invention, in the manufacturing process of the N-type MOS transistor, source / drain ion implantation is omitted, and a high-concentration conductor film (using deposition or SEG process) is formed directly in the opening between the spacers to form a contact plug, and then the dopant of the contact plug Out-diffusion into the LDD region to form source / drain regions reduces damage due to fine contact hole etching, thereby increasing contact resistance on the contact surface, preventing shorts between devices, and simplifying the manufacturing process. have.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 4는 본 발명에 따라 소오스/드레인 영역과 콘택플러그를 동시에 형성할 수 있는 반도체장치의 모스트랜지스터 제조 과정을 나타낸 공정 순서도로이다. 이를 참조하면 본 발명의 N형 모스트랜지스터 제조 공정은 다음과 같다.1 to 4 are process flowcharts illustrating a process of manufacturing a MOS transistor of a semiconductor device capable of simultaneously forming a source / drain region and a contact plug according to the present invention. Referring to this, the N-type MOS transistor manufacturing process of the present invention is as follows.
도 1에 도시된 바와 같이, 반도체기판으로서 실리콘기판(10)에 소자의 활성 영역과 비활성 영역을 정의하기 위한 필드 산화막(미도시함)을 형성한다. 그리고, 필드 산화막이 형성된 기판(10)에 게이트산화막(12)을 형성한다. 게이트산화막(12) 위에 게이트 도전체로서 도프트 폴리실리콘막(14)을 형성한 후에 그 위에 캐핑막 절연체로서 질화막(16) 및 산화막(18)을 적층한다. 이때, 게이트 도전체는 도프트 폴리실리콘 대신에 금속 또는 폴리사이드 구조로 대체할 수 있다.As shown in FIG. 1, a field oxide film (not shown) is formed on the silicon substrate 10 as a semiconductor substrate for defining active and inactive regions of the device. The gate oxide film 12 is formed on the substrate 10 on which the field oxide film is formed. After the doped polysilicon film 14 is formed as the gate conductor on the gate oxide film 12, the nitride film 16 and the oxide film 18 are laminated thereon as the capping film insulator. In this case, the gate conductor may be replaced with a metal or polyside structure instead of doped polysilicon.
그 다음, 게이트 마스크를 이용한 사진 및 식각 공정을 진행하여산화막(18), 질화막(16)으로 이루어진 캐핑막과 도프트 폴리실리콘막(14)을 패터닝해서 게이트전극(G)을 형성한다. 그리고, 상기 게이트전극(G)에 맞추어 게이트산화막(12)도 식각한다. 이어서, n형 불순물로서 P(phosphorus)를 저농도로 이온 주입하여 기판(10)의 표면 근방, 즉 게이트 전극(G)의 에지 사이 또는 게이트 전극(G)과 필드 산화막 사이에 셀프얼라인하는 LDD 영역(20)을 형성한다.Next, a photo-etching process using a gate mask is performed to form a gate electrode G by patterning the capping film and the doped polysilicon film 14 including the oxide film 18 and the nitride film 16. The gate oxide film 12 is also etched in accordance with the gate electrode G. FIG. Next, an LDD region which is self-aligned near the surface of the substrate 10, that is, between the edge of the gate electrode G or between the gate electrode G and the field oxide film by ion implantation of P (phosphorus) at low concentration as an n-type impurity 20 is formed.
그 다음, 도 2에 도시된 바와 같이, 게이트 전극(G) 측벽에 스페이서를 형성하기 위하여 절연체로서 질화막을 증착한다. 그리고, 전면 식각 공정을 실시하여 질화막을 식각해서 게이트전극(G) 측벽에 스페이서(22)를 형성한다.Next, as shown in FIG. 2, a nitride film is deposited as an insulator to form a spacer on the sidewall of the gate electrode G. As shown in FIG. Then, the entire surface etching process is performed to etch the nitride film to form the spacer 22 on the sidewall of the gate electrode G.
그 다음, 도 3에 도시된 바와 같이, 기판 전면에 고농도 도전체막으로서 n+ 불순물이 도핑된 폴리실리콘막을 두껍게 증착한다. 그리고, 게이트전극(G)의 캐핑막중에서 산화막(18)이 노출될때까지 고농도 도전체막을 화학기계연마한다. 그러면, 스페이서(22) 사이의 개구부에는 LDD 영역(20)과 접하는 콘택플러그(24)가 형성된다. 여기서, 콘택플러그(24)의 도전체막은 폴리실리콘대신에 비정질 폴리실리콘 또는 금속을 이용할 수 있다.Next, as shown in FIG. 3, a polysilicon film doped with n + impurity is thickly deposited as a high-concentration conductor film on the entire substrate. In the capping film of the gate electrode G, the high-concentration conductor film is subjected to chemical mechanical polishing until the oxide film 18 is exposed. Then, contact plugs 24 in contact with the LDD regions 20 are formed in the openings between the spacers 22. Here, the conductive film of the contact plug 24 may use amorphous polysilicon or a metal instead of polysilicon.
이어서, 게이트전극과 콘택플러그의 단락을 방지하기 위한 마스크를 이용한 사진 및 식각 공정을 진행하여 게이트전극(G)보다 크게 스페이서(22) 주변의 콘택플러그(24)의 식각 제거한다. 이로 인해, 게이트전극(G)의 스페이서(22)와 콘택플러그(24) 사이, 상측 부분이 분리되어 게이트전극과 콘택플러그의 단락을 방지한다.Subsequently, a photo-etching process using a mask for preventing a short circuit between the gate electrode and the contact plug is performed to etch away the contact plug 24 around the spacer 22 larger than the gate electrode G. As a result, an upper portion is separated between the spacer 22 and the contact plug 24 of the gate electrode G to prevent a short circuit between the gate electrode and the contact plug.
그 다음, 도 4에 도시된 바와 같이, 기판 전면에 스페이서(22)와콘택플러그(24) 사이의 분리된 공간(a)을 채우면서 층간 절연물질을 두껍게 증착하고 이를 화학기계연마해서 평탄화된 층간절연막(26)을 형성한다.Next, as shown in FIG. 4, a thick interlayer insulating material is deposited and chemical mechanical polishing is performed to fill the separated space a between the spacer 22 and the contact plug 24 on the front surface of the substrate to planarize the interlayer. The insulating film 26 is formed.
이후 도면에 도시하지 않았지만, 층간절연막(26)에 배선 공정을 실시하여 콘택플러그(24)에 연결되는 비트라인 및 스토리지전극용 플러그를 형성한다.Although not shown in the drawings, a wiring process is performed on the interlayer insulating layer 26 to form a bit line and a storage electrode plug connected to the contact plug 24.
그러므로, 본 발명은 상술한 콘택플러그 제조공정에 의해 소오스/드레인 이온 주입 공정을 실시하지 않아도 이후 열공정에 의해 콘택플러그(24)의 도펀트가 LDD 영역(20)으로 배출 확산(out-diffusion)되어 소오스/드레인 영역이 형성되기 때문에 미세 콘택홀 식각으로 인한 손상을 줄여 콘택면의 접촉 저항을 높이고 소자 사이의 쇼트를 방지함과 동시에 제조 공정의 단순화를 이룰 수 있다.Therefore, in the present invention, the dopant of the contact plug 24 is discharged out-diffusion into the LDD region 20 by the thermal process, even though the source / drain ion implantation process is not performed by the above-described contact plug manufacturing process. Since the source / drain regions are formed, damage due to fine contact hole etching can be reduced to increase contact resistance of the contact surface, prevent shorts between devices, and simplify the manufacturing process.
또한, 본 발명의 콘택 플러그의 다른 제조 방법은 스페이서 사이의 개구부에 실리콘의 선택적 애피택셜 성장(selective epitaxial growth of silicon) 공정으로 고농도 도프트 폴리실리콘막을 성장할 수 있다.In addition, another method of manufacturing the contact plug of the present invention can grow a high concentration doped polysilicon film by a selective epitaxial growth of silicon process in the opening between the spacers.
상술한 바와 같이 본 발명에 따른 반도체장치의 모스트랜지스터 제조방법에 의하면, 스페이서 사이의 개구부에 직접 고농도 도전체막(증착 또는 SEG 공정 이용)을 형성하여 콘택 플러그를 형성하기 때문에 소오스/드레인 이온 주입 공정을 실시하지 않아도 이후 열공정에 의해 콘택플러그의 도펀트가 LDD 영역으로 배출 확산되어 소오스/드레인 영역이 형성된다.As described above, according to the method of manufacturing a MOS transistor of a semiconductor device, a source / drain ion implantation process is performed because a contact plug is formed by directly forming a highly conductive film (using a deposition or SEG process) in an opening between spacers. Although not performed, the dopant of the contact plug is discharged and diffused into the LDD region by the thermal process to form a source / drain region.
이에 따라, 본 발명은 미세 콘택홀 식각으로 인한 손상을 줄여 콘택면의 접촉 저항을 높이고 소자 사이의 쇼트를 방지함과 동시에 제조 공정의 단순화를 이룰 수 있다.Accordingly, the present invention can reduce the damage caused by the fine contact hole etching to increase the contact resistance of the contact surface, prevent short between the devices and at the same time simplify the manufacturing process.
Claims (4)
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| KR1019990064494A KR20010064326A (en) | 1999-12-29 | 1999-12-29 | Method for forming MOS transistor in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100465380B1 (en) * | 2000-12-04 | 2005-01-13 | 샤프 가부시키가이샤 | Semiconductor device and fabrication process therefor |
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| KR100465380B1 (en) * | 2000-12-04 | 2005-01-13 | 샤프 가부시키가이샤 | Semiconductor device and fabrication process therefor |
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