KR20020015818A - semiconductor device and method for manufacturing the same - Google Patents
semiconductor device and method for manufacturing the same Download PDFInfo
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- KR20020015818A KR20020015818A KR1020000048935A KR20000048935A KR20020015818A KR 20020015818 A KR20020015818 A KR 20020015818A KR 1020000048935 A KR1020000048935 A KR 1020000048935A KR 20000048935 A KR20000048935 A KR 20000048935A KR 20020015818 A KR20020015818 A KR 20020015818A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 콘택(Contact) 형성이 용이하고 콘택간 격리를 완벽하게 하는데 적당한 반도체 소자 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device and a method for manufacturing the same, which are suitable for easy contact formation and perfect inter-contact isolation.
현재 DRAM 칩(Chip) 제조시 가장 많이 사용하는 워드 라인(Word Line)과 비트 라인(Bit Line) 및 스토리지 노드(Storage Node)의 콘택(Contact) 형성 공정이 매우 중요하다.At present, the contact forming process of the word line, the bit line, and the storage node, which are most used in the manufacture of DRAM chips, is very important.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1C are process cross-sectional views showing a conventional method for manufacturing a semiconductor device.
도 1a에 도시한 바와 같이, 액티브 영역과 필드 영역으로 정의된 반도체 기판(11)의 필드 영역에 STI(Shallow Trench Isolation)구조를 갖는 소자 격리막(12)을 형성한다.As shown in FIG. 1A, a device isolation film 12 having a shallow trench isolation (STI) structure is formed in a field region of a semiconductor substrate 11 defined as an active region and a field region.
이어, 상기 반도체 기판(11)의 전면에 게이트 산화막(13), 게이트 전극용 폴리 실리콘막, 질화막을 차례로 형성한다.Subsequently, a gate oxide film 13, a polysilicon film for a gate electrode, and a nitride film are sequentially formed on the entire surface of the semiconductor substrate 11.
그리고 포토 및 식각공정을 통해 상기 질화막, 폴리 실리콘막, 게이트 산화막(13)을 선택적으로 제거하여 일정한 간격을 갖는 게이트 캡 질화막(15) 및 게이트 전극(14)을 형성한다.The nitride film, the polysilicon film, and the gate oxide film 13 are selectively removed through photo and etching processes to form the gate cap nitride film 15 and the gate electrode 14 having a predetermined interval.
이어, 상기 게이트 캡 질화막(15)을 마스크로 이용하여 상기 반도체 기판(11)의 전면에 불순물 이온을 주입하여 게이트 전극(14) 양측의 반도체 기판(11) 표면내에 소오스/드레인 불순물 영역(16)을 형성한다.Subsequently, impurity ions are implanted into the entire surface of the semiconductor substrate 11 using the gate cap nitride film 15 as a mask, so that source / drain impurity regions 16 are formed in the surface of the semiconductor substrate 11 on both sides of the gate electrode 14. To form.
그리고 상기 게이트 전극(14)을 포함한 반도체 기판(11)의 전면에 질화막을 형성한 후, 전면에 에치백 공정을 실시하여 상기 게이트 캡 질화막(15) 및 게이트 전극(14)의 양측면에 질화막 측벽(17)을 형성한다.After the nitride film is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14, an etch back process is performed on the entire surface to form nitride film sidewalls on both sides of the gate cap nitride film 15 and the gate electrode 14. 17).
도 1b에 도시한 바와 같이, 상기 게이트 전극(14)을 포함한 반도체 기판(11)의 전면에 층간 절연막(18)을 형성한다.As shown in FIG. 1B, an interlayer insulating film 18 is formed on the entire surface of the semiconductor substrate 11 including the gate electrode 14.
여기서 미설명한 A, B는 층간 절연막(18)의 형성시 소자의 집적도가 향상됨에 따라 게이트 전극(14)간이 간격이 좁아져 발생하기 쉬운 보이드(Void)의 발생 영역을 나타낸다.Here, A and B, which are not described, represent regions in which voids tend to occur due to a narrow interval between gate electrodes 14 as the degree of integration of the device is improved when the interlayer insulating layer 18 is formed.
도 1c에 도시한 바와 같이, 상기 층간 절연막(18)이 형성된 반도체 기판(11)의 전면에 CMP 공정을 이용하여 표면을 평탄화한다.As shown in FIG. 1C, the surface of the semiconductor substrate 11 on which the interlayer insulating film 18 is formed is planarized using a CMP process.
이어, 포토 및 식각공정을 통해 상기 게이트 전극(14) 사이의 반도체 기판(11) 표면 즉, 소오스/드레인 불순물 영역(16)이 소정부분 노출되도록 상기 층간 절연막(18)을 선택적으로 제거하여 콘택홀을 형성한다.Subsequently, the interlayer insulating layer 18 may be selectively removed to expose a portion of the surface of the semiconductor substrate 11, that is, the source / drain impurity region 16 between the gate electrodes 14, through photo and etching processes. To form.
이어, 상기 콘택홀을 포함한 전면에 폴리 실리콘막을 형성한 후 상기 콘택홀의 내부에만 남도록 상기 폴리 실리콘막을 선택적으로 제거하여 폴리 실리콘 플러그(19)를 형성한다.Subsequently, after the polysilicon film is formed on the entire surface including the contact hole, the polysilicon film is selectively removed to remain only inside the contact hole to form the polysilicon plug 19.
이후 공정은 도면에 도시되지 않았지만, 상기 폴리 실리콘 플러그(19)에 연결되는 비트 라인(B/L)과 스토리지 노드(SN)와 연결하는 등의 DRAM 칩(chip) 제조시 필요한 공정을 실시한다.Since the process is not shown in the drawings, a process required for manufacturing a DRAM chip such as connecting the bit line B / L and the storage node SN connected to the polysilicon plug 19 is performed.
그러나 상기와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above has the following problems.
첫째, 소자가 고집적화됨에 따라 워드 라인(게이트)간의 간격이 좁아져서 층간 절연막이 워드 라인 사이를 완전히 채우지 못하여 보이드(Void)가 발생한다.First, as the device is highly integrated, the gap between word lines (gates) becomes narrow, and voids occur because the interlayer insulating layer does not completely fill the word lines.
둘째, 플러그 형성을 위하여 폴리 실리콘 등의 증착시 보이드에도 폴리 실리콘 등이 증착되어 플러그간에 숏트(Short)가 발생한다.Second, in order to form the plug, polysilicon is also deposited in the voids when polysilicon is deposited, and a short occurs between the plugs.
셋째, 콘택 저항을 낮추기 위하여 비트 라인과 스토리지 노드의 농도를 높이는 것이 좋으나 셀 트랜지스터의 특성 저하를 유발하므로 적용이 불가능하다.Third, it is preferable to increase the concentration of the bit line and the storage node in order to lower the contact resistance, but it is not applicable because it causes deterioration of the characteristics of the cell transistors.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 콘택 형성을 용이하게 함과 동시에 콘택간 숏트를 방지하도록 한 반도체 소자 및 그의 제조방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which facilitate contact formation and prevent short between contacts.
도 1a 내지 도 1c는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2는 본 발명에 의한 반도체 소자를 나타낸 구조단면도Figure 2 is a structural cross-sectional view showing a semiconductor device according to the present invention
도 3a 내지 도 3e는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 소자 격리막21 semiconductor substrate 22 device isolation film
23 : 저농도 n형 불순물 영역 24 : 고농도 n형 불순물 영역23: low concentration n-type impurity region 24: high concentration n-type impurity region
25 : 산화막 26 : 트랜치25 oxide film 26 trench
27 : 질화막 측벽 28 : 게이트 산화막27: nitride film sidewall 28: gate oxide film
29 : 게이트 전극 30 : 층간 절연막29 gate electrode 30 interlayer insulating film
31 : 폴리 실리콘 플러그31: polysilicon plug
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자는 액티브 영역과 필드 영역으로 정의된 반도체 기판의 필드 영역에 형성되는 소자 격리막과, 상기 반도체 기판의 액티브 영역에 일정한 간격을 갖고 소정깊이로 형성되는 복수개의 트랜치와, 상기 각 트랜치 사이의 반도체 기판 표면내에 형성되는 소오스/드레인 불순물 영역과, 상기 트랜치의 양측면에 형성되는 절연막 측벽과, 상기 트랜치의 저면에 형성되는 게이트 산화막과, 상기 트랜치 내부의 게이트 산화막상에 형성되는 게이트 전극과, 상기 소오스/드레인 불순물 영역의 표면이 소정부분 노출되도록 콘택홀을 갖고 반도체 기판상에 형성되는 층간 절연막과, 상기 콘택홀의 내부에 형성되는 폴리 실리콘 플러그를 포함하여 구성됨을 특징으로 한다.The semiconductor device according to the present invention for achieving the above object is formed in a device isolation film formed in the field region of the semiconductor substrate defined by the active region and the field region, and a predetermined depth in the active region of the semiconductor substrate A plurality of trenches, a source / drain impurity region formed in a semiconductor substrate surface between the trenches, an insulating film sidewall formed on both sides of the trench, a gate oxide film formed on the bottom of the trench, and an inside of the trench A gate electrode formed on the gate oxide film, an interlayer insulating film formed on the semiconductor substrate with contact holes to expose a predetermined portion of the surface of the source / drain impurity region, and a polysilicon plug formed inside the contact hole; Characterized in that configured.
또한, 상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 액티브 영역과 필드 영역으로 정의된 반도체 기판의 필드 영역에 소자 격리막을 형성하는 단계와, 상기 반도체 기판의 표면내에 소오스/드레인 불순물 영역을 형성하는 단계와, 상기 반도체 기판을 선택적으로 제거하여 상기 소오스/드레인 불순물 영역보다 깊은 일정한 간격을 갖는 복수개의 트랜치를 형성하는 단계와, 상기 트랜치의 양측면에 절연막 측벽을 형성하는 단계와, 상기 트랜치의 저면에 게이트 산화막을 형성하는 단계와, 상기 트랜치 내부의 게이트 산화막상에 게이트 전극을 형성하는 단계와, 상기 게이트 전극을 포함한 반도체 기판의 전면에 층간 절연막을 형성하는 단계와, 상기 게이트 전극 사이의 고농도 불순물 영역의 표면이 소정부분 노출되도록 상기 층간 절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계와, 상기 콘택홀 내부에 전도성 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.In addition, a method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a device isolation film in the field region of the semiconductor substrate defined by the active region and the field region, the source / in the surface of the semiconductor substrate; Forming a drain impurity region, selectively removing the semiconductor substrate to form a plurality of trenches having a predetermined gap deeper than the source / drain impurity region, and forming insulating film sidewalls on both sides of the trench; Forming a gate oxide film on the bottom surface of the trench, forming a gate electrode on the gate oxide film in the trench, forming an interlayer insulating film on the entire surface of the semiconductor substrate including the gate electrode, and forming the gate oxide film. Even if the surface of the high concentration impurity region between the electrodes is exposed Characterized in that the forming including forming a step of selectively removing the interlayer insulating film to form a contact hole, a conductive plug within the contact hole.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자 및 그의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 의한 반도체 소자를 나타낸 구조단면도이다.2 is a structural cross-sectional view showing a semiconductor device according to the present invention.
도 2에 도시한 바와 같이, 액티브 영역과 필드 영역으로 정의된 반도체 기판(21)의 필드 영역에 형성되는 소자 격리막(22)과, 상기 반도체 기판(21)의 액티브 영역에 일정한 간격을 갖고 소정깊이로 형성되는 복수개의 트랜치(26)와, 상기 각 트랜치(26) 사이의 반도체 기판(21) 표면내에 형성되는 저농도 n형 불순물영역(23)과 고농도 n형 불순물 영역(24)으로 이루어진 소오스/드레인 불순물 영역과, 상기 트랜치(26)의 양측면에 형성되는 질화막 측벽(27)과, 상기 트랜치(26)의 저면에 형성되는 게이트 산화막(28)과, 상기 트랜치(26) 내부의 게이트 산화막(28)상에 형성되는 게이트 전극(29)과, 상기 고농도 n형 불순물 영역(24)의 표면이 소정부분 노출되도록 콘택홀을 갖고 반도체 기판(21)상에 형성되는 층간 절연막(30)과, 상기 콘택홀의 내부에 형성되는 폴리 실리콘 플러그(31)를 포함하여 구성된다.As shown in FIG. 2, the device isolation film 22 formed in the field region of the semiconductor substrate 21 defined by the active region and the field region and the active region of the semiconductor substrate 21 have a predetermined depth at a predetermined depth. A source / drain comprising a plurality of trenches 26 formed of a plurality of trenches 26 and a low concentration n-type impurity region 23 and a high concentration n-type impurity region 24 formed in the surface of the semiconductor substrate 21 between the trenches 26. An impurity region, a nitride film sidewall 27 formed on both sides of the trench 26, a gate oxide film 28 formed on the bottom surface of the trench 26, and a gate oxide film 28 inside the trench 26. An interlayer insulating film 30 formed on the semiconductor substrate 21 having a contact hole so that the gate electrode 29 formed on the surface, the surface of the high concentration n-type impurity region 24 is exposed to a predetermined portion, and the contact hole. Polysilicon formed inside It is configured to include the 31.
여기서 상기 게이트 전극(29)의 하부는 저농도 n형 불순물 영역(23)보다 깊게 형성되며, 상기 게이트 전극(29)의 상부는 반도체 기판(21)의 상부 표면과 동일 높이로 형성된다.The lower portion of the gate electrode 29 is formed deeper than the low concentration n-type impurity region 23, and the upper portion of the gate electrode 29 is formed at the same height as the upper surface of the semiconductor substrate 21.
또한, 상기 저농도 n형 불순물 영역(23)은 고농도 n형 불순물 영역(24)보다 깊게 형성되어 있다.The low concentration n-type impurity region 23 is formed deeper than the high concentration n-type impurity region 24.
도 3a 내지 도 3f는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3a에 도시한 바와 같이, 액티브 영역과 필드 영역으로 정의된 반도체 기판(21)의 필드 영역에 STI(Shallow Trench Isolation)구조를 갖는 소자 격리막(22)을 형성한다.As shown in FIG. 3A, an element isolation film 22 having a shallow trench isolation (STI) structure is formed in the field region of the semiconductor substrate 21 defined by the active region and the field region.
여기서 상기 소자 격리막(22)은 반도체 기판(21)의 필드 영역을 소정깊이로 제거하여 트랜치를 형성한 후, 상기 트랜치 내부에 절연 물질을 매립하여 형성한다.The isolation layer 22 is formed by removing a field region of the semiconductor substrate 21 to a predetermined depth to form a trench, and then filling an insulating material in the trench.
이어, 상기 반도체 기판(21)의 전면에 저농도 n형 불순물 이온과 고농도 n형불순물 이온을 각각 주입하여 반도체 기판(21) 표면내에 저농도 n형 불순물 영역(23)과 고농도 n형 불순물 영역(24)을 각각 형성한다.Subsequently, the low concentration n-type impurity ions and the high concentration n-type impurity ions are implanted into the entire surface of the semiconductor substrate 21 to form the low concentration n-type impurity region 23 and the high concentration n-type impurity region 24 in the surface of the semiconductor substrate 21. Form each.
여기서 상기 저농도 n형 불순물 영역(23)과 고농도 n형 불순물 영역(24)은 소오스/드레인 불순물 영역이다.The low concentration n-type impurity region 23 and the high concentration n-type impurity region 24 are source / drain impurity regions.
도 3b에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 산화막(25)을 형성하고, 포토 및 식각공정을 통해 상기 산화막(25)을 선택적으로 제거하여 게이트 영역을 정의한다.As shown in FIG. 3B, an oxide layer 25 is formed on the entire surface of the semiconductor substrate 21, and the gate layer is defined by selectively removing the oxide layer 25 through a photo and etching process.
이어, 상기 산화막(25)을 마스크로 이용하여 상기 노출된 반도체 기판(21) 즉, 게이트 영역을 선택적으로 제거하여 소정깊이를 갖는 복수개의 트랜치(26)를 형성한다.Subsequently, the exposed semiconductor substrate 21, that is, the gate region, is selectively removed using the oxide layer 25 as a mask to form a plurality of trenches 26 having a predetermined depth.
도 3c에 도시한 바와 같이, 상기 트랜치(26)를 포함한 반도체 기판(21)의 전면에 질화막을 형성한 후, 전면에 에치백 공정을 실시하여 상기 트랜치(26)의 양측면에 질화막 측벽(27)을 형성한다.As shown in FIG. 3C, after the nitride film is formed on the entire surface of the semiconductor substrate 21 including the trench 26, an etch back process is performed on the entire surface to form nitride film sidewalls 27 on both sides of the trench 26. To form.
여기서 상기 질화막 측벽(27)을 형성하기 전에 문턱전압 조절을 위한 이온을 주입한다.Here, before forming the nitride film sidewall 27, ions are implanted to adjust the threshold voltage.
도 3d에 도시한 바와 같이, 상기 반도체 기판(21)에 산화 공정을 실시하여 상기 트랜치(26)의 저면에 게이트 산화막(28)을 형성한다.As shown in FIG. 3D, an oxidation process is performed on the semiconductor substrate 21 to form a gate oxide film 28 on the bottom surface of the trench 26.
이어, 상기 트랜치(26)를 포함한 반도체 기판(21)의 전면에 게이트 전극용 폴리 실리콘막을 형성한 후, 에치백 및 CMP 공정을 실시하여 상기 트랜치(26)내의 게이트 산화막(28)상에 게이트 전극(29)을 형성한다.Subsequently, after forming a polysilicon film for a gate electrode on the entire surface of the semiconductor substrate 21 including the trench 26, an etch back and a CMP process are performed to form a gate electrode on the gate oxide film 28 in the trench 26. (29) is formed.
도 3e에 도시한 바와 같이, 상기 고농도 n형 불순물 영역(24)의 표면을 앤드 포인트(End Point)로 하여 반도체 기판(21)의 전면에 CMP 공정을 실시하여 표면을 평탄화한다.As shown in FIG. 3E, the surface of the high concentration n-type impurity region 24 is used as an end point to perform a CMP process on the entire surface of the semiconductor substrate 21 to planarize the surface.
즉, 상기 CMP 공정에 의해 산화막(25) 및 질화막 측벽(27)의 일부가 선택적으로 제거되어 상기 게이트 전극(29)은 반도체 기판(21)의 상부 표면과 동일 높이가 된다.That is, a portion of the oxide film 25 and the nitride film sidewall 27 are selectively removed by the CMP process, so that the gate electrode 29 is flush with the upper surface of the semiconductor substrate 21.
도 3f에 도시한 바와 같이, 상기 반도체 기판(21)의 전면에 층간 절연막(30)을 형성하고, 포토 및 식각 공정을 통해 상기 고농도 n형 불순물 영역(24)의 표면이 소정부분 노출되도록 상기 층간 절연막(30)을 선택적으로 제거하여 콘택홀을 형성한다.As shown in FIG. 3F, an interlayer insulating film 30 is formed on the entire surface of the semiconductor substrate 21, and the interlayer is exposed so that a predetermined portion of the surface of the high concentration n-type impurity region 24 is exposed through photo and etching processes. The insulating layer 30 is selectively removed to form contact holes.
이어, 상기 콘택홀을 포함한 반도체 기판(21)의 전면에 폴리 실리콘막을 형성한 후 선택적으로 제거하여 폴리 실리콘 플러그(31)를 형성한다.Subsequently, a polysilicon film is formed on the entire surface of the semiconductor substrate 21 including the contact hole and then selectively removed to form the polysilicon plug 31.
이후 공정은 도면에 도시되지 않았지만, 상기 폴리 실리콘 플러그(31)에 연결되는 비트 라인(B/L)과 스토리지 노드(SN)와 연결하는 등의 DRAM 칩(chip) 제조시 필요한 공정을 실시한다.Since the process is not shown in the figure, a process necessary for manufacturing a DRAM chip such as connecting the bit line B / L and the storage node SN connected to the polysilicon plug 31 is performed.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자 및 그의 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device and its manufacturing method according to the present invention have the following effects.
첫째, 소오스/드레인 영역을 먼저 형성시킴으로서 이온주입후 충분한 열처리를 실시하는 것이 가능하여 소오스/드레인 저항을 작게 할 수 있고, 문턱전압 조절을 위한 이온과 게이트 형성후 고온공정이 필요하지 않아 트랜지스터 특성을 향상시킬 수 있다.First, since source / drain regions are formed first, sufficient heat treatment can be performed after ion implantation, so that source / drain resistance can be reduced, and high temperature processes are not required after ion and gate formation for threshold voltage control. Can be improved.
둘째, 트랜지스터에 영향을 미치지 않고 소오스/드레인 영역의 농도를 높임으로서 콘택저항을 줄일 수 있다.Second, the contact resistance can be reduced by increasing the concentration of the source / drain regions without affecting the transistor.
셋째, 비트 라인과 스토리지 노드 콘택간의 격리를 위한 절연막 증착시 기판 전면에 평평하여 절연막에 보이드 등이 발생하지 않아 콘택간의 격리 특성을 향상할 수 있다.Third, when the insulating film is deposited for isolation between the bit line and the storage node contact, the insulating film may be flat on the entire surface of the substrate to prevent voids and the like, thereby improving the isolation property between the contacts.
넷째, 기판의 전면에 평평하여 이후 배선 공정 등이 용이하다.Fourth, it is flat on the front surface of the substrate, and subsequent wiring processes are easy.
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| KR100988775B1 (en) * | 2007-12-27 | 2010-10-20 | 주식회사 동부하이텍 | Method of manufacturing a trench contact of a semiconductor device |
| CN108281424A (en) * | 2017-01-06 | 2018-07-13 | 联华电子股份有限公司 | Semiconductor element with and preparation method thereof |
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| KR101051813B1 (en) * | 2005-03-03 | 2011-07-25 | 매그나칩 반도체 유한회사 | CMOS device and its manufacturing method |
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| KR100988775B1 (en) * | 2007-12-27 | 2010-10-20 | 주식회사 동부하이텍 | Method of manufacturing a trench contact of a semiconductor device |
| CN108281424A (en) * | 2017-01-06 | 2018-07-13 | 联华电子股份有限公司 | Semiconductor element with and preparation method thereof |
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