KR20010061118A - DRAM cell and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A DRAM cell is provided to have a transistor formed perpendicularly to a trench capacitor. CONSTITUTION: A p-type semiconductor substrate(31) has a plurality of trenches. Plural dielectric films(32) and plural lower electrodes(33) are stacked in the trenches respectively so as to bury the trenches. A plurality of channels(36) are formed on the semiconductor substrate(31). A plurality of drain regions(34) are formed in the channels(36). A plurality of gate electrodes(37) are formed at both sides of two channels. An inter poly oxide layer(38) is formed on the semiconductor substrate(31) between the trenches and at one side of the channel comprising the gate electrode(37). A metal layer(39) is formed on the inter poly oxide layer(38) and the channel regions(36).

Description

DRAM cell and method for manufacturing the same {DRAM cell and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (DRAM) cell and a method of manufacturing the same. In particular, a trench capacitor and a DRAM cell for forming a transistor vertically to improve the characteristics and integration of the device and its formation It is about a method.

In general, DRAM is composed of a unit cell consisting of a transistor that performs a number of switching (Swithing) operation and a capacitor that stores information in the form of charge, and has the characteristic of storing information as a state of charge stored in the capacitor.

As the integration of semiconductor devices proceeds, the integration of DRAM, which is a volatile memory device, is accompanied by a reduction of the capacitor area, which causes a decrease in the capacitance of the capacitor. Accordingly, studies are actively conducted to improve the capacity of the capacitor to the same level as before. It is becoming.

In the conventional DRAM cell manufacturing method, as shown in FIG. 1A, an insulating film is embedded on a semiconductor substrate 11 on which a field oxide film 12 is formed by a typical shallow trench isolation (STI) process in an isolation region, and a source / A plurality of gate electrodes 13 having a drain region are formed.

After the first nitride film 14 is formed on the entire surface including the gate electrodes 13, the first oxide film 15 and the first photoresist film are formed on the first nitride film 14. The photoresist is selectively exposed and developed so as to be removed only at the portion where the bit line contact hole is to be formed by a photolithography process.

Thereafter, the first oxide film 15 and the first nitride film 14 are selectively etched using the first exposed and developed photosensitive film as a mask to form a first contact hole, and then the first photosensitive film is removed. do.

Subsequently, after the first polycrystalline silicon layer is formed on the first oxide layer 15 including the first contact hole, the first oxide layer 15 is etched back to the etching end point, thereby forming the first polycrystalline silicon layer. The first plug layer 16 is formed in the contact hole.

After the second polycrystalline silicon layer, the tungsten silicide layer, the second nitride film and the second photosensitive film are formed on the first oxide film 15 including the first plug layer 16, the second photosensitive film is formed on the first film. The photolithography process is performed so that only the bit line will be formed around the contact hole.

Next, the second nitride film, the tungsten silicide layer, and the second polycrystalline silicon layer are selectively etched using the photo-etched second photosensitive film as a mask to form a plurality of bit lines 17, and then the second photosensitive film is removed. .

A third nitride film is formed on the entire surface including the bit lines 17 and etched back to form third nitride film sidewalls 18 on the first oxide film 15 on both sides of the bit lines 17.

Subsequently, after the second oxide film 19 and the third photoresist film are formed on the entire surface including the third nitride film sidewall 18, the third photoresist film is etched to remove only the portion where the capacitor contact hole is to be formed.

Thereafter, the second oxide layer 19, the first oxide layer 15, and the first nitride layer 14 are selectively etched using the photo-etched third photosensitive layer as a mask to form a second contact hole, and then 3 Remove the photoresist film.

Subsequently, after forming a third polycrystalline silicon layer on the second oxide film 19 including the second contact hole, the second oxide film 19 is etched back to an etching end point to form a third polycrystalline silicon layer in the second contact hole. The second plug layer 20 is formed.

As shown in FIG. 1B, a third oxide film 22 and a fourth photosensitive film are formed on the second oxide film 19 including the second plug layer 20.

After the photolithography process is performed such that the fourth photoresist film is removed only at the portion where the lower electrode of the capacitor is to be formed, the third oxide film 22 is selectively etched using the photo-etched fourth photoresist film as a mask, and then Remove the photoresist.

As shown in FIG. 1C, the fourth polycrystalline silicon layer 23a and the fifth photosensitive layer 24 are formed on the entire surface including the etched third oxide layer 22.

As shown in FIG. 1D, the fifth photoresist layer 24 and the fourth polycrystalline silicon layer 23a are etched back to form the lower electrode 23 by using the third oxide layer 22 as an etching end point. The oxide film 22 and the fifth photosensitive film 24 are removed.

A dielectric layer 25 is formed on the lower electrode 23 surface.

As shown in FIG. 1E, the upper electrode 26 is formed on the entire surface including the dielectric layer 25.

However, the conventional DRAM cell and its manufacturing method are formed by forming source / drain regions in the semiconductor substrate surfaces on both sides of the gate electrode, that is, by forming transistors horizontally and stacking bit lines and capacitors on the upper side thereof. As a result, the manufacturing process of the device is complicated and there is a problem of degrading the characteristics and integration of the device.

First, when forming bit lines and capacitors on the upper side of the transistor, a plurality of contact hole forming processes are required by the Self-Aligned-Contact (SAC) method, thereby forming a plurality of etching endpoint insulating films, which makes the device manufacturing process complicated. do.

Second, since the transistors are formed horizontally, a plurality of transistors are formed per well, so that a plurality of device isolation ion implantation processes are required for device isolation.

Third, since the transistor, the bit line, and the capacitor are formed in a stacked structure, the step difference between the cell and the peripheral region increases.

Fourth, a plurality of mask processes are required to form a capacitor, and a short occurs between the gate electrode, the bit line, and the plug layer as the device is integrated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a DRAM cell and a method of manufacturing the same, which form a transistor perpendicular to the trench capacitor.

1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional DRAM cell.

2 is a layout diagram illustrating a DRAM cell according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a DRAM cell on a line I-I of FIG. 2;

4A through 4D are cross-sectional views illustrating a method of manufacturing a DRAM cell according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

31: semiconductor substrate 32: dielectric film

33: lower electrode 34: drain region

35: second nitride film 36: channel region

37: gate electrode 38: IPO layer

39: metal layer

The DRAM cell of the present invention includes a first conductive substrate having a plurality of trenches and also serving as an upper electrode of a capacitor, a plurality of dielectric layers and source regions of transistors, each of which is buried and stacked in each of the trenches. A plurality of lower conductive electrodes having a second conductivity type, a plurality of channel regions of a first conductivity type formed on a substrate above the lower electrodes, and a plurality of second conductive types formed in a surface of an upper portion of each channel region. Drain regions, a plurality of gate electrodes formed by embedding a gate oxide film on both sides of the two channel regions as one unit, a plurality of gate electrodes formed on a substrate between the trenches and on one side of the channel region including the gate electrode Device isolation oxide layers and a wiring layer formed on the device isolation oxide layers and the channel regions. Characterized in that configured.

A method of manufacturing a DRAM cell of the present invention comprises the steps of: providing a first conductive substrate having a plurality of trenches and also acting as an upper electrode of a capacitor, filling a plurality of dielectric films and transistors in each trench; Stacking lower electrodes of a second conductivity type, which also serves as a source region, forming a first conductive layer of a first conductivity type on the entire surface including the lower electrodes, and a second conductivity type impurity in the first conductive layer Performing an ion implantation process, forming a first insulating layer on the first conductive layer and selectively etching the first insulating layer and the first conductive layer to form a plurality of channel regions having a first conductivity type on a substrate above the lower electrodes; Forming a plurality of drain regions of a second conductivity type in the surface of the upper portion, the two channel regions being in one unit on both sides thereof Forming a plurality of gate electrodes having a gate oxide film, forming a second insulating film having an etch selectivity with the first insulating film on the entire surface, and then etching the entire surface to form a substrate on the substrate between the trenches and the channel including the gate electrode; Forming a plurality of device isolation insulating layers on one side of the region, removing the first insulating layer, and forming a wiring layer on the device isolation oxide layers and the channel regions.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of a DRAM cell and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout diagram illustrating a DRAM cell according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a DRAM cell on a line I-I of FIG. 2.

4A through 4D are cross-sectional views illustrating a method of manufacturing a DRAM cell according to an exemplary embodiment of the present invention.

As shown in FIGS. 2 and 3, a DRAM cell according to an exemplary embodiment of the present invention has a plurality of trenches, a p-type semiconductor substrate 31, and a plurality of dielectric layers formed by filling the trenches and being stacked in the trenches. 32 and lower electrodes 33, a plurality of channel regions 36 formed on the semiconductor substrate 31 on the lower electrodes 33, and each of the channel regions 36. A plurality of drain regions 34 formed in a surface of an upper portion, and a plurality of gates having gate oxide films on both sides of the two channel regions 36 as one unit and arranged in one direction of a rod structure Inter Poly Oxide (IPO), which is formed on the semiconductor substrate 31 between the electrodes 37 and the trenches and on one side of the channel region 36 including the gate electrode 37, serves as a device isolation oxide layer. Layer 38, the IPO layer 38 and the channel Is configured at the station 36 deulsang a metal layer (39) formed in a direction perpendicular to the gate electrode 37.

Here, the semiconductor substrate 31 also serves as an upper electrode of the capacitor, and the lower electrode 33 also serves as a source region of the transistor.

In the method of manufacturing a DRAM cell transistor according to an embodiment of the present invention, as shown in FIG. 4A, a first photoresist film is coated on a p-type semiconductor substrate 31, and then a trench capacitor is formed by a photolithography process. It is selectively exposed and developed to be removed only in the area to be removed.

Here, the semiconductor substrate 31 also serves as an upper electrode of the capacitor.

The semiconductor substrate 31 is selectively etched using the selectively exposed and developed first photoresist layer to form a plurality of trenches, and then the first photoresist layer is removed.

Subsequently, after the thermal oxidation process is performed on the entire surface, a nitride structure and a first polycrystalline silicon layer doped with a high concentration n-type impurity are formed on the semiconductor substrate 31 including the trenches, and are etched back to form a stacked structure in each of the trenches. Dielectric layers 32 and lower electrodes 33 are formed.

Here, the lower electrode 33 also serves as a source region of the transistor.

As shown in FIG. 4B, a second polycrystalline silicon layer doped with a high concentration p-type impurity is formed on the semiconductor substrate 31 including the trenches filled by the lower electrode 33.

Then, after ion implantation of well ions into the second polycrystalline silicon layer, ion implantation and drive-in diffusion of high concentration n-type impurity ions are performed to drain the region within the surface of the second polycrystalline silicon layer 34. 34).

Subsequently, after forming the second nitride film 35 and the second photosensitive film on the second polycrystalline silicon layer, the second photoresist film is subjected to the photolithography process so that only the upper portion of the lower electrodes 33 remains.

Thereafter, the second nitride film 35 and the second polycrystalline silicon layer are selectively etched using the selectively removed second photoresist layer to form a plurality of channel regions 36, and then the second photoresist layer is removed. do.

As shown in FIG. 4C, after the gate oxide film is grown by thermal oxidation on the entire surface, a third polycrystalline silicon layer and a third photosensitive film are formed on the gate oxide film, and then the gate is formed by a photolithography process. Remain only at the site to be formed.

The third polycrystalline silicon layer is selectively etched using the selectively removed third photoresist film, and then the third photoresist film is removed.

Subsequently, the plurality of gate electrodes 37 having the gate oxide layer embedded on the semiconductor substrate 31 on both sides of the two channel regions 36 as one unit by etching back the remaining third polycrystalline silicon layer. Form them.

Subsequently, an IPO layer 38 is formed on the entire surface including the gate electrodes 37.

As shown in FIG. 4D, the IPO layer 38 is etched back using the second nitride film 35 as an etching end point, and then the second nitride film 35 is removed.

Here, the IPO layer 38 serves as a device isolation oxide layer and forms a plurality of contact holes exposing the channel regions 36 by an etch back process of the IPO layer 38.

The metal layer 39 is formed as a wiring on the channel regions 36 and the IPO layer 38.

The DRAM cell of the present invention and the manufacturing method thereof form a trench capacitor and a drain region so as to protrude from the semiconductor substrate to form a transistor vertically, so that a plurality of contact hole forming processes by the SAC method are unnecessary and the capacitor is a semiconductor substrate. It reduces the number of mask processes to simplify the device fabrication process, reduces the step between the cell and the peripheral area, prevents short circuit between gate electrodes, bit lines, and capacitors, and one well per cell. Increasing the characteristics of device isolation has the effect of increasing the characteristics and integration of the device.

Claims (2)

A first conductivity type substrate having a plurality of trenches and also serving as an upper electrode of the capacitor; A plurality of dielectric layers buried in the trenches and stacked in each of the trenches, and second electrodes having a second conductivity type serving as a source region of a transistor; A plurality of channel regions of a first conductivity type formed on a substrate above the lower electrodes; A plurality of drain regions of a second conductivity type formed in a surface of an upper portion of each channel region; A plurality of gate electrodes formed by embedding a gate oxide layer on both sides of the two channel regions as one unit; A plurality of device isolation oxide layers formed on a substrate between the trenches and on one side of a channel region including the gate electrode; And a wiring layer formed on the device isolation oxide layers and channel regions. Providing a first conductivity type substrate having a plurality of trenches and also serving as an upper electrode of the capacitor; Stacking each of the trenches and forming a plurality of dielectric layers and lower electrodes of a second conductivity type in each trench, which also serves as a source region of a transistor; Forming a first conductive layer having a first conductivity type on a front surface of the lower electrodes; Performing a second conductive impurity ion implantation process on the first conductive layer; A first insulating layer is formed on the first conductive layer, and the first insulating layer and the first conductive layer are selectively etched, thereby forming a plurality of channel regions having a first conductivity type on the substrate above the lower electrodes and in a surface of an upper portion thereof. Forming a plurality of drain regions of a second conductivity type; Forming a plurality of gate electrodes having gate oxide layers on both sides of the two channel regions as one unit; Forming a plurality of device isolation insulating films on the substrate between the trenches and on one side of the channel region including the gate electrode by forming a second insulating film having an etching selectivity with the first insulating film on the entire surface and then etching the entire surface; Removing the first insulating film; And forming a wiring layer on the device isolation oxide layers and the channel regions.