KR101043409B1 - Method of fabricating semiconductor apparatus - Google Patents

Abstract

In the present invention, a gate electrode in a cell array embedded in a semiconductor substrate, a core connected to the cell array, and a gate electrode included in a peripheral region are formed using a single gate mask. A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film on a semiconductor substrate on which an active region is defined, and etching the interlayer insulating film and the semiconductor substrate by using a gate mask on a cell array, a core and a peripheral region. Forming a recess, forming a gate insulating film in the recess and filling it with a gate material, etching the gate material to be formed below the surface of the semiconductor substrate, and forming a gate insulating film on the gate material. Forming to form a gate pattern.

Semiconductors, Cell Arrays, Peripheral Areas, Recess Gates, Pin Gates

Description

Manufacturing method of semiconductor device {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a unit cell that operates stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. In addition, the semiconductor memory device may include a core region including circuits for transferring data transferred to a unit cell or sensing and amplifying data output from the unit cell, and connecting the core region to the outside of the semiconductor memory device and used in the semiconductor memory device. Peripheral areas including circuitry for generating voltages, and the like.

As the degree of integration of semiconductor memory devices increases, the size of various internal circuits needs to be reduced. In particular, reducing the area of the cell array that occupies the largest area in the semiconductor memory device is more efficient in increasing the density of the semiconductor memory device relative to other circuits. For this reason, various methods for making a cell array including a unit cell having a size of 6F ² have recently been proposed, including US Patent No. 7,034,408 (Title: Memory device and method of manufacturing a memory device, inventor: Schloesser). Can be. Hereinafter, a characteristic configuration and a manufacturing method of the above-described US patent will be described, and details thereof will be omitted.

In the above-described US patent, a cell transistor is formed as a recess gate in order to prevent short channel effects that may occur as the unit cell is reduced in size. In particular, word lines were embedded in a semiconductor substrate on which active regions were formed and protected by an insulating film, and then bit line contacts were formed between the insulating films or above the insulating films. The word line constituting the gate of the cell transistor included in the unit cell is generally formed at a level higher than the surface of the semiconductor substrate. However, in the above-described US patent, the word line is formed below the surface of the semiconductor substrate to form a bit line. It is easier to make electrical disconnection with bit line contacts connected with Conventionally, when the electrical disconnection between the word line and the bit line through only the insulating film, due to the parasitic capacitance of the bit line, the performance of the semiconductor memory device has been degraded due to the increase of leakage current and the deterioration of the operating speed. This buried feature allows for clear parasitic capacitance, with clear bit lines and bit line contacts and electrical disconnects.

Referring to the summary of the above-described US patent, instead of forming a recess gate when forming a transistor included in a peripheral region, the gate of the transistor is formed in the same structure as a bit line formed by stacking a plurality of layers of a cell array. . That is, in the aforementioned US patent, a word line including a gate of a cell transistor included in a unit cell is formed using a word line mask, while gate electrodes of transistors in a core and a peripheral circuit are formed in a cell array. A gate electrode is formed by forming a gate electrode by using a mask in forming a line and depositing the same material as a plurality of conductive materials constituting a bit line. Therefore, an alignment error occurs between the word line composed of the gate of the cell transistor and the gate of the transistor formed in the core and the peripheral circuit at the edge of the cell array. Moreover, even if the design rule is reduced, such alignment error is not reduced, which causes a malfunction of the semiconductor memory device.

In order to solve the above-mentioned conventional problems, in the present invention, a semiconductor memory device for forming a gate electrode in a cell array embedded in a semiconductor substrate, a core connected to the cell array, and a gate electrode included in a peripheral region using a single gate mask. A method of manufacturing a semiconductor device and a semiconductor memory device manufactured accordingly are provided.

According to an embodiment of the present invention, an STI process is performed on a semiconductor substrate to define an active region, an interlayer insulating layer is formed on the semiconductor substrate, and the interlayer insulating layer and the interlayer insulating layer are formed by using a gate mask on a cell array and a core and a peripheral region. Etching a semiconductor substrate to form a recess, forming a gate insulating film in the recess, filling the recess with a gate material, and etching the gate material to be formed below the surface of the semiconductor substrate And forming a gate upper insulating film on the gate material to form a gate pattern.

Advantageously, the method of manufacturing a semiconductor memory device comprises forming a sidewall insulating film on sidewalls of the gate pattern in the core and peripheral regions; And forming source / drain regions on both sides of the gate pattern in the core and peripheral regions.

Preferably, the method of manufacturing the semiconductor memory device further includes etching the semiconductor substrate on both sides of the gate pattern formed in the core and the peripheral region after the formation of the gate pattern.

Preferably, the thickness of the gate insulating film in the core and the peripheral region is varied.

Preferably, the gate insulating layer is formed to have a different thickness according to the cell array, the core and the peripheral region.

Preferably, the gate insulating film includes any one selected from the group consisting of an oxide film and a nitrided oxide film.

Preferably, when the gate insulating film is formed differently according to the cell array, the core and the peripheral area, the gate insulating film formed on the core and the peripheral area may be any one selected from the group consisting of an oxide film, an aluminum oxide film, and a hafnium oxide film. It is characterized by including.

Preferably, the sidewall insulating film comprises any one selected from the group consisting of an oxide film, a nitride film and an oxynitride film.

Preferably, the gate material is characterized in that it comprises any one selected from the group consisting of polycrystalline silicon, TiN and tungsten (W).

According to the present invention, an alignment error can be prevented by forming a gate pattern formed in a cell array, a core, and a peripheral region using a same mask in a semiconductor memory device having a structure in which a word line is buried in a semiconductor substrate.

In addition, the present invention can form the source / drain region and the LDD region formed on both sides of the gate pattern formed in the core and the peripheral region after adjusting the height of the semiconductor substrate, so that the length of the channel without increasing the value of the gate capacitance The short channel effect can be prevented by increasing, and the density can be increased by reducing the size of a transistor.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In manufacturing a semiconductor memory device having a structure in which word lines in a cell array are embedded in a semiconductor substrate, in a method of manufacturing a semiconductor memory device according to an embodiment of the present invention, a word line embedded in a cell array and a core region other than the cell array are embedded. And a gate electrode of the transistor formed in the peripheral region using one gate mask. Through this method, alignment errors caused by forming gate electrodes of transistors formed in word lines, core regions, and peripheral regions of a cell array using different masks according to a conventional method of manufacturing a semiconductor memory device can be eliminated. . In addition, when the method of manufacturing a semiconductor memory device is applied to an embodiment of the present invention using one gate mask, the gate electrode of a transistor formed in the core region and the peripheral region, such as a word line in a cell array, is also embedded in the semiconductor substrate. This allows the effective channel length to be increased without increasing the value of the gate capacitance.

A method of manufacturing a semiconductor memory device according to an embodiment of the present invention is to allow the gate electrode of a transistor in a semiconductor memory device to be recessed and formed under a semiconductor substrate. The semiconductor memory device includes a unit cell composed of three-dimensional cell transistors. In particular, the present invention may be applied regardless of the structure of a three-dimensional cell transistor such as a pin transistor or a recess gate transistor.

1A to 1D are plan views illustrating an ISO mask and a gate mask according to an embodiment of the present invention for forming a semiconductor memory device.

1A and 1B illustrate ISO mask patterns 102A and 102B and first and second gate mask patterns 104A and 104B in a cell array according to unit cell sizes. Specifically, FIG. 1A illustrates a case in which a unit cell has a size of 8F ² , and FIG. 1B illustrates a case in which a unit cell has a size of 6F ² . In this case, F means a minimum line width according to a design rule.

In addition, in contrast to the ISO mask patterns 102C and 102D, FIG. 1C illustrates a third gate mask pattern 104C that can define where gate line widths of transistors in the core and the peripheral region of the semiconductor memory device are formed differently. 1D illustrates the fourth gate mask pattern 104D of the transistor having a large line width in the core and the peripheral region.

In the method of manufacturing a semiconductor memory device according to an embodiment of the present invention, various first, second, third, and fourth gate mask patterns 104A or 104B, 104C, and 104D shown in FIGS. It is characterized by being included in the gate mask. As a result, word lines embedded in the cell arrays corresponding to the first or second gate mask patterns 104A or 104B are formed in the core region and the peripheral region outside the cell arrays corresponding to the gate mask patterns 104C and 104D. It is possible to form the gate electrode of the transistor using one gate mask.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention using the gate mask shown in FIGS. 1A to 1D. In particular, in the case where the cell transistor in the semiconductor memory device includes a recess gate structure, four of X--X ', Y--Y', I-I ', and II-II' shown in FIGS. 1A to 1D are shown. A method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to a cross section along the axis.

Referring to FIG. 2A, an isolation insulating film 202 is formed in the semiconductor substrate 201 by performing a shallow trench isolation (STI) process. The STI process is described in detail as follows. First, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially stacked on the semiconductor substrate 201 (the oxidation process and the deposition process are performed), and then the etching process using the active mask is performed. A trench is formed in the trench. Then, the insulating insulating film 202 is deposited to fill the trench, followed by chemical mechanical polishing (CMP) to form the insulating insulating film 202 with the trench embedded therein, and then the pad nitride film and the pad oxide film. Remove sequentially.

After the isolation insulating film 202 is formed through the STI process, the buffer insulating film 203 is formed on the exposed semiconductor substrate 201. A photoresist (not shown) is coated on the buffer insulating layer 203, and a photo process using an implant mask is performed to inject wells and channel ions into necessary portions to remove remaining photoresist. Here, in order to form the well and the channel region, the semiconductor substrate 201 is exposed as necessary by using each mask, and then ion implantation is repeatedly performed. Thereafter, a first insulating film 204 is formed on the buffer insulating film 203 and the insulating insulating film 202.

Referring to FIG. 2B, after the gate pattern hard mask film 205 is formed on the first insulating film 204, the photosensitive film 206 is coated on the gate pattern hard mask film 205. Thereafter, the photosensitive film 206 is patterned through a photo process using a gate mask. The gate pattern hard mask layer 205 exposed by the patterned photoresist layer 206 is etched, and the exposed first insulating layer 204 is etched again.

Subsequently, the exposed buffer insulating film 203 is etched while the gate pattern hard mask film 205 and the first insulating film 204 are etched, and then the exposed semiconductor substrate 201 and the insulating insulating film 202 are word lines. Etch it to the depth required to bury it.

As shown in FIG. 2C, the semiconductor substrate 201 is etched to a predetermined depth to form a recess, and a chemical dry etching (CDE) is performed to round the bottom surface of the recess, and then, a first insulating layer. The photoresist film 206 and the gate pattern hard mask film 205 remaining on the 204 are removed.

Subsequently, the cleaning operation is performed and the second insulating film 207 is thinly deposited, followed by dry etching, so that the second insulating film 207 remains only on the sidewalls of the recess. Here, the second insulating layer 207 is for electrically disconnecting the sidewall of the word line to be buried thereafter.

Referring to FIG. 2D, the gate insulating layer 208 is formed after the ion implantation for channel formation is further performed on the semiconductor substrate 201 exposed by the recess. Next, a conductive material is deposited on the gate insulating layer 208 to a predetermined thickness to fill the recess to form the gate electrode 209. Referring to <X-X '> and <Y-Y'>, in the case of narrow recesses of the cell array in the semiconductor memory device, the recesses are completely filled due to the conductive material, but are shown in <II-II '>. As shown, in the case of a wide gate region, the recess is not completely filled by the conductive material. Since it is not efficient to deposit a thick conductive material to completely fill the wide gate region, the first gate upper insulating layer 210 is deposited so that the recess corresponding to the wide gate region is completely filled.

Referring to FIG. 2E, the gate electrode 209 formed by filling the recess is etched by a predetermined thickness through a first etch-back process. In this case, the first etch back process allows the upper portion of the gate electrode 209 to remain higher than the semiconductor substrate 201. After performing the first etch back process, the exposed first insulating layer 204 and the second insulating layer 207 are etched by a predetermined amount through isotropic wet etching to form a recess having a wider width than that of the gate electrode 209. To form.

As shown in FIG. 2F, the exposed gate electrode 209 is etched by a predetermined thickness through a secondary etch back process. In this case, the second etchback process allows the upper portion of the gate electrode 209 to remain lower than the semiconductor substrate 201. Thereafter, the second gate upper insulating layer 211 is formed on the gate electrode 209 to fill the recess, and then planarize by performing a chemical mechanical polishing process (CMP). At this time, due to the isotropic wet etching performed before the second etch back process, the second gate upper insulating film 211 is formed on the gate electrode 209 to have a narrow width in the region lower than the surface of the semiconductor substrate 201, but the semiconductor The width is wider in an area higher than the surface of the substrate 201.

Where the width of the gate electrode 209 is narrow, only the second gate upper insulating film 211 is formed on the gate electrode 209, but the width of the gate electrode 209 is formed on the gate electrode 209. In addition to the two gate upper insulating layer 211, a first gate upper insulating layer 210 is formed together. Therefore, in order to ensure uniform characteristics of the transistor in the semiconductor memory device, it is preferable that the first gate upper insulating film 210 and the second gate upper insulating film 211 are made of the same material.

Referring to FIG. 2G, the photoresist layer 212 is coated on the first and second gate upper insulating layers 210 and 211 and the first insulating layer 204, and the cell is exposed to expose the core region and the peripheral region outside the cell array region. A photo process using a cell close mask is performed. Thereafter, the first insulating layer 204 exposed to the core region and the peripheral region outside the cell array region is etched, and then the exposed buffer insulating layer 203 is also removed.

Thereafter, the semiconductor substrate 201 exposed while the buffer insulating layer 203 is removed is etched in a predetermined amount within a range not lower than the lower portions of the gate electrode 209 and the gate insulating layer 208. Thereafter, the remaining photoresist film 212 is removed.

Referring to FIG. 2H, after the new photoresist film (not shown) is applied onto the structure, the photoresist is patterned by performing a photo process using a mask defining a source / drain region. In order to form the LDD region and the local doped region (Halo) in the source / drain region exposed by the patterned photoresist, ion implantation is performed with low concentration of impurities.

Subsequently, the third insulating layer 213 is deposited on the core region and the peripheral region outside the cell array region, and dry etching is performed so that the third insulating layer 213 remains only on the sidewalls of the gate electrode pattern and the insulating insulating layer 202. In this case, the third insulating layer 213 is formed for the purpose of insulating the LDD region. Then, ion implantation is performed with high concentrations of impurities to form source / drain regions. Thereafter, the photoresist remaining in the cell array region is removed.

Although not shown, after completion of the source / drain regions in the core region and the peripheral region outside the cell array region, the interlayer insulating film is deposited and planarized in the same manner as in the manufacture of a general semiconductor memory device. Form. Thereafter, a bit line plug and a bit line contact for connecting the bit line and the cell transistor are formed, and a storage node plug for connecting the cell transistor and the capacitor is formed. Thereafter, bit lines and capacitors are formed in the cell array region, and other metal wirings and the like are further formed to manufacture the semiconductor memory device.

3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

In the method of manufacturing a semiconductor memory device according to another embodiment of the present invention, the semiconductor substrate 301 and the insulating film 304 are etched and recessed from the process of forming the insulating insulating film 302 through the STI process in the semiconductor substrate 301. After the process, the gate electrode 309 is formed by filling the conductive material and forming the gate insulating film 311 in the space formed through the etch back process, as described with reference to FIGS. 2A through 2F.

Subsequently, referring to FIG. 3A, the photoresist layer 312 is coated on the first and second gate upper insulating layers 310 and 311 and the first insulating layer 304 to expose the core region and the peripheral region other than the cell array region. The photo process is performed using a cell close mask. Thereafter, the first insulating layer 304 exposed to the core region and the peripheral region outside the cell array region is etched, and the photoresist layer 312 remaining in the cell array region is removed.

Referring to FIG. 3B, after the new photoresist film (not shown) is applied onto the structure, the photoresist is patterned by performing a photo process using a mask defining a source / drain region. In order to form the LDD region and the local doped region (Halo) in the source / drain region exposed by the patterned photoresist, ion implantation is performed with low concentration of impurities.

Thereafter, the third insulating layer 313 is deposited on the core region and the peripheral region outside the cell array region, and dry etching is performed so that the third insulating layer 313 remains only on the sidewall of the gate electrode pattern. In this case, the third insulating layer 313 is formed for the purpose of insulating the LDD region. Then, ion implantation is performed with high concentrations of impurities to form source / drain regions. Thereafter, the photoresist remaining in the cell array region is removed.

Although not shown, after completion of the source / drain regions in the core region and the peripheral region outside the cell array region, the interlayer insulating film is deposited and planarized in the same manner as in the manufacture of a general semiconductor memory device. Form. Thereafter, a bit line plug and a bit line contact for connecting the bit line and the cell transistor are formed, and a storage node plug for connecting the cell transistor and the capacitor is formed. Thereafter, bit lines and capacitors are formed in the cell array region, and other metal wirings and the like are further formed to manufacture the semiconductor memory device.

2H and 3B, in the present invention, the semiconductor substrate 301 may be selectively etched after the cell array region is covered with the photoresist using a photo process using a cell close mask, thereby changing the order of the processes or performing additional processes. It is possible to manufacture a semiconductor memory device corresponding to the structure of transistors formed in the core region and the peripheral region other than the cell array region.

In the present invention, since the gate electrode of the cell transistor is formed by recessing lower than the upper surface of the semiconductor substrate as in the prior art, parasitic capacitance occurring between the bit line and the word line can be reduced, thereby improving sensing margin and refresh characteristics of data. In addition, by forming the gate of the transistor in the core region and the peripheral region outside the cell array region by using the same mask as the gate of the cell transistor, alignment error between the conventionally generated word line and core and peripheral circuit transistor gate electrode patterns Does not occur.

In addition, since the LDD and the source / drain regions of the transistors formed in the core and the peripheral region are formed by selectively etching the semiconductor substrate to adjust the height, the gate capacitance values of the transistors formed in the core and the peripheral region are also the same as before. Can be made smaller. In addition, the height of the semiconductor substrate can be adjusted when the LDD and the source / drain regions are formed, so that the short channel effect can be reduced compared to the prior art, thereby increasing the degree of integration of the semiconductor memory device.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1D are plan views illustrating an ISO mask and a gate mask according to an embodiment of the present invention for forming a semiconductor memory device.

2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention using the gate mask shown in FIGS. 1A to 1D.

3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

Claims (9)

Performing an STI process on the semiconductor substrate to define an active region; Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating layer and the semiconductor substrate using a gate mask in a cell array, a core, and a peripheral region to form a recess; Forming a gate insulating film in the recess; Filling the recess with a gate material; Etching the gate material so that the gate material is formed below the surface of the semiconductor substrate; Forming a gate pattern by forming a gate upper insulating layer on the gate material; And Etching the semiconductor substrate on both sides of the gate pattern formed in the core and the peripheral region A manufacturing method of a semiconductor memory device comprising a. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, Forming a sidewall insulating film on sidewalls of the gate pattern in the core and peripheral regions; And And forming source / drain regions on both sides of the gate pattern in the core and peripheral regions. delete delete Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And the gate insulating film is formed to have a different thickness depending on the cell array, the core and the peripheral area. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, And the gate insulating film includes any one selected from the group consisting of an oxide film and a nitrided oxide film. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, When the gate insulating film is formed differently according to the cell array, the core and the peripheral area, the gate insulating film formed on the core and the peripheral area includes any one selected from the group consisting of an oxide film, an aluminum oxide film, and a hafnium oxide film. A method of manufacturing a semiconductor memory device. Claim 8 was abandoned when the registration fee was paid. The method of claim 2, And the sidewall insulating film includes any one selected from the group consisting of an oxide film, a nitride film and an oxynitride film. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, And the gate material comprises any one selected from the group consisting of polycrystalline silicon, TiN and tungsten (W).

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