JP2006060056A - Method for manufacturing semiconductor memory device and the semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a structure for supplying hydrogen easily and efficiently, and to provide its manufacturing method. <P>SOLUTION: When a capacitor connected with a source region 3 of a cell transistor TR is formed, an interlayer dielectric 8 is formed and a contact hole 8D for opening the source region 3 is formed therein. Subsequently, a hydrogen containing insulating film, e.g. a first plasma nitride film 9A covering the side face and the bottom face of the contact hole 8D is formed and heat-treated in a hydrogen atmosphere. In this regard, hydrogen is supplied to the source region in order to terminate a dangling bond. Thereafter, the first plasma nitride film 9A is etched and left on the side face of the contact hole 8D, and the contact hole 8D is filled with a plug 10 thus forming a capacitor CAP such that the lower electrode 12A is connected to the plug 10. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a DRAM (semiconductor memory device) having a structure in which a lower electrode of an upper capacitor is connected to one impurity region constituting a source or drain of a transistor, and the semiconductor memory device It is.

FIG. 6 shows an example of a cross-sectional structure of a DRAM having a so-called stacked capacitor (see Patent Document 1). FIG. 6 shows two DRAM cells.
An element isolation insulating layer 101 is formed on the semiconductor substrate 100. The semiconductor surface portion between the element isolation insulating layers 101 becomes the active region of the DRAM cell transistor.
In this active region, the drain region (D) 102 and the source region (S) 103 are formed at a certain distance on both sides in one direction of the drain region (D). An active region between the drain region (D) 102 and the source region (S) 103 is a channel formation region of the cell transistor.

  A gate stacked body of the gate insulating film 104 and the gate electrode 105 is formed on each channel formation region. A first insulating film 106 and a second insulating film 107 are deposited on the gate stack, and a bit contact that opens the drain region (D) 102 and a source region ( S) Contacts of storage nodes that open 103 are opened, and contact plugs 108 are embedded in these bit contacts and storage node contacts. The contact plug 108 in the bit contact is provided at a position on the second insulating film 107 different from the cross-sectional location, and is connected to the bit line BL indicated by a broken line. A third insulating film 109 is deposited on the second insulating film 107 and the bit line BL, and further, a fourth insulating film 110 is deposited thereon.

A capacitor groove is formed in the fourth insulating film 110, and a stack type capacitor 111 having an MIM structure is formed in the capacitor groove. The capacitor 111 includes a lower electrode 111A, a high dielectric film 111B, and an upper electrode 111C.
The lower electrode 111A of the capacitor is connected to the contact plug 108A immediately below it by the storage node plug 112, whereby the connection between the capacitor 111 and the source region (S) 103 is achieved.

In the manufacture of such a DRAM cell, first, an element isolation insulating layer 101 having a trench structure, a gate insulating film 104 of a cell transistor, a gate electrode (a part of a word line) 105, and a drain region (D) are formed on a semiconductor substrate 100. 102 and source region (S) 103 are formed using a conventional MOS transistor forming technique.
Next, a first insulating film 106 is deposited, a contact plug 108 using, for example, polycrystalline silicon doped with P or As is formed, and a second insulating film 107 and a bit line BL are formed.
A third insulating film 109 is deposited, and a storage node plug 112 made of, for example, titanium nitride TiN is formed.

Next, a fourth insulating film 110 is deposited, a groove is formed in the fourth insulating film 110, and a lower electrode 111A is formed by applying and drying a solution containing a ruthenium Ru element and CVD using a raw material containing ruthenium.
Thereafter, a high dielectric film 111B is formed, and an upper electrode 111C is formed in the same manner as the lower electrode 111A, thereby completing the capacitor 111.
JP 2003-332261 A

  With the integration of semiconductor memories (DRAM), how to improve capacitor capacity and data retention characteristics has become a major issue. From the viewpoint of capacitor capacity, reduction of the area occupied by the capacitor due to memory cell shrinkage, and from the viewpoint of data retention characteristics, junction leakage and subthreshold leakage are problems.

  Conventionally, various devices for increasing the capacitance value per unit area have been made with the reduction of the capacitor occupation area. The above-mentioned Patent Document 1 is also a part thereof, and is characterized by the material of the lower electrode 111A and the upper electrode 111C and the method of forming the same in order to form the high dielectric film 111B.

  However, in the technique of the above-mentioned Patent Document 1, even if the storage capacity of the capacitor 111 is improved, no countermeasure is taken against the fact that the junction leakage and the subthreshold leakage are large and the data retention characteristics are deteriorated.

  In order to suppress junction leakage and subthreshold leakage, it is effective to reduce the N-type impurity concentration in the storage node diffusion layer, that is, in the above-mentioned Patent Document 1, by reducing the N-type impurity concentration in the source region 103. This is because if the storage node diffusion layer (source region 103) is formed deep and at a high concentration, the electric field strength increases with the surrounding P-type region, the band bends sharply, junction leakage increases, and the cell This is because off-leakage (subthreshold leakage) increases between the drain region 102 and the source region 103 when the transistor is off.

  However, when the concentration of the storage node diffusion layer is lowered, the sheet resistance of the diffusion layer increases, and the driving capability of the cell transistor deteriorates. As a result, there is a problem that the random access speed of the DRAM cell itself is lowered and the demand for high performance cannot be sufficiently satisfied.

  In order to reduce the leakage of such a low concentration, thin storage node diffusion layer (source region 103), hydrogen is supplied, and dangling bonds (dangling bonds) due to crystal defects are terminated with hydrogen. It is known that reducing the position is effective.

  The problem to be solved by the present invention is to provide a semiconductor memory device having a structure in which hydrogen supply is easy and efficient, and a manufacturing method thereof.

  A method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a capacitor in which a lower electrode is connected through a contact hole to one impurity region of a transistor formed on a semiconductor substrate. A contact opening step of forming an interlayer insulating film on the transistor, forming a contact hole in the interlayer insulating film to open the impurity region, and a hydrogen-containing insulating film covering a side surface and a bottom surface of the contact hole A hydrogen supply step for supplying hydrogen to the impurity region in contact with the hydrogen-containing insulating film by performing a heat treatment in a hydrogen atmosphere; etching the hydrogen-containing insulating film; and hydrogen-containing side surfaces of the contact holes An etching step for leaving a part of the insulating film in contact with the impurity region; Forming a plug by filling the Kutohoru a conductive material, and a capacitor formation step of the lower electrode on the plug to form the capacitor to connect.

According to such a manufacturing method, hydrogen is supplied to the one impurity region using the hydrogen-containing insulating film as a hydrogen supply source.
More specifically, hydrogen in the hydrogen-containing insulating film is supplied to the impurity region in the heat treatment after the hydrogen-containing insulating film is formed on the bottom and side surfaces of the contact hole, and hydrogen in the atmosphere at the time of the heat treatment is hydrogen-containing insulating film To be supplied to the impurity region. Further, even after the hydrogen-containing insulating film is etched and left on the side surface of the contact hole, the remaining sidewall-shaped hydrogen-containing insulating film is in contact with impurities, so that the shape of the sidewall is not changed in the subsequent heat treatment. Hydrogen is supplied from the hydrogen-containing insulating film to the impurity region.

  In this manufacturing method, the interlayer insulating film is preferably formed by laminating a plurality of insulating films including a hydrogen-containing insulating film. By doing so, during the subsequent heat treatment, the hydrogen-containing insulating film in the interlayer insulating film is passed through the sidewall-shaped hydrogen-containing insulating film in contact therewith, or another insulating film in the interlayer insulating film. Through the hydrogen, hydrogen is supplied to the impurity region of the transistor.

In this manufacturing method, preferably, the capacitor forming step further includes a multilayer insulating film forming step in which two types of insulating films, one of which is a hydrogen-containing insulating film and having different etching rates, and the multilayer insulating film are formed. A groove forming step for forming a capacitor groove that opens the upper portion of the plug in the film; an etching step for retracting one of the multilayer insulating films at a side surface in the capacitor groove; and the capacitor having irregularities formed on the side surface An electrode forming step of forming a lower electrode in the groove and sequentially forming a capacitor dielectric film and an upper electrode on the lower electrode;
Also in this case, since the hydrogen-containing insulating film is included in the multilayer insulating film, during the subsequent heat treatment, hydrogen is transmitted from the hydrogen-containing insulating film in the interlayer insulating film through the contact or through the interlayer insulating film. Supplied to the impurity region.

The hydrogen-containing insulating films formed at the various locations described above are preferably formed by a plasma CVD method using silane (SiH ₄ ) gas.

A semiconductor memory device according to the present invention includes a transistor formed on a semiconductor substrate, an interlayer insulating film on the transistor, and a contact hole formed in the interlayer insulating film with respect to one impurity region of the transistor. A semiconductor memory device having a capacitor connected to a lower electrode, wherein a hydrogen-containing insulating film having a lower end in contact with one impurity region of the transistor is formed on an inner wall of a contact hole of the interlayer insulating film, A conductive plug that connects the one impurity region and the lower electrode of the capacitor on the interlayer insulating film is formed in the contact hole surrounded by the film.
Preferably, the interlayer insulating film is composed of a plurality of insulating films including a hydrogen-containing insulating film.
Preferably, a multilayer insulating film in which two types of insulating films, one of which is a hydrogen-containing insulating film and having different etching rates, are alternately stacked is formed on the interlayer insulating film, and the capacitor is a groove of the multilayer insulating film. A lower electrode connected to the one impurity region via the contact; a capacitor dielectric film on the lower electrode; and an upper electrode on the capacitor dielectric film.

  According to the present invention, it is possible to provide a semiconductor memory device having a structure in which hydrogen supply is easy and efficient, and a manufacturing method thereof.

  The semiconductor memory device (DRAM) according to the present embodiment includes a transistor formed on a semiconductor substrate and a so-called stack type capacitor formed in a laminated film structure thereabove. In this DRAM, a so-called sidewall-shaped hydrogen-containing insulating film is provided in the contact of the storage node, and more preferably, an interlayer insulating film in which the storage node contact is formed, and an insulating film in which an upper capacitor is formed. Also includes a hydrogen-containing insulating film. Hereinafter, this most preferred embodiment will be described in detail with reference to the drawings. Here, as the hydrogen-containing insulating film, silicon nitride (SiN) formed by so-called plasma CVD is exemplified.

FIG. 1 shows a cross-sectional structure of a DRAM according to the present embodiment.
The illustrated DRAM cell 1 has a cell transistor TR in which one of a source and a drain is connected to a bit line (not shown), and a lower electrode (storage node electrode) connected to the other of the source and the drain of the cell transistor TR. A capacitor CAP.

  The cell transistor TR includes a source region 3 formed in a P-type well (P well) 2 formed in a semiconductor substrate, for example, a silicon wafer, and a drain region 4 electrically connected to a bit line (not shown). And have. This source region 3 constitutes one embodiment of “one impurity region” in the present invention. The surface portion of the P well 2 between the source region 3 and the drain region 4 becomes a channel formation region in which the channel of the cell transistor TR is formed.

  On the channel formation region, a gate insulating film 5 made of a thin silicon oxide film of, for example, about several nm to several tens of nm and a gate electrode 6 made of, for example, N-type polycrystalline silicon are laminated. The gate electrode 6 can form a word line by being formed as a long wiring in a direction orthogonal to the cross section of FIG. Sidewall spacer layers 7 made of, for example, silicon oxide are formed on both sides in the wiring width direction of a laminated body (hereinafter referred to as a gate laminated body) composed of the gate insulating film 5 and the gate electrode 6. The source region 3 and the drain region 4 are positioned so that their end portions overlap directly below the sidewall spacer layer 7.

  The source region 3 and the drain region 4 have a shallow junction depth of about 10 to 20 nm, for example, and an N-type impurity concentration such as phosphorus or arsenic is formed lower than that of a normal MOS transistor. Considering the low concentration thin layer and the positional relationship with respect to the sidewall spacer layer 7, the source region 3 and the drain region 4 can be formed under the same ion implantation conditions as a so-called extension region in a normal MOS transistor. is there. Therefore, in the case where the DRAM is mounted with a logic circuit, the DRAM cell transistor TR is formed by preventing the high density source region and drain region from being formed in the DRAM cell region in the process of the logic transistor. It can be formed simultaneously with the logic transistor.

The DRAM cell transistor TR is covered with a thick oxide insulating film 8A, an etching stopper film 8B made of a second plasma nitride film, and an interlayer insulating film 8 made of a thin oxide insulating film 8C.
The intermediate etching stopper film 8B is composed of a second plasma nitride film as a hydrogen-containing insulating film, that is, a silicon nitride film formed by a plasma CVD method using silane (SiH ₄ ) gas. Since the silicon nitride film functions as an etching stopper when etching the thin oxide insulating film 8C thereon, it is hereinafter referred to as an etching stopper film.

A contact hole 8D of a storage node that opens a part of the source region 3 is formed in the interlayer insulating film 8. A first plasma nitride film 9 as a hydrogen-containing insulating film, that is, a silicon nitride film formed by a plasma CVD method using silane (SiH ₄ ) gas is formed on the side surface in the contact hole 8D. The sidewall-shaped first plasma nitride film 9 has a lower end in contact with the source region 3 and functions as a hydrogen supply source.
A plug 10 made of, for example, conductive polycrystalline silicon is embedded in the internal space of the contact hole 8D surrounded by the sidewall-shaped first plasma nitride film 9.

A multilayer insulating film 11 is formed on the interlayer insulating film 8 by alternately stacking a third plasma nitride film 11A as a hydrogen-containing insulating film and an oxide-based insulating film 11B a plurality of times.
A capacitor groove is formed in the multilayer insulating film 11. The capacitor trench is also formed in the thin oxide film insulating film 8 </ b> C which is the uppermost layer of the interlayer insulating film 8.
On the side surface in the capacitor trench, the thin oxide insulating film 8C and the oxide insulating film 11B constituting the multilayer insulating film recede to the outside in the width direction of the capacitor trench. As a result, the capacitor Irregularities are formed on the side surface of the groove.

A lower electrode (storage node electrode) 12A of the capacitor CAP made of a conductive material is formed in the capacitor groove having such an inner surface shape (uneven shape). Since the lower electrode 12A is formed of a relatively thin conductive layer, the surface of the lower electrode 12A is formed so as to wave, reflecting the inner shape (uneven shape) of the capacitor groove.
A capacitor dielectric film 12B is thinly formed on the surface of the lower electrode 12A including the wavy portion, and an upper electrode (plate electrode) 12C having a width slightly larger than the capacitor groove is formed on the surface of the capacitor dielectric film 12B. ing.
The plate electrode 12C is formed as a long wiring in a direction orthogonal to the cross section of FIG. An oxide protective film 13 having a flat surface is formed on the plate electrode 12C.

Although not particularly illustrated, the DRAM cells having such a structure are arranged in a matrix on a planar pattern, thereby forming a DRAM cell array.
A predetermined voltage can be applied by a peripheral circuit in which plate electrode lines, word lines, and bit lines formed of the upper electrode 12C are formed outside the DRAM memory cell array. A read circuit that amplifies and reads the potential of the bit line is also formed in the peripheral circuit.

In the structure of the DRAM cell 1, three plasma nitride films, that is, a first plasma nitride film 9 in a sidewall shape that is in direct contact with the source region 3, and indirectly to the source region 3 through the first plasma nitride film 9. A second plasma nitride film (etching stopper film) 8B in contact therewith, and a third plasma nitride film 11A overlying the second plasma nitride film 11A. Again, these are all formed by plasma CVD using silane (SiH ₄ ) gas and contain hydrogen, so that they function as a hydrogen supply source during the annealing process after formation. That is, the DRAM cell having the structure shown in FIG. 1 has an advantage that the hydrogen supply source is appropriately and sufficiently arranged in the cell structure itself, and as a result, the hydrogen supply to the source region 3 can be sufficiently achieved.

Next, a manufacturing method for forming the cell structure shown in FIG. 1 will be described.
2A to 5B are cross-sectional views in the middle of manufacturing the DRAM according to this embodiment.

First, a DRAM cell transistor TR shown in FIG. 2A is formed.
In the formation of the cell transistor TR, an element isolation insulating layer (not shown) is formed on the surface of a semiconductor substrate made of a silicon wafer, for example, by the LOCOS method or STI method, and the P well 2 is formed by ion implantation of P-type impurities. Then, ion implantation for adjusting the threshold voltage of the transistor is performed as necessary.
After the gate insulating film 5 is formed on the surface of the P well 2 by a thermal oxidation method, a polycrystalline silicon film to be the gate electrode 6 (word line) is deposited by the CVD method, and these are patterned by etching. It is also possible to form a polycide on the gate electrode 6 to reduce the resistance, and further to form a protective insulating layer thereon.
Next, after the sidewall spacer layer 7 is formed on the gate electrode 6, ion implantation is performed by self-alignment to form the source region 3 and the drain region 4. Examples of impurities used for ion implantation include phosphorus and arsenic. As ion implantation conditions, conditions at the time of forming so-called extension regions can be used.

On the formed cell transistor TR, a thick oxide-based insulating film 8A, a second plasma nitride film 8B, and a thin oxide-based insulating film 8C are sequentially formed on the surface of the surrounding P well 2 and the element isolation insulating layer. Form. As a result, as shown in FIG. 2A, an interlayer insulating film 8 composed of a plurality of films is formed.
Subsequently, a resist (not shown) opening above the source region 3 is formed, and a contact hole 8D of a storage node having a large aspect ratio is formed by anisotropic etching using the resist as a mask.

As shown in FIG. 2B, the first plasma nitride film 9A is formed under conditions with good coverage covering the side and bottom surfaces in the contact hole 8D.
In this state, the first hydrogen annealing is performed. In the hydrogen annealing, the wafer is exposed to a hydrogen atmosphere and, for example, RTA (short-time heat treatment) for about several tens of seconds is performed. Thereby, hydrogen (H ₂ ) is supplied to the source region 3 and the drain region 4 in particular, and the supplied hydrogen terminates dangling bonds near the well interface and the junction.

  The entire surface of first plasma nitride film 9A is etched (etched back) by anisotropic etching such as RIE. As a result, as shown in FIG. 3A, the first plasma nitride film 9A is removed on the thin oxide insulating film 8C and on the bottom surface in the contact hole 8D, and the side surface in the contact hole 8D is removed. The sidewall-shaped first plasma nitride film 9 remains.

The contact hole 8D is filled with a conductive material, and the surface is flattened by CMP, for example. As a result, the plug 10 is formed as shown in FIG. In addition, the third plasma nitride film 11A and the oxide film-based insulating film 11B are alternately stacked many times, here, the third plasma nitride film 11A is stacked in five layers and the oxide film-based insulating film 11B is stacked in four layers. Thereby, the multilayer insulating film 11 is formed on the interlayer insulating film 8.
In this state, the second hydrogen annealing is performed in the same manner as the first hydrogen annealing, for example. When there is a dangling bond near the well interface or junction, this dangling bond can be terminated with supplied hydrogen.

  A resist (not shown) having an opening is formed on a region around the plug 10 and anisotropic etching (dry etching) is performed using the resist as a mask. In this etching, the etching conditions of the nitride film and the etching conditions of the oxide film are alternately switched, but after the etching of the third plasma nitride film 11A in the lowermost layer of the multilayer insulating film 11, the etching conditions are switched to the oxide film. The oxide insulating film 8C having a thin interlayer insulating film 8 is also etched. As a result, the upper portion of the plug 10 is exposed, but at this time, the etching rate is extremely slowed by the etching stopper film (second plasma nitride film 8B), so that the etching is stopped by performing some over-etching from that time. (See FIG. 4A).

  After removing the resist, isotropic etching is performed. Thereby, due to the etching rate difference between the plasma nitride film 11A and the insulating film 11B, irregularities are formed on the inner wall surface in the capacitor groove 11C as shown in FIG. 4B.

Next, the capacitor CAP is formed.
First, as shown in FIG. 5A, a conductive film to be the lower electrode 12A is formed by a method with good coverage. As a result, the conductive film is formed such that the surface thereof undulates at the uneven portion of the inner wall surface in the capacitor groove 11C. Capacitor trench 11C is filled with resist R1. Specifically, as shown in FIG. 5A, the resist R1 is etched back by a method of etching back the resist R1 or by exposing the entire surface of the positive resist R1 and dissolving the surface with a developer. Remains.

  With the resist R1 protecting the lower electrode 12A in the capacitor trench 11C, the surrounding conductive film is removed by etching.

After removing the resist R1, the capacitor dielectric film 12B is thinly formed by a method with good coverage, and a conductive film to be the upper electrode 12C is formed on the capacitor dielectric film 12B.
Subsequently, a resist R2 having a pattern shown in FIG. 5B is formed, and the conductive film to be the upper electrode 12C is etched using the resist R2 as a mask.
Thereafter, when the resist is removed to form the protective film 13, the DRAM cell 1 shown in FIG. 1 is completed.

Such a manufacturing method has the following many advantages.
First, by performing hydrogen annealing twice during the formation of the structures of the first to third plasma nitride films 9, 8B and 11A, the silicon dangling bonds are terminated with hydrogen, and the source region 3 and Junction leakage and subthreshold leakage of the drain region 4 can be reduced, and as a result, the charge retention characteristics of the DRAM cell can be greatly improved.

More specifically, when the first plasma nitride film 9 is formed on the side wall of the contact hole 8D for conducting to the capacitor, immediately after the first plasma nitride film 9 is formed on the inner wall and the bottom surface of the contact hole (before etch back) ), The first hydrogen annealing is performed. That is, by performing the hydrogen annealing with the first plasma nitride film 9 remaining on the bottom of the contact hole 8D (immediately above the source region 3), uniform hydrogen supply can be achieved at a required location, thereby making the junction The effect of reducing leaks is increased. Regarding the deterioration of the data retention characteristics of the DRAM, the junction leak is more dominant than the capacitor leak. Therefore, it is important to reduce the junction leak.
Further, the second hydrogen annealing is performed after the multilayer insulating film 11 is formed. This is because, when hydrogen annealing is performed after forming irregularities by etching, the absolute amount of the plasma nitride film is small, so that the hydrogen annealing is performed before this etching, thereby completing the leakage reduction effect.

  Second, the capacitor CAP has a concave structure, and the surface area of the capacitor CAP is increased by forming irregularities on the side wall of the capacitor groove 11C. As a means for forming the unevenness, a laminated film of the third plasma nitride film 11A and the insulating film 11B is formed, and the unevenness is formed by utilizing the etching rate difference of the laminated film at the time of forming the groove. Thereby, there is an advantage that uniform unevenness can be formed to a necessary degree.

  Thirdly, the first plasma nitride film 9 has an advantage of increasing the aspect ratio of the storage node contact in addition to the above-described role as a hydrogen supply source. This makes it possible to form holes below the limit resolution of photolithography, and further shrink the cell area. Further, even when a mask shift occurs when the contact hole is formed and this overlaps with the gate electrode 6, the first plasma nitride film 9 functions as an insulating film, so that a short circuit between the gate and the source can be effectively prevented. There are also advantages.

  Fourth, since the second plasma nitride film 8B is used as the etch stopper film at the time of forming the capacitor groove, diversification of hydrogen supply sources for ensuring a good shape of the capacitor groove and reducing junction leakage is simultaneously performed. It has been achieved.

  Fifth, the lower electrode 12A in which the capacitor CAP is electrically connected to the node of the cell transistor TR by a plug embedded in the interlayer insulating film 8, the capacitor dielectric film 12B, and the upper electrode 12C are substantially Since it is formed so as to be embedded in the multilayer insulating film 11, the level difference between the memory cell portion and the peripheral circuit portion is reduced. On the other hand, since the surface area of the capacitor electrode is effectively increased by the unevenness provided on the side surface in the capacitor groove as described above, the capacitor capacity is increased. Thus, the capacitor CAP having a small occupation area and good flatness is realized.

1 is a cross-sectional structure diagram of a DRAM according to an embodiment. In the manufacturing of the DRAM according to the present embodiment, it is a cross-sectional view showing a process until the first hydrogen annealing in particular. It is sectional drawing which shows the process from the process following FIG. 2 to the 2nd hydrogen annealing. It is sectional drawing which shows the process from the process following FIG. 3 to the uneven | corrugated formation in a capacitor groove | channel. FIG. 5 is a cross-sectional view showing steps from the step following FIG. 4 to the patterning of the upper electrode of the capacitor. FIG. 10 is a cross-sectional structure diagram of a conventional DRAM including a so-called stacked capacitor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... DRAM cell, 2 ... P well, 3 ... Source region, 4 ... Drain region, 8 ... Interlayer insulation film, 8B ... 2nd plasma nitride film, 9 ... 1st plasma nitride film, 10 ... Plug, 11 ... Multilayer insulating film, 11A ... third plasma nitride film, C ... capacitor groove, 12A ... lower electrode, 12B ... capacitor dielectric film, 12C ... upper electrode, TR ... transistor, CAP ... capacitor

Claims (10)

A method of manufacturing a semiconductor memory device including a step of forming a capacitor connected to a lower electrode through a contact hole for one impurity region of a transistor formed on a semiconductor substrate,
A contact opening step of forming an interlayer insulating film on the transistor, and forming a contact hole for opening the impurity region in the interlayer insulating film;
Forming a hydrogen-containing insulating film covering the side and bottom surfaces of the contact hole, and performing a heat treatment in a hydrogen atmosphere to supply hydrogen to the impurity region in contact with the hydrogen-containing insulating film;
Etching the hydrogen-containing insulating film and leaving a part of the hydrogen-containing insulating film in contact with the impurity region on the side surface of the contact hole;
Forming a plug by filling the contact hole with a conductive material, and forming the capacitor so that a lower electrode is connected to the plug. A method of manufacturing a semiconductor memory device. The method of manufacturing a semiconductor memory device according to claim 1, wherein the interlayer insulating film is formed by stacking a plurality of insulating films including a hydrogen-containing insulating film. The capacitor forming step further comprises:
A step of forming a multilayer insulating film in which two types of insulating films, one of which is a hydrogen-containing insulating film and having different etching rates, are alternately formed;
A groove forming step of forming a capacitor groove opening the upper portion of the plug in the multilayer insulating film;
An etching step for retracting one of the multilayer insulating films at a side surface in the capacitor trench;
The semiconductor memory device according to claim 1, further comprising: an electrode forming step of forming a lower electrode in the capacitor groove having unevenness on a side surface, and sequentially forming a capacitor dielectric film and an upper electrode on the lower electrode. Manufacturing method. The method for manufacturing a semiconductor memory device according to claim 1, wherein the hydrogen-containing insulating film is formed by a plasma CVD method using silane (SiH ₄ ) gas. The interlayer insulating film is formed by laminating a plurality of insulating films including a hydrogen-containing insulating film formed by a plasma CVD method using silane (SiH ₄ ) gas,
4. The method of manufacturing a semiconductor memory device according to claim 3, wherein, in the groove forming step, an insulating film above the hydrogen-containing insulating film in the interlayer insulating film is etched under a condition that the hydrogen-containing insulating film serves as a stopper. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein in the step of forming the multilayer insulating film, the hydrogen-containing insulating film constituting the multilayer insulating film is formed by a plasma CVD method using silane (SiH ₄ ) gas. The method for manufacturing a semiconductor memory device according to claim 3, further comprising a heat treatment step of performing a heat treatment in a hydrogen atmosphere after the step of forming the multilayer insulating film. A transistor formed on a semiconductor substrate; an interlayer insulating film on the transistor; and a capacitor having a lower electrode connected to one impurity region of the transistor through a contact hole formed in the interlayer insulating film. A semiconductor memory device,
A hydrogen-containing insulating film whose lower end is in contact with one impurity region of the transistor is formed on the inner wall of the contact hole of the interlayer insulating film, and the one impurity is inside the contact hole surrounded by the hydrogen-containing insulating film. A semiconductor memory device in which a conductive plug connecting the region and the lower electrode of the capacitor on the interlayer insulating film is formed. The semiconductor memory device according to claim 8, wherein the interlayer insulating film includes a plurality of insulating films including a hydrogen-containing insulating film. A multilayer insulating film in which two types of insulating films made of a hydrogen-containing insulating film and having different etching rates are alternately stacked is formed on the interlayer insulating film,
The capacitor is
A lower electrode formed in the trench of the multilayer insulating film and connected to the one impurity region via the contact;
A capacitor dielectric film on the lower electrode;
The semiconductor memory device according to claim 8, further comprising: an upper electrode on the capacitor dielectric film.

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