CN112490192A - Dynamic random access memory and preparation method thereof - Google Patents
Dynamic random access memory and preparation method thereof Download PDFInfo
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- CN112490192A CN112490192A CN201910866415.XA CN201910866415A CN112490192A CN 112490192 A CN112490192 A CN 112490192A CN 201910866415 A CN201910866415 A CN 201910866415A CN 112490192 A CN112490192 A CN 112490192A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
A method for fabricating a dynamic random access memory, comprising: providing a conductive layer and a plurality of contact plugs formed in the conductive layer at intervals, wherein the conductive layer comprises contact surfaces, each contact plug partially protrudes out of the contact surfaces, and each contact plug comprises a top surface and a side surface which are protruded on the contact surfaces; forming a barrier layer on the conductive layer and the contact plug; forming a dielectric layer on one side of the barrier layer, which is far away from the conductive layer; etching the dielectric layer and the barrier layer to form a plurality of grooves until the conductive layer is exposed, wherein each groove is positioned between two adjacent contact plugs; and forming an electrode layer on the hole wall of each groove to connect with the conductive layer. The invention also provides a memory prepared by the method. The above mode can ensure the stability of each electrode layer in the subsequent groove and the enough contact connection area with the conductive layer.
Description
Technical Field
The invention relates to a dynamic random access memory and a preparation method thereof, in particular to a capacitor applied to the dynamic random access memory and a preparation method thereof.
Background
Each memory cell of a dynamic random access memory comprises a selection transistor and a capacitor connected in series with the selection transistor. In order to achieve a large capacitance, the capacitor in the memory cell must be further miniaturized, which results in insufficient electrode area of the capacitor and failure to increase the capacitance. In order to increase the capacitance of the memory cell, the electrode area of the capacitor needs to be increased in a limited space. The existing method for increasing the electrode area of the capacitor is as follows: the insulating layer is arranged above the conducting layer, a groove penetrating through the insulating layer is formed in the insulating layer, and the electrode is formed on the groove wall of the groove to increase the area of the electrode.
Disclosure of Invention
Therefore, it is desirable to provide a method for fabricating a dynamic random access memory, which can effectively solve the above problems.
A method for preparing a dynamic random access memory comprises the following steps:
providing a conductive layer and a plurality of contact plugs formed in the conductive layer at intervals, wherein the conductive layer comprises a contact surface, each contact plug partially protrudes out of the contact surface, each contact plug comprises a top surface and a side surface, the top surface and the side surface are protruded on the contact surface, the side surface is connected with the contact surface, and the top surface is far away from the conductive layer and is connected with the side surface;
forming a barrier layer on the conductive layer and the contact plugs, the barrier layer covering the contact surfaces and the top and side surfaces of each contact plug;
forming a dielectric layer on one side of the barrier layer far away from the conductive layer;
etching the dielectric layer and the barrier layer to form a plurality of grooves until the conductive layer is exposed, wherein each groove is positioned between two adjacent contact plugs; and
and forming an electrode layer on the hole wall of each groove to be connected with the conductive layer.
In addition, it is also necessary to provide a dynamic random access memory, which includes:
the conductive layer comprises a contact surface, each contact plug partially protrudes out of the contact surface, each contact plug comprises a top surface and a side surface, the top surface is protruded on the contact surface, the side surface is connected with the contact surface, and the top surface is far away from the conductive layer and is connected with the side surface;
the dielectric layer is at least positioned on the conducting layer, a plurality of grooves are formed in the dielectric layer, each groove is positioned between two adjacent contact plugs, and the bottom walls of the grooves are contact surfaces; and
a barrier layer at least arranged between the top surface of each contact plug and the dielectric layer; and
and the electrode layer covers the hole wall of each groove and is connected with the conductive layer.
According to the preparation method, the contact plugs are arranged in a protruding mode relative to the conductive layer, so that whether the groove obtained by etching the dielectric layer subsequently faces or deviates from the position between two adjacent contact plugs, the stability of each electrode layer in the subsequent groove and the enough uniform contact connection area between the electrode layer and the conductive layer can be guaranteed.
Drawings
Fig. 1 is a flow chart of a method of manufacturing a semiconductor device of the present invention.
Fig. 2A to fig. 2C are first schematic diagrams illustrating a method for manufacturing a semiconductor device.
Fig. 3A to fig. 3B are second schematic diagrams illustrating a manufacturing method of the semiconductor device according to the first embodiment.
Fig. 4 is a third schematic view of the manufacturing method of the semiconductor device of the first embodiment.
Fig. 5A to 5B are second diagrams illustrating a manufacturing method of a semiconductor device according to a second embodiment.
Fig. 6 is a third schematic view of the manufacturing method of the semiconductor device of the second embodiment.
Description of the main elements
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The present invention will be further described with reference to the accompanying drawings.
Detailed Description
While the embodiments of the invention are illustrated in the drawings, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions may be exaggerated for clarity.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 shows a method for manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device of the present invention is a capacitor of a dynamic random access memory. The manufacturing method of the invention mainly relates to the manufacturing of the capacitor of the dynamic random access memory, and the manufacturing method of other parts of the dynamic random access memory is not correspondingly described in the invention. The preparation method comprises the following steps.
Step S1: as shown in fig. 2A, a conductive layer 10 and a plurality of contact plugs (contact plugs) 20 formed in the conductive layer 10 at intervals are provided.
As shown in fig. 2A, the conductive layer 10 includes a contact surface 11, and each contact plug 20 partially protrudes out of the contact surface 11 of the conductive layer 10. Each contact plug 20 comprises a top surface 21 protruding above the contact surface 11 and a side surface 23 connecting the top surface 21, the side surface 23 being connected to the contact surface 11, the top surface 21 being remote from the conductive layer 10. In this way, the contact surface 11 of the conductive layer 10 and the contact plug 20 cooperate to form an uneven profile.
In one embodiment, the formation of the conductive layer 10 and the plurality of contact plugs 20 protruding from the conductive layer 10 may include the following steps: forming a plurality of contact plugs 20, and then forming an initial conductive layer (not shown) between the contact plugs 20, the initial conductive layer completely covering the contact plugs 20; then, the initial conductive layer is etched to obtain the conductive layer 10, so that the contact plug 20 is protruded from the conductive layer 10.
In another embodiment, the formation of the conductive layer 10 and the plurality of contact plugs 20 protruding from the conductive layer 10 may also include the following steps: forming a complete initial conductive layer (not shown), etching the initial conductive layer to form a conductive layer 10 having a receiving hole (not shown), forming a dielectric layer 50 (not shown) on the conductive layer 10, the dielectric layer 50 entering the receiving hole, and etching a portion of the dielectric layer 50 to form a plurality of contact plugs 20 spaced apart from each other on the dielectric layer 50 and to make the contact plugs 20 protrude from the conductive layer 10.
It is to be understood that the formation of the conductive layer 10 and the plurality of contact plugs 20 protruding from the conductive layer 10 is not limited to the above two methods, and may be formed in other various methods.
In this embodiment, the conductive layer 10 is made of a conductive metal, such as metal tungsten. The contact plug 20 is made of an insulating material, such as silicon nitride or silicon boron nitride.
As shown in fig. 2A, in the present embodiment, each contact plug 20 includes a first portion 210 and a second portion 220 connected to the first portion 210, wherein the first portion 210 penetrates the contact surface 11, and the second portion 220 is thinner than the first portion 210.
It is understood that the conductive layer 10 and the plurality of contact plugs 20 are carried by a substrate (not shown), and various other components and circuits (not shown) are disposed between the substrate and the conductive layer 10.
Step S2: as shown in fig. 2B, a barrier layer 30 is formed on the conductive layer 10 and the contact plug 20. The barrier layer 30 covers the contact surface 11 and the top surface 21 and the side surfaces 23 of each contact plug 20.
The barrier layer 30 may be formed in a conventional manner, such as coating, ink jet, physical vapor deposition (sputtering), chemical vapor deposition, and the like. The barrier layer 30 has a thinner thickness with respect to the contact plug 20; the barrier layer 30 matches the rugged profile formed by the contact surface 11 and the contact plug 20, and itself also has a rugged profile.
The material of the barrier layer 30 is an insulating material, such as silicon nitride. In one embodiment, the barrier layer 30 and the contact plug 20 are made of the same silicon nitride material.
Step S3: as shown in fig. 2C, a dielectric layer 50 is formed on the side of the barrier layer 30 away from the conductive layer 10.
The dielectric layer 50 may be formed in a conventional manner, such as, for example, coating, ink jet, physical vapor deposition (sputtering), chemical vapor deposition, and the like. As shown in fig. 2C, the dielectric layer 50 has a relatively large thickness with respect to the conductive layer 10 and the barrier layer 30. The dielectric layer 50 is an insulating material, such as silicon oxide.
Step S4: referring to fig. 3A, the dielectric layer 50 and the barrier layer 30 are etched to form a plurality of grooves 51 until the conductive layer 10 is exposed.
The etching mode can adopt the conventional dry etching in the field and adopts etching gas for etching; or wet etching, and etching with an etching solution. The portion of the barrier layer 30 covering the contact surface 11 and the portion of the dielectric layer 50 above the portion of the barrier layer 30 during the etching will be etched away to form a recess 51.
As shown in fig. 3A, the opening size of each groove 51 becomes gradually larger as directed from the conductive layer 10 to a direction away from the conductive layer 10.
As shown in fig. 3A, when each of the recesses 51 is etched to be disposed right opposite to a position between two contact plugs 20 adjacent thereto, that is, a center point of a bottom wall of the recess 51 substantially coincides with a center point between two adjacent contact plugs 20.
As shown in fig. 3A, the barrier layer 30 covering the top surface 21 and the side surface 23 of the contact plug 20 is not removed during the process of etching to form the recess 51. In this case, the method further comprises the steps of: as shown in fig. 3B, the barrier layer 30 is etched to remove the portion covering the top surface 21, so that the side surface 23 of the contact plug 20 is exposed, and the space left by removing the barrier layer 30 is formed as a card slot 510, which corresponds to two card slots 510 formed in each of the grooves 51 near the bottom of the conductive layer 10 and communicating with the groove 51. The barrier layer 30 that remains finally covers only the top surface 21 of the contact plug 20 and does not cover other areas, for example the side surfaces 23 of the contact plug.
Fig. 3A and 3B described above show the case where each of the recesses 51 is etched to face the position between two contact plugs 20 adjacent thereto. However, during the etching, there is a high possibility that an undesirable situation may occur, for example, each of the recesses 51 is not directly opposed to a position between two contact plugs 20 adjacent thereto, and the center point of the bottom wall of the recess 51 is relatively deviated from the midpoint between two contact plugs 20 adjacent to the recess 51, as shown in fig. 5A and 5B.
As shown in fig. 5A, when each of the recesses 51 is not disposed directly opposite to a position between two contact plugs 20 adjacent thereto, that is, the center point of the bottom wall of the recess 51 is offset relative to the center point between two adjacent contact plugs 20.
As shown in fig. 5A, each of the contact plugs 20 has two opposite side surfaces 23; in the process of forming the recess 51 by etching, the barrier layer 30 covered on one side surface 23 of each contact plug 20 is completely removed, and the barrier layer 30 covered on the other side surface 23 and the top surface 21 is not removed. That is, the barrier layer 30 covering the top surface 21 and one of the side surfaces 23 of the contact plug 20 is not removed during the etching process to form the recess 51. In this case, the method further comprises: as shown in fig. 5B, a portion of the barrier layer 30 between the dielectric layer 50 and the top surface 21 of the corresponding contact plug 20 is etched to form a first card slot 511 communicating with the recess 51, and a portion of the barrier layer 30 covering the contact surface 11 is etched to form a second card slot 513 communicating with the recess 51.
Step S5: referring to fig. 4, an electrode layer 60 is formed on the wall of each groove 51 to connect with the conductive layer 10. The electrode layer 60 is made of a conductive material, such as titanium nitride.
The electrode layer 60 can be formed in a conventional manner, such as coating, ink jet, physical vapor deposition (sputtering), chemical vapor deposition, and the like.
Wherein fig. 4 is a schematic diagram of the steps following fig. 3B. As shown in fig. 4, in the step of forming the electrode layer 60, the electrode layer 60 enters and fills the card slot 510, i.e., covers the side 23 of the contact plug 20. The portion of the electrode layer 60 filling the clamping groove 510 can make the electrode layer 60 more firmly attached to the groove wall of the groove 51, and at the same time, ensure that the electrode layer 60 in each groove 51 has a sufficient uniform contact connection area with the conductive layer 10.
Fig. 6 is a schematic diagram of another embodiment of forming an electrode layer 60, which follows the steps in fig. 5B. As shown in fig. 6, in the step of forming the electrode layer 60, the electrode layer 60 enters and fills the first and second card slots 511 and 513. In this way, although the recess 51 is offset from the position between two adjacent contact plugs 20, the portion of the electrode layer 60 filling the first slot 511 and the second slot 513 makes the electrode layer 60 more firmly attached to the slot walls of the recess 51, and ensures that the electrode layer 60 in each recess 51 has a sufficient uniform contact connection area with the conductive layer 10.
According to the manufacturing method of the capacitor of the dynamic random access memory, the contact plugs 20 are arranged to be protruded relative to the conductive layer 10, so that when the dielectric layer 50 is etched subsequently to obtain a plurality of grooves 51, no matter whether the position between each groove 51 and two adjacent contact plugs 20 is in a state of being over-aligned or offset, the blocking layer 30 can be removed by etching to form the card slot 510 (or the first card slot 511 and the second card slot 513) communicated with the groove 51, and the electrode layer 60 attached to the wall of each groove 51 enters and fills the card slot 510 (or the first card slot 511 and the second card slot 513), so that the stability of each electrode layer 60 in the subsequent groove 51 and the sufficient uniform contact connection area with the conductive layer are ensured.
As shown in fig. 4, the dynamic random access memory according to the first embodiment of the present invention includes a conductive layer 10 and a plurality of contact plugs 20 spaced apart from each other in the conductive layer 10. The conductive layer 10 comprises a contact surface 11. Each contact plug 20 projects partly out of the contact face 11 of the conductive layer 10. Each contact plug 20 comprises a top surface 21 and a side surface 23 that project above the contact surface 11. The side surface 23 is connected to the contact surface 11, and the top surface 21 is remote from the conductive layer 10 and is connected to the side surface 23.
Each contact plug 20 comprises a first portion 210 and a second portion 220 connected to the first portion 210, wherein the first portion 210 extends through the contact surface 11 and the second portion 220 is thinner than the first portion 210.
In this embodiment, the conductive layer 10 is made of a conductive metal, such as metal tungsten. The contact plug 20 is made of an insulating material, such as silicon nitride or silicon boron nitride.
The dynamic random access memory of the present invention further comprises a dielectric layer 50, a barrier layer 30, and an electrode layer 60. The material of the barrier layer 30 is an insulating material, such as silicon nitride. In one embodiment, the barrier layer 30 and the contact plug 20 are made of the same silicon nitride material. The dielectric layer 50 is an insulating material, such as silicon oxide. The electrode layer 60 is made of a conductive material, such as titanium nitride.
A plurality of grooves 51 are opened in the dielectric layer 50 to expose the conductive layer 10. The bottom wall of the groove 51 is the contact surface 11. Each of the recesses 51 is located between adjacent two of the contact plugs 20. The opening of each recess 51 is gradually larger in size from the conductive layer 10 toward a direction away from the conductive layer 10.
The barrier layer 30 is disposed between the top surface 21 of each contact plug 20 and the dielectric layer 50. The electrode layer 60 covers the hole wall of each groove 51 and is connected to the conductive layer 10.
As shown in fig. 4, each of the grooves 51 is disposed opposite to a position between two contact plugs 20 adjacent thereto, and the electrode layer 60 covers and directly contacts the side surfaces 23 of the contact plugs 20.
As shown in fig. 6, the dynamic random access memory according to the second embodiment of the present invention is different from the first embodiment in that: each groove 51 is not arranged opposite to the position between two adjacent contact plugs 20, a first clamping groove 511 which is communicated with the groove 51 is formed between the dielectric layer 50 and the top surface 21 of the corresponding contact plug 20, a second clamping groove 513 which is communicated with the groove 51 is formed between the dielectric layer 50 and the barrier layer 30 and the contact surface 11, and the electrode layer 60 fills the first clamping groove 511 and the second clamping groove 513.
The above embodiments are only intended to illustrate the technical solution of the present invention and not to limit, and the up, down, left and right directions shown in the drawings are only for convenience of understanding, although the present invention is described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. A method for manufacturing a dynamic random access memory is characterized in that: which comprises the following steps:
providing a conductive layer and a plurality of contact plugs formed in the conductive layer at intervals, wherein the conductive layer comprises a contact surface, each contact plug partially protrudes out of the contact surface, each contact plug comprises a top surface and a side surface, the top surface and the side surface are protruded on the contact surface, the side surface is connected with the contact surface, and the top surface is far away from the conductive layer and is connected with the side surface;
forming a barrier layer on the conductive layer and the contact plugs, the barrier layer covering the contact surfaces and the top and side surfaces of each contact plug;
forming a dielectric layer on one side of the barrier layer far away from the conductive layer;
etching the dielectric layer and the barrier layer to form a plurality of grooves until the conductive layer is exposed, wherein each groove is positioned between two adjacent contact plugs; and
and forming an electrode layer on the hole wall of each groove to be connected with the conductive layer.
2. The method of claim 1, wherein: the opening size of each groove is gradually increased from the conducting layer to the direction far away from the conducting layer.
3. The method of claim 1, wherein: when each groove is opposite to a position between two adjacent contact plugs, the method further comprises the step of etching and removing the part of the barrier layer, which covers the top surface, to form a clamping groove communicated with the groove before the electrode layer is formed.
4. The method of claim 3, wherein: in the step of forming the electrode layer, the electrode layer enters and fills the card slot.
5. The method of claim 1, wherein: when each groove is not arranged opposite to the position between two adjacent contact plugs, the method further comprises the steps of etching and removing the part, located on the top surfaces of the dielectric layers and the corresponding contact plugs, of the barrier layers to form a first clamping groove communicated with the groove and etching and removing the part, located on the contact surfaces, of the barrier layers to form a second clamping groove communicated with the groove before the electrode layers are formed.
6. The method of claim 5, wherein: in the step of forming the electrode layer, the electrode layer enters and fills the first and second card slots.
7. A dynamic random access memory, comprising: it includes:
the conductive layer comprises a contact surface, each contact plug partially protrudes out of the contact surface, each contact plug comprises a top surface and a side surface, the top surface is protruded on the contact surface, the side surface is connected with the contact surface, and the top surface is far away from the conductive layer and is connected with the side surface;
the dielectric layer is at least positioned on the conducting layer, a plurality of grooves are formed in the dielectric layer, each groove is positioned between two adjacent contact plugs, and the bottom walls of the grooves are contact surfaces; and
a barrier layer at least arranged between the top surface of each contact plug and the dielectric layer; and
and the electrode layer covers the hole wall of each groove and is connected with the conductive layer.
8. The dynamic random access memory of claim 7, wherein: the opening size of each groove is gradually increased from the conducting layer to the direction far away from the conducting layer.
9. The dynamic random access memory according to claim 7, wherein when each of the grooves is disposed opposite to a position between two contact plugs adjacent thereto, the electrode layer covers and directly contacts a side surface of the contact plug.
10. The dynamic random access memory of claim 7, wherein when each recess is not disposed opposite to each other between two adjacent contact plugs, a first slot is formed between the dielectric layer and the top surface of the contact plug and is communicated with the recess, a second slot is formed between the dielectric layer and the barrier layer and is communicated with the recess, and the electrode layer fills the first slot and the second slot.
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