KR101004527B1 - Method of fabricating semiconductor apparatus and semiconductor apparatus fabricated thereby - Google Patents

Abstract

The present invention provides a method for manufacturing a semiconductor device which can prevent contact failure due to a process error or increase leakage current when forming a unit cell in a highly integrated semiconductor device and stably maintain the depth of implanted ions during ion implantation. . A method of manufacturing a semiconductor device according to the present invention includes forming a first hard mask film in a region other than a local damascene region and forming a recess gate in a gate region including the local damascene region.

Semiconductors, Pin Transistors, Recess Gate Electrodes

Description

TECHNICAL FIELD OF THE INVENTION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS FABRICATED THEREBY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a unit cell that operates stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. The transistor is composed of three regions: a gate, a source, and a drain, and charge transfer between the source and the drain occurs according to a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of the semiconductor memory device increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller. That is, the design rules of the capacitors and transistors included in the unit cell have been reduced. As a result, the channel length of the cell transistors has gradually decreased, and thus, short channel effects and drain induced barrier lower (DIBL) effects have been applied to conventional transistors. Occurred, and the reliability of the operation was deteriorated. Phenomena that occur as the channel length decreases can be overcome by maintaining the threshold voltage so that the cell transistor can perform normal operation. Typically, the shorter the channel of the transistor, the higher the doping concentration of impurities in the region where the channel is formed.

However, as the design rule decreases below 100 nm, increasing the doping concentration in the channel region further increases the electric field at the storage node (SN) junction, which deteriorates the refresh characteristics of the semiconductor memory device. Cause. To overcome this problem, a cell transistor having a three-dimensional channel structure having a long channel length in the vertical direction is used to maintain the channel length of the cell transistor even if the design rule is reduced. That is, even if the channel width in the horizontal direction is short, the doping concentration can be reduced by securing the channel length in the vertical direction, thereby preventing the refresh characteristics from deteriorating. Hereinafter, a structure and a manufacturing process of a transistor including a recess gate used as a cell transistor having a three-dimensional channel structure will be described.

1A and 1B are plan views illustrating the structure of a unit cell of a conventional semiconductor memory device.

The unit cell of the semiconductor memory device may be divided into an 8F ² unit cell shown in FIG. 1A and a 6F ² unit cell shown in FIG. 1B according to size. Here, 8F ² unit cell is the side length of 4F (where, F is a minimum pattern line width according to design rules), it means the unit cell is formed in a plane other side length of 2F and, 6F ² unit cell side length of 3F, It means that the unit cell is formed in the plane of the other side length 2F.

1A and 1B, the active region (source / drain region) of the unit cell is formed in the horizontal direction, and the active region is defined by the device isolation film formed in the other region. In addition, a bit line in a horizontal direction is formed on the active region. On the other hand, a recess gate is formed in the vertical direction and a word line is formed on the recess gate. At this time, an isolation insulating layer recess for forming a gate is not formed in the isolation insulating region between the active regions in the horizontal direction. To this end, the contact mask for forming the local damascene region is removed to form only the portions that are not the local damascene region to expose the active regions among the remaining regions other than the local damascene region.

As shown in FIG. 1A, in a cell array including unit cells having a size of 8F ² , a recess gate is formed only in a local damascene region and is designed to cross one active region. In contrast, in the cell array including unit cells having a size of 6F ² shown in FIG. 1B, one recess gate formed in the local damascene region is designed to cross two active regions. In both unit cells having sizes of 8F ² and 6F ^2, the recess gates formed in the local damascene region are connected to each other through a line-shaped word line formed thereon. Hereinafter, a method of forming a cell array including unit cells having a size of 6F ² illustrated in FIG. 1B will be described in more detail.

2A to 2O are perspective views illustrating a method of manufacturing a saddle-type fin transistor of a conventional semiconductor device using the mask pattern shown in FIG. 1.

As shown in FIG. 2A, a pad oxide film 204 and a pad nitride film 206 are formed over the semiconductor substrate 202. The pad nitride film 206 is typically formed by depositing SiN.

Referring to FIG. 2B, after the first photoresist film (not shown) is applied on the pad nitride film 204, an exposure process using an active mask is performed to pattern the first photoresist film to remain in the portion where the active region is to be formed. Thereafter, the pad nitride film 206 and the pad oxide film 204 exposed between the patterns of the first photoresist film are etched to remove the photoresist pattern.

As illustrated in FIG. 2C, a trench is formed by etching the semiconductor substrate 202 using the pad oxide film 204 and the pad nitride film 206 remaining in the portion where the active region is to be formed as an etching mask. The trench thus formed is filled with an isolation oxide film 208 as shown in FIG. 2D and then planarized by chemical mechanical polishing (CMP).

Referring to FIG. 2E, after applying the second photoresist layer 210 on the planarized pad nitride layer 206 and the isolation oxide layer 208, the second photoresist layer 210 is formed by using a mask for forming a local damascene region. Pattern. In this case, the mask exposes between the active regions to the remaining regions other than the local damascene region as described with reference to FIG. 1B.

Referring to FIG. 2F, the isolation oxide layer 208 is etched by the thickness of the pad nitride layer 206 and the pad oxide layer 204 in the region exposed by the patterned second photoresist layer 210. Thereafter, the second photosensitive film 210 is removed. Here, the local damascene region is a recessed region for forming the gate electrode, as shown in FIG. 1B, and is not exposed by the second photoresist layer 210, so that the isolation oxide layer 208 is not etched.

Thereafter, as shown in FIG. 2G, the nitride film 212 is formed in both the local damascene region and the other regions. In this case, the nitride film 212 may be made of SiN like the pad nitride film 206. After formation of the nitride film 212, as shown in FIG. 2H, the chemical mechanical polishing process (CMP) is performed and planarized until the isolation oxide film 208 and the pad nitride film 206 are exposed. As a result, the nitride film 212 remains in the region exposed by the mask shown in FIG. 1B.

As shown in FIG. 2I, a third photoresist layer 214 is formed on the planarized pad nitride layer 206, the isolation oxide layer 208, and the nitride layer 212, and then a fin forming mask having a line shape is used. Thus, patterning is performed to remove the third photosensitive film 214 corresponding to the portion where the fin region of the cell transistor is to be formed. Based on the patterned third photoresist 214, the exposed isolation oxide 208 is etched as shown in FIG. 2J. In this process, the exposed isolation oxide 208 that is not covered by the third photoresist 214 is etched by the height corresponding to the height of the fin region, while the exposed nitride layer 212 is not etched to lower the nitride layer 212. The isolation oxide film 208 remains at the same height as the semiconductor substrate 202.

Thereafter, after removing the third photoresist layer 214 patterned on the pad nitride layer 206 as shown in FIG. 2K, the pad nitride layer 206 and the pad are exposed to expose the semiconductor substrate 202 as shown in FIG. 2L. The oxide film 204 is removed.

As shown in FIG. 2M, a gate oxide film (not shown) is grown on the exposed surface of the semiconductor substrate 202, and a polycrystalline silicon layer, which is a conductive material used as a gate lower electrode, is deposited on the gate oxide film. Planarization is performed by a polishing process (CMP). A gate material layer 216 is formed by depositing a gate upper electrode, which is a metal layer, on the polycrystalline silicon layer, and depositing a gate hard mask insulating layer for protecting the gate electrode.

Subsequently, referring to FIG. 2N, after applying the fourth photoresist film (not shown) and partially removing the fourth photoresist film corresponding to the portion where the gate electrode will not be formed using the gate mask, the exposed gate hard mask insulating film and the gate The gate material layer 216 including the upper electrode and the lower gate electrode is etched and patterned. Then, the fourth photoresist film remaining on the patterned gate material layer 216 is removed.

Referring to FIG. 2O, a structure in which a fin region and a gate pattern of a cell transistor correspond to each other may be described. Specifically, in FIG. 2O, the pattern of the gate material layer 216 is transparently illustrated on the upper fin region formed in FIG. 2N, so that the relationship between the semiconductor pattern 202 of the fin region under the patterned gate material layer 216 may be known. Shown to be. In particular, since the recess gate region is formed only in the local damascene region, and the isolation oxide layer 208 of the remaining regions except the local damascene region is not etched, the recess gate region is formed between the lower recess regions of the gate pattern when the gate pattern in the form of a line is formed. It can be seen that disconnected from.

A method for forming a local damascene region in a method for forming a recess gate as described above, that is, a method for forming a local damascene fin cell transistor having a partially recessed gate bottom electrode. 2E-2H, the isolation oxide film 208 is etched between the active regions in the remaining regions except the local damascene region, the nitride film 212 is deposited, and the chemical mechanical polishing for planarization is shown. Further process (CMP) had to be carried out. Therefore, when doping impurities into the well and channel regions of the cell transistor, as shown in FIG. 2H, ion implantation is performed while the pad nitride film 206 covers the upper portion of the active region. As illustrated in 2L, after the pad nitride layer 206 is removed, ion implantation should be performed while the semiconductor substrate 202 is exposed.

First, as shown in FIG. 2H, when ion implantation is performed while the pad nitride film 206 and the nitride film 212 cover the upper portion of the active region, implantation is performed to form a well and a channel region. Since the ions are passed through the pad nitride layer 206 and doped to the semiconductor substrate 202, the ion implanted depth (Rp) becomes shallow during ion implantation, and the energy for larger ion implantation is overcome to overcome this. ) Is required. For this reason, the difficulty of the ion implantation process occurs and there is a disadvantage that the amount of change (ΔRp) of the ion implantation depth may also increase according to energy.

In addition, when ion implantation is performed while the semiconductor substrate 202 is exposed after the pad nitride layer 206 is removed as shown in FIG. 2L, the pad nitride layer 206 over the active region is removed to form an ion implantation depth ( It can be easier to control Rp). However, when the pad nitride film 206 is removed, the isolation oxide film 208 may be further etched due to the ion implantation energy during the ion implantation process. If the exposed isolation oxide layer 208 is etched due to the ion implantation process, alignment errors may occur in the subsequent process of forming a contact or the like. This alignment error causes problems such as a failure in the formation of a self aligned contact (SAC) or an increase in the drain induced drain leakage (GIDL).

Furthermore, the above-described method of forming a fin cell transistor having a partially recessed gate bottom electrode can be used only when manufacturing a fin cell transistor which is generally used, and a saddle-type fin which etches a semiconductor substrate to form a fin region. (Saddle Fin) There is a disadvantage that can not be applied to manufacture a transistor.

In order to solve the above-mentioned problems, the present invention prevents contact failure or leakage current caused by process error when forming a unit cell in a highly integrated semiconductor device, and maintains the depth of implanted ions stably during ion implantation. It provides a way to do it.

The present invention provides a method of manufacturing a semiconductor device, including forming a first hard mask film in a region other than a local damascene region and forming a gate in a gate region including the local damascene region.

Preferably, the method of manufacturing a semiconductor device further includes defining an active region by forming an isolation layer on a semiconductor substrate and forming a well region and a channel region through an ion implantation process in the active region.

Preferably, the forming of the first hard mask layer comprises depositing the first hard mask layer on the device isolation layer and the active region, and forming the first hard mask layer using a mask defining the local damascene region. Etching is included.

Preferably, the mask is characterized in that it is a positive mask or a negative mask defining the local damascene region.

The forming of the gate may include forming a saddle fin channel region by etching the semiconductor substrate and the device isolation layer based on a mask defining the gate region; Forming a gate oxide layer on the fin channel region; And forming a gate pattern on the gate oxide layer.

Preferably, forming the saddle fin channel region comprises: forming a second hard mask layer on the structure including the first hard mask layer, forming an anti-reflection film on the second hard mask layer, Forming a photoresist pattern on the anti-reflection film, etching the anti-reflection film, the second hard mask film by using the photoresist pattern as an etch mask, and etching the semiconductor substrate and the device isolation layer.

Preferably, the first hard mask layer has an etching selectivity different from that of the second hard mask layer.

Preferably, the first hard mask film includes a nitride film, and the second hard mask film includes an amorphous carbon film.

Preferably, the first hard mask film includes an amorphous carbon film, and the second hard mask film includes a nitride film.

The forming of the gate may include forming a fin channel region by etching only an isolation layer based on a mask defining a gate region, forming a gate oxide layer on the fin channel region, and Forming a gate pattern on the gate oxide layer.

The forming of the gate pattern on the gate oxide layer may include depositing a gate lower electrode, depositing a diffusion barrier metal layer on the gate lower electrode, and forming a gate upper electrode on the diffusion barrier metal layer. Depositing.

Preferably, the gate lower electrode includes at least one of a polycrystalline silicon film, a polycrystalline silicon germanium film, a composite material including a polycrystalline silicon film and a polycrystalline silicon germanium film, TiN, TaN, and silicide.

The present invention overcomes the disadvantages of ensuring the ion implantation depth due to the ion implantation performed in a state where a nitride film is formed on the active region in the manufacture of a semiconductor device, and the variation and variation of the ion implantation depth is large in response to the ion implantation energy. It can be suppressed so that there is an advantage to enable efficient control of the ion implantation process.

In addition, the present invention performs an ion implantation process for the formation of a well region and a channel region before the fin shape is formed, so that isolation may occur when ion implantation is performed after the fin shape is formed. The alignment error due to the additional etching of the oxide layer can be prevented, and thus side effects such as a failure of the self-aligned contact and an increase in the drain leakage current caused by the alignment error can be prevented.

Furthermore, the present invention can prevent the device isolation layer from being etched in the remaining region by depositing a hard mask film in the remaining region except the local damascene region during the etching of the device isolation layer and the semiconductor substrate for forming the fin region in the local damascene region. In this case, it is advantageous to facilitate the fabrication of saddle fin (S-Fin) transistors as well as conventional fin (C-Fin) transistors that do not etch the semiconductor substrate when forming the fin region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are plan views illustrating a mask pattern for fabricating a hard mask on a local damascene region in a semiconductor device according to an embodiment of the present invention.

3A and 3B illustrate structures of an active region, a bit line, a recess gate region, and a word line according to the size of a unit cell in a semiconductor device as shown in FIGS. 1A and 1B. On the other hand, in contrast to the mask for forming the nitride film to prevent the local damascene region from being etched during the formation of the recess for forming the gate, the mask used in the present invention has a larger area than the conventional technique in view of the process error. Is specified.

In the conventional case, when forming a recess in which a gate electrode in a local damascene region is formed, an isolation oxide layer formed between adjacent active regions in a region other than the local damascene region is removed and then covered with a nitride layer to prevent etching of the isolation oxide layer. It was not. However, there is a disadvantage in that the operating margin is small in manufacturing a mask for removing some isolation oxide film in the remaining area. However, the present invention uses a method of depositing a hard mask film on the isolation oxide film and the active area so that a recess is not formed between the active areas in the remaining areas except the local damascene area, so that a mask for patterning the hard mask film is used. Designing larger than the area range that prevents the formation of recesses improves operating margins and reduces leakage current in semiconductor devices.

The reason why the active region is not etched in the remaining regions other than the local damascene region is to prevent the recess gate electrode to cover the region where the gate electrode is to be formed and the fin region where the active region intersect to form an unnecessary region. Accordingly, as shown in FIG. 3C, it is also possible to use a mask that covers only the region where the recess is to be formed and covers the other region when manufacturing the unit cell having the size of 8F ² . As a result, in the present invention, the operating margin is increased in the manufacturing process by using a method of depositing a hard mask film on the isolated oxide film instead of forming a nitride film by etching the isolation oxide film in the remaining region.

4A through 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention using the mask pattern shown in FIG. 3B. In particular, FIGS. 4A to 4G showing cross-sectional views on two axes X-X 'and Y-Y' in FIG. 3B illustrate the case where the saddle-type fin transistor is formed as a cell transistor in a semiconductor memory device.

Referring to FIG. 4A, an isolation insulating film 408 is formed in the semiconductor substrate 402 by performing a shallow trench isolation (STI) process. At this time, the STI process is performed in the following manner. First, a pad oxide film and a pad nitride film (not shown) are sequentially stacked on the semiconductor substrate 402 (the oxidation process and the deposition process are performed), followed by an etching process using an active mask defining an active region. A trench is formed in the trench. Thereafter, the insulating insulating film 408 is deposited to fill the trench, and then a chemical mechanical polishing process (CMP) is performed to expose the pad nitride film, and the insulating insulating film 408 remains inside the trench. Thereafter, the exposed pad nitride film and the pad oxide film are sequentially removed.

Thereafter, a buffer oxide layer 405 is formed on the exposed semiconductor substrate 402. After the formation of the buffer oxide film 405, an exposure process using an ion implantation mask is performed to selectively remove the first photoresist film (not shown) in the region to be implanted with ions. Thereafter, ion implantation is performed to dope the wells and the channel regions in the semiconductor substrate 402 and to remove the remaining first photoresist layer.

Referring to FIG. 4B, a first hard mask film 412 is deposited on the buffer oxide film 405 and the isolation insulating film 408, and a second photoresist film (not shown) is applied on the first hard mask film 412. After that, the second photoresist layer is patterned through an exposure process using a mask illustrated in FIG. 3B. Thereafter, the exposed first hard mask layer 412 is removed by using the patterned second photoresist layer as an etch mask so that the first hard mask layer 412 remains on the remaining regions except for the local damascene region. After that, the remaining second photoresist film is removed.

A second hard mask layer 413 is formed on the structure including the first hard mask layer 412 as shown in FIG. 4C. After the anti-reflection film 415 is formed on the second hard mask film 413, the third photoresist film 414 is coated. In order to form the fin region, the third photoresist layer 414 is patterned using a mask defining a recess gate region.

Referring to FIG. 4D, the anti-reflection film 415, the second hard mask film 413, the buffer oxide film 405, and the semiconductor substrate 402 and the isolation are exposed using the patterned third photoresist 414 as an etch mask. The insulating film 408 is sequentially etched. In this case, the isolation oxide film or the semiconductor substrate 402 is not etched in the region where the first hard mask film 412 is formed, but only the first hard mask film 412 is slightly etched, which is the first hard mask film 412. This is because the etching rate of the hard mask layer 413, the buffer oxide layer 405, and the semiconductor substrate 402 and the isolation insulating layer 408 is made of a different material than that of the hard mask layer 413, the buffer layer 405, and the insulating layer 408. For example, when the first hard mask film 412 is formed of a nitride film, the second hard mask film 413 may be formed of an amorphous carbon film. In contrast, the first hard mask film 412 may be formed of an amorphous carbon film, and the second hard mask film 413 may be formed of a nitride film. Through this etching process, it is possible to form a saddle-type fin transistor having a fin region formed at a height lower than the height of the insulating insulating layer 408.

Thereafter, as shown in FIG. 4E, all of the first and second hard mask layers 412 and 413 remaining on the buffer oxide layer 405 and the isolation insulating layer 408 are removed.

Referring to FIG. 4F, the exposed buffer oxide layer 405 is removed and the gate oxide layer 417 is formed, and then a gate material layer 416 is deposited on the gate oxide layer 417 and the isolation insulating layer 408. A gate hard mask layer 418 is deposited on the gate material layer 416.

Referring to FIG. 4G, after applying a fourth photoresist film (not shown) and patterning it through an exposure process using a gate mask, the gate hard mask film 418 and the gate exposed using the patterned fourth photoresist film as an etching mask are exposed. The material layer 416 is etched to complete the gate pattern. Although not shown, the gate material layer 416 forms a gate pattern by sequentially depositing a gate lower electrode, a diffusion preventing metal film on the gate lower electrode, and a gate upper electrode on the diffusion preventing metal film instead of one conductive material. You may. In this case, the gate lower electrode may be formed of either a polycrystalline silicon film or a polycrystalline silicon germanium film, and may include both a polycrystalline silicon film and a polycrystalline silicon germanium film. In addition, the gate lower electrode may be formed of any one of TiN, TaN, or silicide.

After the gate pattern is completed, formation of LDD (Lightly Doped Drain) region, formation of sidewall insulating film of gate pattern, cell contact formation, bit line contact and bit line formation to prevent high field phenomenon or pinch-off phenomenon of transistor Processes such as capacitor contact and capacitor formation are performed.

5A through 5G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention using the mask pattern shown in FIG. 3B. In particular, FIGS. 5A to 5G illustrate a case where a conventional Fin (C-Fin) fin transistor is formed as a cell transistor in a semiconductor memory device.

Here, since the process of FIGS. 5A-5C is the same as the process of FIGS. 4A-4C, detailed description is abbreviate | omitted.

Referring to FIG. 5D, unlike the FIG. 4D, the antireflection film 515, the second hard mask film 513, and the buffer oxide film 505 that are exposed by the photoresist pattern 514 are sequentially etched, and the exposed isolation oxide film is sequentially exposed. 508 is etched but the exposed semiconductor substrate 502 is not etched. In this case, similarly to the case of FIG. 4D, the isolation oxide film 508 formed in the local damascene region is protected without being etched by the first hard mask film 512. Unlike the case where the saddle-type fin transistor is formed, the semiconductor substrate 402 is etched. This process is performed by adjusting the thickness or etching selectivity of the first hard mask layer 512 or adjusting the etching conditions. Do not etch this.

5E to 5G, the gate oxide film 517, the gate material layer 516, and the gate hard mask film 518 are formed in a manner similar to that of FIGS. 4E through 4G, and then exposed using a gate mask. The process is performed to complete the gate pattern. After the completion of the gate pattern, a process of forming an LDD region, forming a sidewall insulating film of a gate pattern, forming a cell contact, forming a bit line contact and a bit line, forming a capacitor contact and a capacitor is performed as described above.

In the above-described method of manufacturing a semiconductor device, ion implantation can be performed in a state where a buffer oxide film is formed instead of a nitride film, so that a semiconductor device (ie, a local damascene (LD) fin cell having a partially recessed gate electrode) can be obtained. In the method of manufacturing a semiconductor memory device having a transistor, when a well and a channel region are doped through ion implantation in a state where a nitride film is present, the ion implantation depth Rp is not constant so that the change amount ΔRp The problem of becoming large and having difficulty controlling the ion implantation depth Rp can be eliminated.

In addition, in the present invention, by performing ion implantation after the STI process, when the ion implantation process is performed after removing the nitride layer after forming the fin region of the transistor in the related art, the width of the isolated oxide film etched around the fin region is increased and then contacted. It is possible to improve the problem of causing a defect in the formation process or increased leakage current during operation.

In addition, in the present invention, the hard mask layer may be formed on the remaining regions other than the local damascene region to protect the insulating insulating layer formed in the remaining regions from being etched even in an environment in which the semiconductor substrate is etched to form the recessed fin region. When using a nitride film as in the prior art, it is possible to overcome the difficulty of forming a recessed fin region of the saddle-type fin transistor. In addition, in the present invention, saddle fin (S-Fin) transistors and conventional fin (C-Fin) transistors are selectively selected when the etching of the semiconductor substrate is selectively performed to form a fin region. It can manufacture.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A and 1B are plan views illustrating the structure of a unit cell of a conventional semiconductor memory device.

2A to 2O are perspective views for explaining a method of manufacturing a saddle fin transistor of a conventional semiconductor device using the mask pattern shown in FIG. 1B.

3A to 3C are plan views illustrating a mask pattern for fabricating a hard mask on a local damascene region in a semiconductor device according to an embodiment of the present invention.

4A to 4G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention using the mask pattern shown in FIG. 3B.

5A through 5G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention using the mask pattern shown in FIG. 3B.

Claims (12)

Forming an isolation layer defining an active region on a semiconductor substrate provided with a local damascene region and a region other than the local damascene region; Depositing a first hard mask layer on the device isolation layer and the active region; Etching the first hard mask film to form a first hard mask film pattern in a region other than the local damascene region; Etching the semiconductor substrate and the device isolation layer to form a saddle fin channel region; And Forming a gate pattern on the saddle fin channel region Method for manufacturing a semiconductor device comprising a. The method of claim 1, Forming an isolation layer on the semiconductor substrate to define an active region; And And forming a well region and a channel region in the active region through an ion implantation process. delete delete delete The method of claim 1, Forming the saddle fin channel region Forming a second hard mask layer on the structure including the first hard mask layer; Forming an anti-reflection film on the second hard mask film; Forming a photoresist pattern on the anti-reflection film; And Etching the antireflection film and the second hard mask film using the photoresist pattern as an etching mask; And Etching the semiconductor substrate and the device isolation layer. The method of claim 6, And the first hard mask layer has an etching selectivity different from that of the second hard mask layer. The method of claim 7, wherein And the first hard mask film comprises a nitride film, and the second hard mask film comprises an amorphous carbon film. The method of claim 7, wherein And said first hard mask film comprises an amorphous carbon film and said second hard mask film comprises a nitride film. The method of claim 1, Forming the gate Forming only a fin channel region by etching only the device isolation layer based on the mask defining the gate region; Forming a gate oxide layer on the fin channel region; And Forming a gate pattern on the gate oxide layer. The method of claim 1, Forming the gate pattern Depositing a gate bottom electrode; Depositing a diffusion barrier metal film on the gate lower electrode; And And depositing a gate upper electrode on the diffusion preventing metal film. The method of claim 11, The gate lower electrode includes at least one of a polycrystalline silicon film, a polycrystalline silicon germanium film, a composite material including a polycrystalline silicon film and a polycrystalline silicon germanium film, TiN, TaN, and silicide.

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